Intel and Pentium are registered trademarks of Intel Corporation. I

C is a licensed trademark of Philips Electronics, N.V. American Microsystems, Inc. reserves the right to change the detail specifica-

tions as may be required to permit improvements in the design of its products.

3.4.02

FS6050/FS6051/FS6053/FS6054

Low-Skew Clock Fanout Buffer ICs

ISO9001

1.0 Features

Generates up to eighteen low-skew, non-inverting

clocks from one clock input

Supports up to four SDRAM DIMMs

Uses either I

-bus or SMBus serial interface with

Read and Write capability for individual clock output
control

Output enable pin tristates all clock outputs to facili-

tate board testing

Clock outputs skew-matched to less than 250ps

Less than 5ns propagation delay

Output impedance: 17

at 0.5V

Serial interface I/O meet I

C specifications; all other

I/O are LVTTL/LVCMOS-compatible

Five differerent pin configurations available:

FS6050: 18 clock outputs in a 48-pin SSOP

FS6051: 10 clock outputs in a 28-pin SOIC, SSOP

FS6053: 13 clock outputs in a 28-pin SOIC

FS6054: 14 clock outputs in a 28-pin SOIC

Figure 1: Block Diagram (FS6050)

Serial

Interface

SDRAM_(0:1)

SCL

SDA

CLK_IN

FS6050

SDRAM_(2:3)

SDRAM_(4:5)

SDRAM_(6:7)

SDRAM_(8:9)

SDRAM_(10:11)

SDRAM_(12:13)

SDRAM_(14:15)

SDRAM_16

VSS_I

VDD_I

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VDD

VSS

VDD

SDRAM_17

VSS

VDD

2.0 Description

The FS6050 family of CMOS clock fanout buffer ICs are
designed for high-speed motherboard applications, such
as Intel Pentium

II PC100-based systems with 100MHz

SDRAM.
Up to eighteen buffered, non-inverting clock outputs are
fanned-out from one clock input. Individual clocks are
skew matched to less than 250ps at 100MHz. Multiple
power and ground supplies reduce the effects of supply
noise on device performance.
Under I

C-bus control, individual clock outputs may be

turned on or off. An active-low output enable is available
to force all the clock outputs to a tristate level for system
testing.

Figure 2: Pin Configuration (FS6050)

(
r
es

v
ed)

(
r
es

v
ed)

DRA

VSS

DRA

_14

_15

(
r
es

v
e

(
r
es

v
e

DRA

VSS

_
I
N

DRA

VSS

DRA

VSS

DRA

1
6

VSS

DD_

_10

_11

_13

_12

S_I

_17

_
9

_
8

FS6050

48-pin SSOP

Figure 3: Pin Configuration (FS6051)

_
0

_
1

VSS

_
2

DRA

_
1
4

DRA

_
1
5

_
3

VSS

_
I
N

DRA

1
6

VSS

DD_

DRA

_
1
3

DRA

_
1
2

SS_I

DRA

_
1
7

FS6051

28-pin SOIC, SSOP

Additional pin configurations are noted on Page 2.

3.4.02

FS6050/FS6051/FS6053/FS6054

Low-Skew Clock Fanout Buffer ICs

ISO9001

Table 1: Pin Descriptions

Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI

= Input with Internal Pull-Up; DI

= Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,

DO = Digital Output; P = Power/Ground; # = Active Low pin

PIN (FS6050)

PIN (FS6051)

PIN (FS6053)

PIN (FS6054)

TYPE

NAME

DESCRIPTION

CLK_IN

Clock input for SDRAM clock outputs

SCL

Serial clock input

SDA

Serial data input/output

SDRAM_0

SDRAM_1

SDRAM_2

SDRAM_3

SDRAM_4

SDRAM_5

SDRAM_6

SDRAM_7

SDRAM clock outputs (Byte 0)

SDRAM_8

SDRAM_9

SDRAM_10

SDRAM_11

SDRAM_12

SDRAM_13

SDRAM_14

SDRAM_15

SDRAM clock outputs (Byte 1)

SDRAM_16

SDRAM_17

SDRAM feedback clock outputs (Byte 2)

Output enable tristates all clock outputs when low

3, 7, 12, 16,

20, 29, 33, 37,

42, 46

1, 5, 10, 19,

24, 28

1, 5, 20, 24,

1, 5, 24, 28

VDD

3.3V ± 5% power supply for SDRAM clock buffers

VDD_I

3.3V ± 5% power supply for serial communications

6, 10, 15, 19,

22, 27, 30, 34,

39, 43

4, 8, 12, 17,

21, 25

4, 8, 17, 21,

4, 8, 21, 25

VSS

Ground for SDRAM clock buffers

VSS_I

Ground for serial communications

1, 2, 47, 48

(reserved)

Reserved

Figure 4: Pin Configuration (FS6053)

RAM

_
0

RAM

_
1

VSS

RAM

_
2

VSS

DRA

_
1
4

DRA

_
1
5

RAM

_
3

VSS

I
N

RAM

_
6

RAM

_
7

M_16

DD_

DRA

_
9

DRA

_
1
3

DRA

_
1
2

VSS

VSS_

VSS

DRA

_
8

FS6053

Figure 5: Pin Configuration (FS6054)

DRA

_
0

DRA

_
1

DRA

_
2

VSS

RAM

_
1
4

RAM

_
1
5

DRA

_
3

_
I
N

DRA

_
6

DRA

_
7

DRA

_
1
6

RAM

_
9

RAM

_
1
3

RAM

_
1
2

VSS

VSS_

RAM

_
1
7

RAM

_
8

FS6054

3.4.02

FS6050/FS6051/FS6053/FS6054

Low-Skew Clock Fanout Buffer ICs

ISO9001

3.0 Programming

Information

Table 2: Clock Enable

CONTROL INPUTS

CLOCK OUTPUTS (MHz)

SDRAM_0:17

tristate

CLK_IN

3.1 Power-Up

Initialization

All outputs are enabled and active upon power-up, and all
output control register bits are initialized to one.
The outputs must be configured at power-up and are not
expected to be configured during normal operation. Inac-
tive outputs are held low and are disabled from switching.

3.1.1 Unused

Outputs

Outputs that are not used in versions of this device with a
reduced pinout are still operational internally. To reduce
power dissipation and crosstalk effects from the unloaded
outputs, it is recommended that these outputs be shut off
via the Control Registers.

3.2 Register

Programming

A logic-one written to a valid bit location turns on the as-
signed output clock. Likewise, a logic-zero written to a
valid bit location turns off the assigned output clock.
Any unused or reserved register bits should be cleared to
zero.
Serial bits are written to this device in the order shown in
Table 3.

Table 3: Register Summary

SERIAL BIT

DATA BYTE

CLOCK OUTPUT

(MSB)

SDRAM_7

SDRAM_6

SDRAM_5

SDRAM_4

SDRAM_3

SDRAM_2

Byte 0

SDRAM Control Register 0

SDRAM_1

(LSB)

SDRAM_0

(MSB)

SDRAM_15

SDRAM_14

SDRAM_13

SDRAM_12

SDRAM_11

SDRAM_10

Byte 1

SDRAM Control Register 1

SDRAM_9

(LSB)

SDRAM_8

(MSB)

SDRAM_17

SDRAM_16

Reserved

Byte 2

SDRAM Control Register 2

Reserved

(LSB)

Reserved

3.4.02

FS6050/FS6051/FS6053/FS6054

Low-Skew Clock Fanout Buffer ICs

ISO9001

Table 4: Byte 0 - SDRAM Control Register 0

REGISTER

BIT

CLOCK

OUTPUT

DESCRIPTION

OUTPUT PIN

(FS6050)

OUTPUT PIN

(FS6051)

OUTPUT PIN

(FS6053)

OUTPUT PIN

(FS6054)

SDRAM_7

On (1) / Off (0)

Pin 18

Pin 11

SDRAM_6

On (1) / Off (0)

Pin 17

Pin 10

SDRAM_5

On (1) / Off (0)

Pin 14

SDRAM_4

On (1) / Off (0)

Pin 13

SDRAM_3

On (1) / Off (0)

Pin 9

Pin 7

SDRAM_2

On (1) / Off (0)

Pin 8

Pin 6

SDRAM_1

On (1) / Off (0)

Pin 5

Pin 3

SDRAM_0

On (1) / Off (0)

Pin 4

Pin 2

Table 5: Byte 1 - SDRAM Control Register 1

REGISTER

BIT

CLOCK

OUTPUT

DESCRIPTION

OUTPUT PIN

(FS6050)

OUTPUT PIN

(FS6051)

OUTPUT PIN

(FS6053)

OUTPUT PIN

(FS6054)

SDRAM_15

On (1) / Off (0)

Pin 45

Pin 27

SDRAM_14

On (1) / Off (0)

Pin 44

Pin 26

SDRAM_13

On (1) / Off (0)

Pin 41

Pin 23

SDRAM_12

On (1) / Off (0)

Pin 40

Pin 22

SDRAM_11

On (1) / Off (0)

Pin 36

SDRAM_10

On (1) / Off (0)

Pin 35

SDRAM_9

On (1) / Off (0)

Pin 32

Pin 19

SDRAM_8

On (1) / Off (0)

Pin 31

Pin 18

Table 6: Byte 2 - SDRAM Control Register 2

REGISTER

BIT

CLOCK

OUTPUT

DESCRIPTION

OUTPUT PIN

(FS6050)

OUTPUT PIN

(FS6051)

OUTPUT PIN

(FS6053)

OUTPUT PIN

(FS6054)

SDRAM_17

On (1) / Off (0)

Pin 28

Pin 18

Pin 17

SDRAM_16

On (1) / Off (0)

Pin 21

Pin 11

Pin 12

Reserved (set to 0)

3.4.02

FS6050/FS6051/FS6053/FS6054

Low-Skew Clock Fanout Buffer ICs

ISO9001

4.0 Dual Serial Interface Control

This integrated circuit is a read/write slave device that
supports both the Inter IC Bus (I

C-bus) and the System

Management Bus (SMBus) two-wire serial interface pro-
tocols. The unique device address that is written to the
device determines whether the part expects to receive
SMBus commands or I

C commands. Since SMBus is

derived from the I

C-bus, the protocol for both bus types

is very similar.
In general, the bus has to be controlled by a master de-
vice that generates the serial clock SCL, controls bus
access, and generates the START and STOP conditions
while the device works as a slave. Both master and slave
can operate as a transmitter or receiver, but the master
device determines which mode is activated. A device that
sends data onto the bus is defined as the transmitter, and
a device receiving data as the receiver.
Bus logic levels and timing parameters noted herein fol-
low I

C-bus convention. Logic levels are based on a per-

centage of VDD. A logic-one corresponds to a nominal
voltage of VDD, while a logic-zero corresponds to ground
(VSS).

4.1 Bus

Conditions

Data transfer on the bus can only be initiated when the
bus is not busy. During the data transfer, the data line
(SDA) must remain stable whenever the clock line (SCL)
is high. Changes in the data line when the clock line is
high is interpreted by the device as a START or STOP
condition. Both I

C-bus and SMBus protocols define the

following conditions on the bus. Refer to Figure 12: Bus
Timing Data for more information.

4.1.1 Not

Busy

Both the data (SDA) and clock (SCL) lines remain high to
indicate the bus is not busy.

4.1.2

START Data Transfer

A high to low transition of the SDA line while the SCL in-
put is high indicates a START condition. All commands to
the device must be preceded by a START condition.

4.1.3

STOP Data Transfer

A low to high transition of the SDA line while SCL is held
high indicates a STOP condition. All commands to the
device must be followed by a STOP condition.

4.1.4 Data

Valid

The state of the SDA line represents valid data if the SDA
line is stable for the duration of the high period of the SCL
line after a START condition occurs. The data on the
SDA line must be changed only during the low period of
the SCL signal. There is one clock pulse per data bit.
Each data transfer is initiated by a START condition and
terminated with a STOP condition. The number of data
bytes transferred between START and STOP conditions
is determined by the master device, and can continue
indefinitely. However, data that is overwritten to the de-
vice after the data registers are filled will overflow from
the last register into the first register, then the second,
and so on, in a first-in, first-overwritten fashion.

4.1.5 Acknowledge

When addressed, the receiving device is required to gen-
erate an Acknowledge after each byte is received. The
master device must generate an extra clock pulse to co-
incide with the Acknowledge bit. The acknowledging de-
vice must pull the SDA line low during the high period of
the master acknowledge clock pulse. Setup and hold
times must be taken into account.
The master must signal an end of data to the slave by not
generating an acknowledge bit on the last byte that has
been read (clocked) out of the slave. In this case, the
slave must leave the SDA line high to allow the master to
generate a STOP condition.

4.2

Bus Operation and Commands

All programmable registers can be accessed via the bi-
directional two wire digital interface. The device accepts
the Random Register Read/Write and the Sequential
Register Read/Write I

C commands. The device also

supports the Block Read/Write SMBus commands.

4.2.1 I

C-bus and SMBus Device Addressing

After generating a START condition, the bus master
broadcasts a seven-bit device address followed by a R/W
bit. Note that every device on an I

C-bus or SMBus must

have a unique address to avoid bus conflicts.
For an SMBus interface, the address of the device is:

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Document Outline

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Document Outline

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