American Microsystems, Inc. reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
2.27.02
FS6128-04 / FS6128-05 / FS6128-06
FS6128-04 / FS6128-05 / FS6128-06
FS6128-04 / FS6128-05 / FS6128-06
FS6128-04 / FS6128-05 / FS6128-06
PLL Clock Generator IC with VCXO
PLL Clock Generator IC with VCXO
PLL Clock Generator IC with VCXO
PLL Clock Generator IC with VCXO
ISO9001
ISO9001
ISO9001
ISO9001
1.0 Features
Phase-locked loop (PLL) device synthesizes output
clock frequency from crystal oscillator or external ref-
erence clock
On-chip tunable voltage-controlled crystal oscillator
(VCXO) allows precise system frequency tuning
Typically used for generation of MPEG-2 decoder
clock
3.3V
supply
voltage
Very low phase noise PLL
Use with "pullable" 14pF crystals no external pad-
ding capacitors required
Small circuit board footprint (8-pin 0.150
SOIC)
Custom frequency selections available - contact your
local AMI Sales Representative for more information
Figure 1: Pin Configuration
1
8
2
3
4
7
6
5
XIN
VDD
XTUNE
VSS
VSS
n/c
CLK
XOUT
FS6
128
8-pin (0.150
) SOIC
2.0 Description
The FS6128 is a monolithic CMOS clock generator IC
designed to minimize cost and component count in digital
video/audio systems.
At the core of the FS6128 is circuitry that implements a
voltage-controlled crystal oscillator (VCXO) when an ex-
ternal resonator (nominally 13.5MHz) is attached. The
VCXO allows device frequencies to be precisely adjusted
for use in systems that have frequency matching re-
quirements, such as digital satellite receivers.
A high-resolution phase-locked loop generates an output
clock (CLK) through a post-divider. The CLK frequency is
ratiometrically derived from the VCXO frequency. The
locking of the CLK frequency to other system reference
frequencies can eliminate unpredictable artifacts in video
systems and reduce electromagnetic interference (EMI)
due to frequency harmonic stacking.
Table 1: Crystal / Output Frequencies
DEVICE
f
XIN
(MHz)
CLK (MHz)
FS6128-04
13.500
27.000
FS6128-05
13.500
13.500
FS6128-06
13.500
54.000
NOTE: Contact AMI for custom PLL frequencies
Figure 2: Block Diagram
VCXO
FS6128-04
FS6128-05
FS6128-06
PLL
XOUT
XIN
CLK
XTUNE
DIVIDER
2
2.27.02
FS6128-04 / FS6128-05 / FS6128-06
FS6128-04 / FS6128-05 / FS6128-06
FS6128-04 / FS6128-05 / FS6128-06
FS6128-04 / FS6128-05 / FS6128-06
PLL Clock Generator IC with VCXO
PLL Clock Generator IC with VCXO
PLL Clock Generator IC with VCXO
PLL Clock Generator IC with VCXO
ISO9001
ISO9001
ISO9001
ISO9001
Table 2: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI
U
= Input with Internal Pull-Up; DI
D
= Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active Low pin
PIN
TYPE
NAME
DESCRIPTION
1
AI
XIN
VCXO Feedback
2
P
VDD
Power Supply (+3.3V)
3
AI
XTUNE
VCXO Tune
4
P
VSS
Ground
5
DO
CLK
Clock Output
6
-
n/c
No Connection
7
DO
VSS
Ground
8
AO
XOUT
VCXO Drive
3.0 Functional Block Description
3.1 Voltage-Controlled
Crystal
Oscillator (VCXO)
The VCXO provides a tunable, low-jitter frequency refer-
ence for the rest of the FS6128 system components.
Loading capacitance for the crystal is internal to the
FS6128. No external components (other than the reso-
nator itself) are required for operation of the VCXO.
Continuous fine-tuning of the VCXO frequency is accom-
plished by varying the voltage on the XTUNE pin. The
value of this voltage controls the effective capacitance
presented to the crystal. The actual amount that this load
capacitance change will alter the oscillator frequency de-
pends on the characteristics of the crystal as well as the
oscillator circuit itself.
It is important that the crystal load capacitance is speci-
fied correctly to "center" the tuning range. See Table 5.
A simple formula to obtain the "pulling" capability of a
crystal oscillator is:
(
)
(
) (
)
C
C
C
C
C
C
C
ppm
f
L
L
L
L
1
0
2
0
6
1
2
1
2
10
)
(
+
+
-
=
where:
C
0 =
the shunt (or holder) capacitance of the crystal
C
1 =
the motional capacitance of the crystal
C
L1
and C
L2
= the two extremes (minimum and maximum)
of the applied load capacitance presented by the
FS6128.
EXAMPLE: A crystal with the following parameters is
used: C
1
= 0.025pF and C
0
= 6pF. Using the minimum
and maximum C
L1
= 10pF, and C
L2
= 20pF, the tuning
range (peak-to-peak) is:
(
)
(
) (
)
ppm
.
f
300
10
6
20
6
2
106
10
20
025
0
=
+
+
-
=
.
3.2
Phase-Locked Loop (PLL)
The on-chip PLL is a standard frequency- and phase-
locked loop architecture. The PLL multiplies the reference
oscillator frequency to the desired output frequency by a
ratio of integers. The frequency multiplication is exact
with a zero synthesis error (unless otherwise specified).
3
2.27.02
FS6128-04 / FS6128-05 / FS6128-06
FS6128-04 / FS6128-05 / FS6128-06
FS6128-04 / FS6128-05 / FS6128-06
FS6128-04 / FS6128-05 / FS6128-06
PLL Clock Generator IC with VCXO
PLL Clock Generator IC with VCXO
PLL Clock Generator IC with VCXO
PLL Clock Generator IC with VCXO
ISO9001
ISO9001
ISO9001
ISO9001
4.0 Electrical
Specifications
Table 3: Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at
these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance,
functionality, and reliability.
PARAMETER
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage (V
SS
= ground)
V
DD
V
SS
-0.5
7
V
Input Voltage, dc
V
I
V
SS
-0.5
V
DD
+0.5
V
Output Voltage, dc
V
O
V
SS
-0.5
V
DD
+0.5
V
Input Clamp Current, dc (V
I
< 0 or V
I
> V
DD
)
I
IK
-50
50
mA
Output Clamp Current, dc (V
I
< 0 or V
I
> V
DD
)
I
OK
-50
50
mA
Storage Temperature Range (non-condensing)
T
S
-65
150
C
Ambient Temperature Range, Under Bias
T
A
-55
125
C
Junction Temperature
T
J
125
C
Lead Temperature (soldering, 10s)
260
C
Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7)
2
kV
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy elec-
trostatic discharge.
Table 4: Operating Conditions
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
Supply Voltage
V
DD
3.3V 10%
3.0
3.3
3.6
V
Ambient Operating Temperature Range
T
A
0
70
C
Crystal Resonator Frequency
f
XTAL
Fundamental Mode
12
13.5
18
MHz
4
2.27.02
FS6128-04 / FS6128-05 / FS6128-06
FS6128-04 / FS6128-05 / FS6128-06
FS6128-04 / FS6128-05 / FS6128-06
FS6128-04 / FS6128-05 / FS6128-06
PLL Clock Generator IC with VCXO
PLL Clock Generator IC with VCXO
PLL Clock Generator IC with VCXO
PLL Clock Generator IC with VCXO
ISO9001
ISO9001
ISO9001
ISO9001
Table 5: DC Electrical Specifications
Unless otherwise stated, V
DD
= 3.3V 10%, no load on any output, and ambient temperature range T
A
= 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are
3
from typical. Negative currents indicate current flows out of the device.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
Overall
Supply Current, Dynamic, with Loaded
Outputs
I
DD
f
XTAL
= 13.5MHz; C
L
= 10pF, V
DD
= 3.6V
30
mA
Supply Current, Static
I
DD
XIN = 0V, V
DD
= 3.6V
3
mA
Voltage Controlled Crystal Oscillator (contact factory for approved crystal sources or other application assistance)
Crystal Loading Capacitance at Center
Tuning Voltage
C
L(xtal)
Order crystal for this capacitance (parallel
load) at desired center frequency
14
pF
Crystal Resonator Motional Capacitance
C
1
Specified motional capacitance of the
crystal will affect pullability (see text)
25
fF
XTUNE Effective Range
0
3
V
Synthesized Load Capacitance Min.
C
L1
@V(XTUNE)=minimum value
10
pF
Synthesized Load Capacitance Max.
C
L2
@V(XTUNE)=maximum value
20
pF
VCXO Tuning Range
f
XTAL
= 13.5MHz; C
L(xtal)
= 14pF; C
1(xtal)
= 25fF
(peak-to-peak)
300
ppm
VCXO Tuning Characteristic
Note: positive change of XTUNE =
positive change of VCXO frequency
150
ppm/V
Crystal Drive Level
R
XTAL
=20
; C
L
= 20pF
200
uW
Clock Output (CLK)
High-Level Output Source Current *
I
OH
V
O
= 2.0V
-40
mA
Low-Level Output Sink Current *
I
OL
V
O
= 0.4V
17
mA
z
OH
V
O
= 0.1V
DD
; output driving high
25
Output Impedance *
z
OL
V
O
= 0.1V
DD
; output driving low
25
Short Circuit Source Current *
I
OSH
V
O
= 0V; shorted for 30s, max.
-55
mA
Short Circuit Sink Current *
I
OSL
V
O
= 3.3V; shorted for 30s, max.
55
mA
5
2.27.02
FS6128-04 / FS6128-05 / FS6128-06
FS6128-04 / FS6128-05 / FS6128-06
FS6128-04 / FS6128-05 / FS6128-06
FS6128-04 / FS6128-05 / FS6128-06
PLL Clock Generator IC with VCXO
PLL Clock Generator IC with VCXO
PLL Clock Generator IC with VCXO
PLL Clock Generator IC with VCXO
ISO9001
ISO9001
ISO9001
ISO9001
Table 6: AC Timing Specifications
Unless otherwise stated, V
DD
= 3.3V 10%, no load on any output, and ambient temperature range T
A
= 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are
3
from typical.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
Overall
VCXO Stabilization Time *
t
VCXOSTB
From power valid
10
ms
PLL Stabilization Time *
t
PLLSTB
From VCXO stable
100
us
Synthesis Error
(unless otherwise noted in Frequency Table)
0
ppm
Clock Output (CLK)
Duty Cycle *
Ratio of high pulse width (as measured from rising
edge to next falling edge at V
DD
/2) to one clock period
45
55
%
Jitter, Period (peak-peak) *
t
j(
P)
From rising edge to next rising edge at V
DD
/2, C
L
=
10pF
200
ps
Jitter, Long Term (
y
(
)) *
t
j(LT)
From 0-500
s at V
DD
/2, C
L
= 10pF
compared to ideal clock source
100
ps
Rise Time *
t
r
V
DD
= 3.3V; V
O
= 0.3V to 3.0V; C
L
= 10pF
1.7
ns
Fall Time *
t
f
V
DD
= 3.3V; V
O
= 3.0V to 0.3V; C
L
= 10pF
1.7
ns
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