American Microsystems, Inc. reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
2.28.02
FS6209
FS6209
FS6209
FS6209
Dual PLL VCXO Clock Generator IC
Dual PLL VCXO Clock Generator IC
Dual PLL VCXO Clock Generator IC
Dual PLL VCXO Clock Generator IC
ISO9001
ISO9001
ISO9001
ISO9001
1.0 Features
Dual phase-locked loop (PLL) device two output
clock frequencies
On-chip tunable voltage-controlled crystal oscillator
(VCXO) allows precise system frequency tuning
3.3V
supply
voltage
Small circuit board footprint (8-pin 0.150
SOIC)
Custom frequency selections available - contact your
local AMI Sales Representative for more information
Figure 1: Pin Configuration
1
8
2
3
4
7
6
5
XIN
VDD
XTUNE
VSS
VSS
CLKB
CLKA
XOUT
FS6
209
8-pin (0.150
) SOIC
2.0 Description
The FS6209 is a monolithic CMOS clock generator IC
designed to minimize cost and component count in digital
video/audio systems.
At the core of the FS6209 is circuitry that implements a
voltage-controlled crystal oscillator when an external
resonator (nominally 13.5MHz) is attached. The VCXO
allows device frequencies to be precisely adjusted for use
in systems that have frequency matching requirements,
such as digital satellite receivers.
Two high-resolution phase-locked loops generate two
output clocks (CLKA and CLKB) through an array of post-
dividers. All frequencies are ratiometrically derived from
the VCXO frequency. The locking of all the output fre-
quencies together can eliminate unpredictable artifacts in
video systems and reduce electromagnetic interference
(EMI) due to frequency harmonic stacking.
Table 1: Crystal / Output Frequencies
DEVICE
f
XIN
(MHz)
CLKA (MHz)
CLKB (MHz)
FS6209-01
13.5
54.0000
22.5792
(+1.12ppm)
NOTE: Contact AMI for custom PLL frequencies
Figure 2: Block Diagram
VCXO
FS6209
PLL
XOUT
XIN
CLKB
CLKA
XTUNE
DIVIDER
ARRAY
PLL
2
2.28.02
FS6209
FS6209
FS6209
FS6209
Dual PLL VCXO
Dual PLL VCXO
Dual PLL VCXO
Dual PLL VCXO Clock Generator IC
Clock Generator IC
Clock Generator IC
Clock Generator IC
ISO9001
ISO9001
ISO9001
ISO9001
Table 2: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI
U
= Input with Internal Pull-Up; DI
D
= Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active Low pin
PIN
TYPE
NAME
DESCRIPTION
1
AI
XIN
VCXO Feedback
2
P
VDD
Power Supply (+3.3V)
3
AI
XTUNE
VCXO Tune
4
P
VSS
Ground
5
DO
CLKA
Clock Output A
6
DO
CLKB
Clock Output B
7
DO
VSS
Ground
8
AO
XOUT
VCXO Drive
3.0 Functional Block Description
3.1
Phase-Locked Loop (PLL)
The on-chip PLLs are a standard frequency- and phase-
locked loop architecture. The PLL multiplies the reference
oscillator to the desired frequency by a ratio of integers.
The frequency multiplication is exact with a zero synthe-
sis error.
3.2 Voltage-Controlled
Crystal
Oscillator (VCXO)
The VCXO provides a tunable, low-jitter frequency refer-
ence for the rest of the FS6209 system components.
Loading capacitance for the crystal is internal to the
FS6209. No external components (other than the reso-
nator itself) are required for operation of the VCXO.
Continuous fine-tuning of the VCXO frequency is accom-
plished by varying the voltage on the XTUNE pin. The
total change (from one extreme to the other) in effective
loading capacitance is ??? nominal.
When using a crystal with a VCXO, it is important that the
crystal load capacitance (as specified in Table 4: Oper-
ating Conditions be matched to the load capacitance as
presented by the VCXO. The crystal must be specified
with the correct load capacitance to obtain the maximum
tuning range.
The oscillator operates the crystal resonator in the paral-
lel-resonant mode. Crystal warping, or the "pulling" of the
crystal oscillation frequency, is accomplished by altering
the effective load capacitance presented to the crystal by
the oscillator circuit. The actual amount that changing the
load capacitance alters the oscillator frequency will be
dependent on the characteristics of the crystal as well as
the oscillator circuit itself.
Specifically, the motional capacitance of the crystal (usu-
ally referred to by crystal manufacturers as C
1
), the static
capacitance of the crystal (C
0
), and the load capacitance
(C
L
) of the oscillator determine the warping capability of
the crystal in the oscillator circuit.
A simple formula to obtain the warping capability of a
crystal oscillator is:
(
)
(
) (
)
C
C
C
C
C
C
C
ppm
f
L
L
L
L
1
0
2
0
6
1
2
1
2
10
)
(
+
+
-
=
where C
L1
and C
L2
are the two extremes of the applied
load capacitance.
EXAMPLE: A crystal with the following parameters is
used. With C
1
= 0.02pF, C
0
= 5pF, C
L1
= 10pF, and C
L2
=
22.66pF, the coarse tuning range is
(
)
(
) (
)
ppm
.
.
.
f
305
10
5
66
22
5
2
106
10
66
22
02
0
=
+
+
-
=
.
3
2.28.02
FS6209
FS6209
FS6209
FS6209
Dual PLL VCXO Clock Generator IC
Dual PLL VCXO Clock Generator IC
Dual PLL VCXO Clock Generator IC
Dual PLL VCXO Clock Generator IC
ISO9001
ISO9001
ISO9001
ISO9001
4.0 Electrical
Specifications
Table 3: Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at
these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance,
functionality, and reliability.
PARAMETER
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage (V
SS
= ground)
V
DD
V
SS
-0.5
7
V
Input Voltage, dc
V
I
V
SS
-0.5
V
DD
+0.5
V
Output Voltage, dc
V
O
V
SS
-0.5
V
DD
+0.5
V
Input Clamp Current, dc (V
I
< 0 or V
I
> V
DD
)
I
IK
-50
50
mA
Output Clamp Current, dc (V
I
< 0 or V
I
> V
DD
)
I
OK
-50
50
mA
Storage Temperature Range (non-condensing)
T
S
-65
150
C
Ambient Temperature Range, Under Bias
T
A
-55
125
C
Junction Temperature
T
J
125
C
Lead Temperature (soldering, 10s)
260
C
Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7)
2
kV
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy elec-
trostatic discharge.
Table 4: Operating Conditions
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
Supply Voltage
V
DD
3.3V 10%
3.0
3.3
3.6
V
Ambient Operating Temperature Range
T
A
0
70
C
Crystal Resonator Frequency
f
XTAL
Fundamental Mode
5
13.5
18
MHz
Crystal Resonator Motional Capacitance
C
1(xtal)
AT cut
25
fF
Crystal Loading Capacitance
C
L(xtal)
AT cut
20
pF
4
2.28.02
FS6209
FS6209
FS6209
FS6209
Dual PLL VCXO
Dual PLL VCXO
Dual PLL VCXO
Dual PLL VCXO Clock Generator IC
Clock Generator IC
Clock Generator IC
Clock Generator IC
ISO9001
ISO9001
ISO9001
ISO9001
Table 5: DC Electrical Specifications
Unless otherwise stated, V
DD
= 3.3V 10%, no load on any output, and ambient temperature range T
A
= 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are
3
from typical. Negative currents indicate current flows out of the device.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
Overall
Supply Current, Dynamic, with Loaded
Outputs
I
DD
f
XTAL
= 13.5MHz; C
L
= 10pF, V
DD
= 3.6V
30
mA
Supply Current, Static
I
DD
XIN = 0V, V
DD
= 3.6V
3
mA
Voltage Controlled Crystal Oscillator
Crystal Loading Capacitance
C
L(xtal)
As seen by a crystal connected to XIN and
XOUT (@ V
XTUNE
= 1.65V)
20
pF
Crystal Resonator Motional Capacitance
C
1(xtal)
AT cut
25
fF
VCXO Tuning Range
f
XTAL
= 13.5MHz; C
L(xtal)
= 20pF; C
1(xtal)
= 25fF
300
ppm
VCXO Tuning Characteristic
Note: positive
-
F for positive
-
V
100
ppm/V
Crystal Drive Level
R
XTAL
=20
; C
L
= 20pF
200
uW
Crystal Oscillator Feedback (XIN)
Threshold Bias Voltage
V
TH
860
mV
High-Level Input Current
I
IH
34
A
Low-Level Input Current
I
IL
-21
A
Crystal Oscillator Drive (XOUT)
High-Level Output Source Current
I
OH
V(XIN) = 3.3V, V
O
= 0V
-0.5
mA
Low-Level Output Sink Current
I
OL
V(XIN) = 0V, V
O
= 3.3V
15
mA
Clock Outputs (CLKA, CLKB)
High-Level Output Source Current *
I
OH
V
O
= 2.0V
-40
mA
Low-Level Output Sink Current *
I
OL
V
O
= 0.4V
17
mA
z
OH
V
O
= 0.1V
DD
; output driving high
25
Output Impedance *
z
OL
V
O
= 0.1V
DD
; output driving low
25
Short Circuit Source Current *
I
OSH
V
O
= 0V; shorted for 30s, max.
-55
mA
Short Circuit Sink Current *
I
OSL
V
O
= 3.3V; shorted for 30s, max.
55
mA
5
2.28.02
FS6209
FS6209
FS6209
FS6209
Dual PLL VCXO Clock Generator IC
Dual PLL VCXO Clock Generator IC
Dual PLL VCXO Clock Generator IC
Dual PLL VCXO Clock Generator IC
ISO9001
ISO9001
ISO9001
ISO9001
Table 6: AC Timing Specifications
Unless otherwise stated, V
DD
= 3.3V 10%, no load on any output, and ambient temperature range T
A
= 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are
3
from typical.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
CLOCK
(MHz)
MIN.
TYP.
MAX.
UNITS
Overall
VCXO Stabilization Time *
t
VCXOSTB
From power valid
10
ms
PLL Stabilization Time *
t
PLLSTB
From VCXO stable
500
us
Synthesis Error
(unless otherwise noted in Frequency Table)
0
ppm
Clock Output (CLKA)
Duty Cycle *
Ratio of high pulse width (as measured from rising edge
to next falling edge at V
DD
/2) to one clock period
54.00
45
55
%
Jitter, Period (peak-peak) *
t
j(
P)
From rising edge to next rising edge at
V
DD
/2, C
L
= 10pF
54.00
390
ps
Jitter, Long Term (
y
(
)) *
t
j(LT)
From 0-500
s at V
DD
/2, C
L
= 10pF
compared to ideal clock source
54.00
155
ps
Rise Time *
t
r
V
DD
= 3.3V; V
O
= 0.3V to 3.0V; C
L
= 10pF
1.7
ns
Fall Time *
t
f
V
DD
= 3.3V; V
O
= 3.0V to 0.3V; C
L
= 10pF
1.7
ns
Clock Output (CLKB)
Duty Cycle *
Ratio of high pulse width (as measured from rising edge
to next falling edge at V
DD
/2) to one clock period
22.579
45
55
%
Jitter, Period (peak-peak) *
t
j(
P)
From rising edge to next rising edge at
V
DD
/2, C
L
= 10pF
22.579
290
ps
Jitter, Long Term (
y
(
)) *
t
j(LT)
From 0-500
s at V
DD
/2, C
L
= 10pF
compared to ideal clock source
22.579
450
ps
Rise Time *
t
r
V
DD
= 3.3V; V
O
= 0.3V to 3.0V; C
L
= 10pF
1.7
ns
Fall Time *
t
f
V
DD
= 3.3V; V
O
= 3.0V to 0.3V; C
L
= 10pF
1.7
ns
Figure 3: VCXO Range vs. Tuning Voltage
TBD
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