This document contains information on a preproduction product. Specifications and information herein are subject to change without notice.
2.28.02
FS6219
FS6219
FS6219
FS6219
Dual-VCXO/Triple-PLL Programmable Clock Generator IC
Dual-VCXO/Triple-PLL Programmable Clock Generator IC
Dual-VCXO/Triple-PLL Programmable Clock Generator IC
Dual-VCXO/Triple-PLL Programmable Clock Generator IC
ISO9001
ISO9001
ISO9001
ISO9001
1.0 Features
Two voltage-controlled crystal oscillators (VCXO)
Three fully programmable phase-locked loops (PLL)
Three system clock frequency outputs
I
2
C
-bus serial interface
3.3 volt operation (contact factory for 5 volt versions)
Compact 16-pin SOIC (0.150") package
Figure 1: Pin Configuration
1
16
2
3
4
5
6
7
8
15
14
13
12
11
10
9
XAO
XAI
XTUNEA
SCL
SDA
VDD
ADDR
VSS
CLKA
CLKB
VDD
CLKC
VSS
XTUNEB
XBI
XBO
FS621
9
2.0 Description
The FS6219 is a monolithic CMOS clock generator IC
designed to minimize cost and component count in digital
video / audio systems.
Two fully independent VCXOs permit accurate and
simulaneous phase locking of the generated clocks to
independent sources, such as satellite or cable delivered
video and terrestrial broadcasts.
Three fully independent, fully programmable PLLs with
flexible post-dividers permit the generation of desired
clock frequencies precisely, with no added "synthesis"
errors.
The FS6219 makes use of the latest AMI PLL technology
for low clock period jitter and low cumulative jitter.
The ADDR pin permits two FS6219 to be uniquely con-
trolled by a single I
2
C bus. The full read/write slave
capability of the FS6219 allows all device programming to
be completely verified.
Contact factory for custom requirements.
Figure 2: Device Block Diagram
Crystal
Oscillator
"B"
Crystal
Oscillator
"A"
FS6219
XTUNEA
XAI
XAO
XBI
XBO
XTUNEB
PLL "A"
PLL "B"
PLL "C"
I
2
C Interface
(Read / Write Slave)
SCL
SDA
Source
Select
Source
Select
FPLLA
FPLLB
FXA
FXB
Post-Divider
"A"
Post-Divider
"B"
Post-Divider
"C"
Source
Select
CLKC
CLKB
CLKA
FPLLC
FXA
FXB
2
2.28.02
FS6219
FS6219
FS6219
FS6219
Dual-VCXO/Triple-PLL Programmable Clock Generator IC
Dual-VCXO/Triple-PLL Programmable Clock Generator IC
Dual-VCXO/Triple-PLL Programmable Clock Generator IC
Dual-VCXO/Triple-PLL Programmable Clock Generator IC
ISO9001
ISO9001
ISO9001
ISO9001
Table 1: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI
U
= Input with Internal Pull-Up; DI
D
= Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active Low pin
PIN
TYPE
NAME
DESCRIPTION
1
AO
XAO
Crystal Oscillator "A" Drive
2
AI
XAI
Crystal Oscillator "A" Feedback
3
AI
XTUNEA
Crystal Oscillator "A" Voltage Tuning Input
4
DI
U
SCL
Serial Interface Clock Input
5
DI
U
O
SDA
Serial Interface Data Input/Output
6
P
VDD
Power Supply (+3.3V nominal)
7
DI
U
ADDR
Serial Interface Address Select
8
P
VSS
Ground
9
DO
CLKA
Clock Output "A"
10
DO
CLKB
Clock Output "B"
11
P
VDD
Power Supply (+3.3V nominal)
12
DO
CLKC
Clock Output "C"
13
P
VSS
Ground
14
AI
XTUNEB
Crystal Oscillator "B" Voltage Tuning Input
15
AI
XBI
Crystal Oscillator "B" Feedback
16
AO
XBO
Crystal Oscillator "B" Drive
Note: When applying an external reference clock to the FS6219, it should be capacitively coupled to the XAO or XBO pins. The
XAI and/or XBI pins should be floating (no connection).
FS6219 VCXO Typical Characteristic
-200
-150
-100
-50
0
50
100
150
200
250
0
0.5
1
1.5
2
2.5
3
V(XTUNE) - volts
D
e
v
i
a
t
i
on -
ppm
3
2.28.02
FS6219
FS6219
FS6219
FS6219
Dual-VCXO/Triple-PLL Programmable Clock Generator IC
Dual-VCXO/Triple-PLL Programmable Clock Generator IC
Dual-VCXO/Triple-PLL Programmable Clock Generator IC
Dual-VCXO/Triple-PLL Programmable Clock Generator IC
ISO9001
ISO9001
ISO9001
ISO9001
3.0 Programming
Information
Table 2: Register Map
(Note: All Register Bits are cleared to zero on power-up.)
ADDRESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BYTE 15
*
*
*
*
*
*
*
*
BYTE 14
*
*
*
*
TSCLK_C
STOPCLK_C
SRCCLK_C[2:0]
BYTE 13
*
*
*
*
TSCLK_B
STOPCLK_B
SRCCLK_B[2:0]
BYTE 12
*
*
*
*
TSCLK_A
STOPCLK_A
SRCCLK_A[2:0]
BYTE 11
MODPOST_C[3:0]
SRCPOST_C[2:0]
BYTE 10
MODPOST_B[3:0]
SRCPOST_B[2:0]
BYTE 9
MODPOST_A[3:0]
SRCPOST_A[2:0]
BYTE 8
SRCPLL_C[1:0]
PDPLL_C
LFTC_C
CP_C
FBKDIV_C[10:8] M-Counter
BYTE 7
FBKDIV_C[7:3] M-Counter
FBKDIV_C[2:0] A-Counter
BYTE 6
REFDIV_C[7:0]
BYTE 5
SRCPLL_B[1:0]
PDPLL_B
LFTC_B
CP_B
FBKDIV_B[10:8] M-Counter
BYTE 4
FBKDIV_B[7:3] M-Counter
FBKDIV_B[2:0] A-Counter
BYTE 3
REFDIV_B[7:0]
BYTE 2
SRCPLL_A[1:0]
PDPLL_A
LFTC_A
CP_A
FBKDIV_A[10:8] M-Counter
BYTE 1
FBKDIV_A[7:3] M-Counter
FBKDIV_A[2:0] A-Counter
BYTE 0
REFDIV_A[7:0]
3.1
Control Bit Assignment
If any PLL control bit is altered during device operation,
including those bits controlling the Reference and Feed-
back Dividers, the output frequency will slew smoothly (in
a glitch-free manner) to the new frequency. The slew rate
is related to the programmed charge pump current and
loop filter time constant.
However, any programming changes to any Mux or Post
Divider control bits will cause a glitch on an operating
clock output.
Table 3: PLL Power-Down Bits
NAME
DESCRIPTION
Power-Down PLL "x"
Bit = 0
Power On
PDPLL_x
Bit = 1
Power Off
Table 4: Divider Control Bits
NAME
DESCRIPTION
REFDIV_x[7:0]
REFerence DIVider for PLL "x" (N
R
)
FeedBacK DIVider for PLL "x" (N
F
)
FBKDIV_x[2:0]
A-Counter Value
FBKDIV_x[10:0]
FBKDIV_x[10:3]
M-Counter Value
Table 5: Post-Divider Control Bits
NAME
DESCRIPTION
MODPOST_x[3:0]
Modulus for POST divider "x"
(see Table 7: Post Divider Modulus)
Table 6: CLK Pin Stop Bit
NAME
DESCRIPTION
CLK "x" Stop Bit
Bit=0
Normal, CLK running
STOPCLK_x
Bit=1
CLK Stopped Low
4
2.28.02
FS6219
FS6219
FS6219
FS6219
Dual-VCXO/Triple-PLL Programmable Clock Generator IC
Dual-VCXO/Triple-PLL Programmable Clock Generator IC
Dual-VCXO/Triple-PLL Programmable Clock Generator IC
Dual-VCXO/Triple-PLL Programmable Clock Generator IC
ISO9001
ISO9001
ISO9001
ISO9001
Table 7: Post Divider Modulus
BIT [3]
BIT [2]
BIT [1]
BIT [0]
DIVIDE BY
0
0
0
0
1
0
0
0
1
2
0
0
1
0
3
0
0
1
1
4
0
1
0
0
5
0
1
0
1
6
0
1
1
0
8
0
1
1
1
9
1
0
0
0
10
1
0
0
1
12
1
0
1
0
15
1
0
1
1
16
1
1
0
0
18
1
1
0
1
20
1
1
1
0
25
1
1
1
1
50
Table 8: PLL Reference Source Select Bits
NAME
DESCRIPTION
PLL "A" Reference Source Select
Bit[1]
Bit[0]
0
0
Reference Frequency A
0
1
Reference Frequency B
1
0
PLL B Frequency
SRCPLL_A
1
1
PLL C Frequency
PLL "B" Reference Source Select
Bit[1]
Bit[0]
0
0
Reference Frequency A
0
1
Reference Frequency B
1
0
PLL A Frequency
SRCPLL_B
1
1
PLL C Frequency
PLL "C" Reference Source Select
Bit[1]
Bit[0]
0
0
Reference Frequency A
0
1
Reference Frequency B
1
0
PLL A Frequency
SRCPLL_C
1
1
PLL B Frequency
Table 9: Post-Divider Source Select Bits
NAME
DESCRIPTION
Post-Divider "x" Reference Source Select
Bit[2]
Bit[1]
Bit[0]
0
0
0
Reference Frequency A
0
0
1
Reference Frequency B
0
1
0
PLL A Frequency
0
1
1
PLL B Frequency
1
0
0
PLL C Frequency
SRCPOST_x
1
1
1
Shutdown Post-Divider
Table 10: CLK Pin Source Select Bits
NAME
DESCRIPTION
CLK "x" Source Select
Bit[1]
Bit[0]
0
0
Post-Divider "A"
0
1
Post-Divider "B"
1
0
Post-Divider "C"
SRCCLK_x
1
1
TEST MODE
Table 11: CLK Pin Tri-State Bit
NAME
DESCRIPTION
CLK "x" Source Select
Bit=0
Normal, CLK enabled
TSCLK_x
Bit=1
CLK Tri-Stated
Table 12: PLL Tuning Bits
NAME
DESCRIPTION
Loop Filter Time Constant for PLL "x"
Bit = 0
Time Constant = t.b.d.
LFTC_x
Bit = 1
Time Constant = t.b.d.
Charge Pump Current for PLL"x"
Bit = 0
Current = t.b.d.
CP_x
Bit = 1
Current = t.b.d.
5
2.28.02
FS6219
FS6219
FS6219
FS6219
Dual-VCXO/Triple-PLL Programmable Clock Generator IC
Dual-VCXO/Triple-PLL Programmable Clock Generator IC
Dual-VCXO/Triple-PLL Programmable Clock Generator IC
Dual-VCXO/Triple-PLL Programmable Clock Generator IC
ISO9001
ISO9001
ISO9001
ISO9001
4.0 Electrical
Specifications
Table 13: Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at
these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance,
functionality, and reliability.
PARAMETER
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage (V
SS
= ground)
V
DD
V
SS
-0.5
7
V
Input Voltage, dc
V
I
V
SS
-0.5
V
DD
+0.5
V
Output Voltage, dc
V
O
V
SS
-0.5
V
DD
+0.5
V
Input Clamp Current, dc (V
I
< 0 or V
I
> V
DD
)
I
IK
-50
50
mA
Output Clamp Current, dc (V
I
< 0 or V
I
> V
DD
)
I
OK
-50
50
mA
Storage Temperature Range (non-condensing)
T
S
-65
150
C
Ambient Temperature Range, Under Bias
T
A
-55
125
C
Junction Temperature
T
J
125
C
Lead Temperature (soldering, 10s)
260
C
Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7)
2
kV
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy elec-
trostatic discharge.
Table 14: Operating Conditions
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
Supply Voltage (3.3 volt system)
V
DD
3.0
3.3
3.6
V
Ambient Operating Temperature
Range
T
A
0
70
C
Crystal Resonator Frequency
f
XTAL
Fundamental Mode
5
13.5
18
MHz
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