AMERICAN MICROSYSTEMS, INC.

September 2000

Intel and Pentium are registered trademarks of Intel Corporation. Lexmark is a trademark of Lexmark International, Inc. Non-linear spread spectrum modulation profile is licensed under US Patent
No. 5488627, Lexmark International, Inc. This document contains information on a preproduction product. Specifications and information herein are subject to change without notice.

9.18.00

IntSKS

FS6232

-01

Two-Way MP Motherboard Clock Generator IC

ISO9001

1.0 Features

Generates all clocks required for single and two-way

multi-processor (MP) platforms, including:
M Four differential current-mode Host clock pairs
M Four 66.67MHz 3.3V CK66 clock outputs
M Ten 33.3MHz 3.3V PCI clock outputs
M Two 3.3V Memory Reference clock outputs
M Two 48MHz 3.3V CK48 clock outputs
M Two buffered copies of the crystal reference

Control of current-mode Host clocks via IREF current

programming pin and ISEL_0:1 current multiplier pins

Host clock frequency selection via the SEL_A,

SEL_B, and SEL133/100# pins

Active-low PWR_DWN# signal allows one complete

clock cycle on each clock outputs and then shuts
down the crystal oscillator, PLLs, and outputs

Spread-spectrum modulation (-0.5% at 31.5kHz) of

SSCG PLL clocks, enabled via SS_EN# input

Supports test mode and tristate output control to fa-

cilitate board testing

Available in a 56-pin SSOP and TSSOP

Table 1: Clock Parameters

CLOCK

GROUP

PINS

SUPPLY

VOLTAGE

SUPPLY

GROUP

FREQ.

(MHz)

PHASE

SKEW

(MAX)

HOST_P

0°

HOST_N

3.3V

VDD_H

133.33
100.00

180°

150ps

Pair to

Pair

MREF_P

0°

MREF_N

3.3V

VDD_M

66.67
50.00

180°

CK66

3.3V

VDD_66

66.67

0°

250ps

PCI

3.3V

VDD_P

33.33

0°

300ps

CK48

3.3V

VDD_48

48.008

0°

REF

3.3V

VDD_R

14.318

0°

Table 2: Clock Offsets

RELATION

PHASE

MIN

TYP

MAX

CK66 leads PCI

0°

1.5ns

3.5ns

Figure 1: Block Diagram

Crystal

Oscillator

XOUT

XIN

PWR_DWN#

FS6232

CK66_0:3

adjust

IREF

REF_0:1

VDD_R

VSS_R

ISEL_0:1

÷3

÷4

VSS_M

VDD_M

MREF_P

MREF_N

VDD_66

VSS_66

÷1

÷2

VSS_H

VDD_H

HOST_P1:4

HOST_N1:4

SEL133/100#

SEL_A:B

PCI_0:9

÷2

VDD_P

VSS_P

CK48_0:1

VDD_48

VSS_48

delay

PLL

SSCG

PLL

Control

SS_EN#

Figure 2: Pin Configuration

REF_0 / ISEL_0

VDD_R

VSS_R

XOUT

VSS_P

CK66_3

VSS_66

SEL133/100#

VSS

MREF_P

MREF_N

SS_EN#

HOST_N1

VSS_H

HOST_P2

IREF

6232-

VDD

HOST_P1

XIN

VSS_M

HOST_N2

VDD_66

PWR_DWN#

VDD_H

HOST_N4

HOST_P4

HOST_N3

HOST_P3

VDD_H

VDD_P

i
r
1P

i
r
2P

i
r
3P

i
r
4

REF_1 / ISEL_1

PCI_0

PCI_1

PCI_2

PCI_3

VSS_P

VDD_P

PCI_4

PCI_5

PCI_6

PCI_7

VSS_P

VDD_P

PCI_8

PCI_9

VDD_48

CK48_0 / SEL_A

CK48_1 / SEL_B

VSS_48

CK66_2

CK66_1

CK66_0

VDD_66

VSS_66

VSS_H

VDD_M

AMERICAN MICROSYSTEMS, INC.

September 2000

9.18.00

FS6232-01

Two-Way MP Motherboard Clock Generator IC

ISO9001

Table 3: Pin Descriptions

Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI

= Input with Internal Pull-Up; DI

= Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,

DO = Digital Output; P = Power/Ground; # = Active-low pin

PIN

TYPE

NAME

DESCRIPTION

SUPPLY

CK48_0

One of two 3.3V 48MHz clock outputs, generated from the non-spread PLL

DIO

SEL_A

One of two latched inputs that select the HOST and MREF output frequency

VDD_48

CK48_1

One of two 3.3V 48MHz clock outputs, generated from the non-spread PLL

DIO

SEL_B

One of two latched inputs that select the HOST and MREF output frequency

VDD_48

35, 34, 31, 30

CK66_0:3

Four 3.3V 66.67MHz clock outputs, generated from the spread spectrum PLL

VDD_66

50, 51

HOST_P1
HOST_N1

Host clock pair #1; one of six pairs of current-steering differential current-mode outputs. The
current is established via a reference current at IREF and a multiplying factor set by ISEL_0:1

VDD_H

47, 48

HOST_P2
HOST_N2

Host clock pair #2; one of six pairs of current-steering differential current-mode outputs

VDD_H

44, 45

HOST_P3
HOST_N3

Host clock pair #3; one of six pairs of current-steering differential current-mode outputs

VDD_H

41, 42

HOST_P4
HOST_N4

Host clock pair #4; one of six pairs of current-steering differential current-mode outputs

VDD_H

IREF

A fixed precision resistor from this pin to ground provides a reference current used for the dif-
ferential current-mode HOST clock outputs

VDD

MREF_N

One clock (180° out of phase with MREF_P) in a pair of outputs provided as a reference clock
to a memory clock driver

VDD_M

MREF_P

One clock in a pair of outputs provided as a reference clock to a memory clock driver

VDD_M

8, 9, 11, 12,

14, 15, 17, 18,

20, 21

PCI_0:9

Ten 3.3V 33.3MHz PCI clocks, lagging the CK66 clock by 1.5 to 3.5ns

VDD_P

PWR_DWN#

Asynchronous active-low LVTTL power-down signal shuts down oscillator and PLL, puts all
clocks in low state. Complete clock cycles on all outputs will occur before shut down begins.

VDD_48

REF_0

One of two 3.3V buffered copies of the crystal reference frequency clock

DIO

ISEL_0

One of two latched inputs that select the multiplying factor of the IREF reference current for the
HOST pair outputs

VDD_R

REF_1

One of two 3.3V buffered copies of the crystal reference frequency clock

DIO

ISEL_1

One of two latched inputs that select the multiplying factor of the IREF reference current for the
HOST pair outputs

VDD_R

SEL133/100# Selects 133MHz (logic high) or 100MHz (logic low) Host clock frequency

VDD_48

SS_EN#

Active low spread-spectrum enable turns on spread spectrum modulation

VDD_M

VDD

3.3V core power supply

VDD_48

3.3V power supply for CK48 clock outputs

29, 36

VDD_66

3.3V power supply for CK66 clock outputs

43, 49

VDD_H

3.3V power supply for the differential HOST clock outputs

VDD_M

3.3V power supply for MREF clock outputs

10, 16, 22

VDD_P

3.3V power supply for PCI clock outputs

VDD_R

3.3V power supply for the REF clock output and the crystal oscillator

VSS

Core ground

VSS_48

Ground for the CK48 clock outputs

32, 33

VSS_66

Ground for the CK66 clock outputs

40, 46

VSS_H

Ground for the differential HOST clock outputs

VSS_M

Ground for the MREF clock outputs

7, 13, 19

VSS_P

Ground for the PCI clock outputs

VSS_R

Ground for the REF clock outputs and the crystal oscillator

XIN

14.318MHz crystal oscillator input

VDD_R

XOUT

14.318MHz crystal oscillator output

VDD_R

AMERICAN MICROSYSTEMS, INC.

September 2000

9.18.00

FS6232-01

Two-Way MP Motherboard Clock Generator IC

ISO9001

2.0 Programming Information

Table 4: Function/Clock Enable Configuration

CONTROL INPUTS

CLOCK OUTPUTS (MHz)

PWR_
DWN#

SEL

133/100#

SEL_A

SEL_B

HOST_P

1:4

HOST_N

1:4

MREF_P,

MREF_N

CK66_

0:3

PCI_

0:9

CK48_

0:1

REF

100.00

50.00

66.67

33.33

48.008

14.318

reserved

tristate

133.33

66.67

33.33

48.008

14.318

reserved

XIN ÷ 2

XIN ÷ 4

XIN ÷ 8

XIN ÷ 2

XIN

IREF

tristate

low

Table 5: Synthesis Error

CLOCK

TARGET

(MHz)

ACTUAL

(MHz)

DEVIATION

(ppm)

100.0000

99.9963

-36.657

HOST_P1:4,

HOST_N1:4

133.3333

133.3072

-195.924

50.0000

49.9982

-36.657

MREF_P,

MREF_N

66.6667

66.6536

-195.924

CK66

66.6667

66.6642

-36.657

PCI

33.3333

33.3321

-36.657

CK48

(1)

48.000

48.008

+167

48MHz USB clock is required to be +167ppm off from 48.000MHz to conform to USB
standards.

Spread spectrum is disabled

3.0 HOST Buffer Current Control

The current supplied at the HOST outputs is controlled by
two parameters:
1) the value of the programming resistor from the IREF

pin to ground (VSS), and

2) the multiplier factor determined by the logic setting of

the ISEL_0 and ISEL_1 pins.

3.1 Current

Reference

The HOST output current is a mirrored and scaled copy
of the reference current flowing through the programming
resistor on the IREF pin. Conceptually, the circuit given in
Figure 2 shows how the mirror current is generated.
The voltage that appears at the IREF pin is one-third of
the voltage at the VDD_I pin. The reference current is

IREF

REF

VDD_I

3.2 Current

Scaling

The mirrored reference current can be increased by
adding one or more copies of the mirror current together.
The additional current is controlled by the logic settings
on the ISEL_0 and ISEL_1 pins.

Table 6: Current Multiplier

ISEL_0

ISEL_1

MULTPLIER

= 5

REF

= 6

REF

= 4

REF

= 7

REF

AMERICAN MICROSYSTEMS, INC.

September 2000

9.18.00

FS6232-01

Two-Way MP Motherboard Clock Generator IC

ISO9001

Figure 2: Current Reference Circuit

IREF

Reference

Current I

REF

Mirror
Current

Additional
Mirror
Current

HOST_N

ISEL_0:1

HOST_P

1.1V

VDD_I (3.3V)

Table 7: HOST Current Selection

PROGRAM

RESISTOR

IREF

REFERENCE

CURRENT

REF

CURRENT

MULTIPLIER

TRACE

IMPEDANCE

OUTPUT

VOLTAGE

0.71V

475

(1%)

2.32mA

= 5

REF

0.59V

0.85V

475

(1%)

2.32mA

= 6

REF

0.71V

0.56V

475

(1%)

2.32mA

= 4

REF

0.47V

0.99V

475

(1%)

2.32mA

= 7

REF

0.82V

0.75V

221

(1%)

5mA

= 5

REF

0.62V

0.90V

221

(1%)

5mA

= 6

REF

0.75V

0.60V

221

(1%)

5mA

= 4

REF

0.50V

1.05V

221

(1%)

5mA

= 7

REF

0.84V

NOTE: Shaded row indicates the Primary System Configuration

Table 8: HOST Buffer Clock Output

HIGH DRIVE CURRENT (mA)

AT PRIMARY SYSTEM CONFIGURATION

Output

Voltage (V)

MIN.

TYP.

MAX.

3.30

0.00

3.14

-3.03

-4.22

-5.76

2.97

-5.66

-7.68

-9.86

2.81

-7.87

-10.30

-11.85

2.64

-9.67

-11.91

-12.45

2.48

-11.05

-12.56

-12.84

2.31

-11.98

-12.85

-13.16

2.14

-12.52

-13.07

-13.45

1.98

-12.77

-13.26

-13.72

1.81

-12.91

-13.42

-13.96

1.65

-12.99

-13.54

-14.17

1.48

-13.04

-13.64

-14.36

1.32

-13.07

-13.70

-14.52

1.15

-13.08

-13.73

-14.64

0.99

-13.09

-13.75

-14.71

0.82

-13.11

-13.76

-14.74

0.66

-13.12

-13.78

-14.76

0.49

-13.13

-13.79

-14.78

0.33

-13.13

-13.80

-14.80

0.16

-13.14

-13.81

-14.82

0.00

-13.15

-13.82

-14.83

-20

-18

-16

-14

-12

-10

-8

-6

-4

-2

Output Voltage (V)

Out

put

rrent

(

)

30
50
90

Max VOH

Data in this table represents nominal characterization data only

AMERICAN MICROSYSTEMS, INC.

September 2000

9.18.00

FS6232-01

Two-Way MP Motherboard Clock Generator IC

ISO9001

4.0 Power

Management

The PWR_DWN# signal is an asynchronous, active-low
LVTTL input that places the device in a low power inac-
tive state without removing power from the device. All
internal clocks are turned off, and all clock outputs are
held low.
Since PWR_DWN# is asynchronous, the signal is syn-
chronized internally to each individual clock. As shown in
Figure 3, a falling-rising-falling edge sequence on any
individual clock output is required before that clock output
is disabled low. This edge sequence ensures that one
complete clock cycle will occur before the clock stops.

Table 9: Latency Table

LATENCY

SIGNAL

STATE

MIN.

MAX.

Output:

2 clocks

3 clocks

Power

OFF

Device:

REF

clocks

REF clocks

PWR_
DWN#

Power

3ms

Upon the release of PWR_DWN# (power-up), external
circuitry should allow a minimum of 3ms for the PLL to
lock before enabling any clocks.

Figure 3: PWR_DWN# Timing

Any Clock

(output)

PWR_DWN#

Any Clock

(internal)

VCO

Crystal

Oscillator

After REF

output shuts off...

3ms until clock is valid

Shaded regions in the Crystal Oscillator and VCO waveforms indicate that the clock is valid and the Crystal Oscillator and VCO are active.

5.0 Dual Function I/O Pins

Several pins on this device serve as dual function in-
put/output pins. During the initial application of VDD to
the device, this type of pin functions as an input pin.
Upon completion of power-up, the logic state present on
the pin is latched internally, and the pin is converted to an
output driver.
An external 10k pull-down resistor to ground is required
for a logic low and a 10k pull-up resistor to the clock
output VDD is required for a logic high. The 10k resistor
presents an insignificant load to the output driver that
should not affect the output clock.
Note that the latching of the logic state occurs only on the
application of the chip supply voltage (VDD). The logic
state on the pin is not latched if the PWR_DWN# signal is
used to power-down the device with VDD still applied.

Figure 4: I/O Pin Programming

Clock Trace

Termination

Resistor

Device Solder

Pads

Ground or

Power Via

10k

Programming

Resistor

AMERICAN MICROSYSTEMS, INC.

September 2000

9.18.00

FS6232-01

Two-Way MP Motherboard Clock Generator IC

ISO9001

6.0 Electrical

Specifications

Table 10: Absolute Maximum Ratings

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at
these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance,
functionality, and reliability.

PARAMETER

SYMBOL

MIN.

MAX.

UNITS

Supply Voltage (V

= ground)

-0.5

Input Voltage, dc

-0.5

+0.5

Output Voltage, dc

-0.5

+0.5

Input Clamp Current, dc (V

< 0 or V

> V

)

-50

Output Clamp Current, dc (V

< 0 or V

> V

)

-50

Storage Temperature Range (non-condensing)

-65

150

°C

Ambient Temperature Range, Under Bias

-55

125

°C

Junction Temperature

125

°C

Lead Temperature (soldering, 10s)

260

°C

Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7)

CAUTION: ELECTROSTATIC SENSITIVE DEVICE

Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy elec-
trostatic discharge.

Table 11: Operating Conditions

PARAMETER

SYMBOL

CONDITIONS/DESCRIPTION

MIN.

TYP.

MAX.

UNITS

Core (VDD)

3.135

3.3

3.465

Supply Voltage

Clock Buffers (VDD_48, VDD_66, VDD_H,
VDD_M, VDD_P, VDD_R)

3.135

3.3

3.465

Operating Temperature Range

°C

Crystal Resonator Frequency

XTAL

14.316

14.318

14.32

MHz

Crystal Resonator Load Capacitance

XIN, XOUT pins

13.5

22.5

MREF_P, MREF_N

PCI_0:9

CK66_0:3

CK48_0:1

Load Capacitance

REF_0:1

Load Resistance

HOST_P1 to HOST_P4,
HOST_N1 to HOST_N4

105

Maximum High-Level Output Voltage

HOST_P1 to HOST_P4,
HOST_N1 to HOST_N4

1.20

AMERICAN MICROSYSTEMS, INC.

September 2000

9.18.00

FS6232-01

Two-Way MP Motherboard Clock Generator IC

ISO9001

Table 12: DC Electrical Specifications

Unless otherwise stated, all power supplies = 3.3V ± 5%, no load on any output, and ambient temperature range T

= 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal

characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are

f rom typical. Negative currents indicate current flows out of the device.

PARAMETER

SYMBOL

CONDITIONS/DESCRIPTION

MIN.

TYP.

MAX.

UNITS

Overall

HOST

=133MHz; V

=3.465V, R

IREF

=475

, I

=6I

REF

260

Supply Current, Dynamic, with Loaded
Outputs

HOST

=100MHz; V

=3.465V, R

IREF

=475

, I

=6I

REF

250

Supply Current, Static

DDs

PWR_DWN# low, all supplies = 3.465V,
R

IREF

= 475

, I

= 6

REF

Digital Inputs (PWR_DWN#, SEL133/100#, SS_EN#)

High-Level Input Voltage

2.0

+0.3

Low-Level Input Voltage

-0.3

0.8

Input Leakage Current

-5

Crystal Oscillator Feedback (XIN)

Threshold Bias Voltage

1.5

High-Level Input Current

= 3.3V

Low-Level Input Current

= 0V

-32

Crystal Loading Capacitance *

L(xtal)

As seen by an external crystal connected to
XIN and XOUT

13.5

22.5

Input Loading Capacitance *

L(XIN)

As seen by an external clock driver on
XOUT; XIN unconnected

Crystal Oscillator Drive (XOUT)

High Level Output Source Current

I (XIN)

= 3.3V, V

= 0V

-8.0

Low Level Output Sink Current

I (XIN)

= 0V, V

= 3.3V

8.7

Current Reference (IREF)

Bias Voltage

no load

1.1

Short Circuit Output Source Current

= 0V

MREF_P, MREF_N, CK66_0:3, PCI_0:9 Clock Outputs (Type 5 Clock Driver)

OH min

VDD_M, VDD_66, VDD_P = 3.135V,
V

= 1.0V

-33

High Level Output Source Current

OH max

VDD_M, VDD_66, VDD_P = 3.465V,
V

= 3.135V

-33

OL min

VDD_M, VDD_66, VDD_P = 3.135V,
V

= 1.95V

Low Level Output Sink Current

OL max

VDD_M, VDD_66, VDD_P = 3.465V,
V

= 0.4V

Measured at 1.65V, output driving low

Output Impedance

Measured at 1.65V, output driving high

Tristate Output Current

-10

Short Circuit Output Source Current

OSH

= 0V; shorted for 30s, max.

-51

Short Circuit Output Sink Current

OSL

= 3.3V; shorted for 30s, max.

AMERICAN MICROSYSTEMS, INC.

September 2000

9.18.00

FS6232-01

Two-Way MP Motherboard Clock Generator IC

ISO9001

Table 13: DC Electrical Specifications, continued

Unless otherwise stated, all power supplies = 3.3V ± 5%, no load on any output, and ambient temperature range T

= 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal

characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are

f rom typical. Negative currents indicate current flows out of the device.

PARAMETER

SYMBOL

CONDITIONS/DESCRIPTION

MIN.

TYP.

MAX.

UNITS

HOST_P1:4, HOST_N1:4 Clock Outputs (Type X1 Clock Driver)

Crossover Voltage

= 33.2

, R

= 49.9

IREF

= 475

, I

= 6

REF

= 0.65V, R

IREF

= 475

, I

= 6

REF

12.9

High-Level Output Source Current

= 0.74V, R

IREF

= 475

, I

= 6

REF

14.9

= 3.3V, over settings in Table 7

-7

Output Source Current Tolerance

VDD_I = 3.3V±5%, over settings in Table 7

-12

+12

Output Impedance

, where V

= 1.0V, V

= V

IREF

= 475

, I

= 6

REF

3000

Tristate Output Current

-10

REF_0 / ISEL_0, REF_1 / ISEL_1 Clock Driver I/O, (Type 3)
CK48_0 / SEL_A, CK48_1 / SEL_B Clock Driver I/O (Type 3)

High-Level Input Voltage

2.0

+0.3

Low-Level Input Voltage

-0.3

0.8

High-Level Input Current

Low-Level Input Current (pull-up)

I
nput

= 0.4V

-9

High Level Output Source Current

VDD_R, VDD_48 = 3.465V, V

= 2.4V

-32

Low Level Output Sink Current

VDD_R, VDD_48 = 3.465V, V

= 0.4V

Measured at 1.65V, output driving low

Output Impedance

Measured at 1.65V, output driving high

Tristate Output Current

-10

Short Circuit Output Source Current

OSH

= 0V; shorted for 30s, max.

-41

Short Circuit Output Sink Current

Out
put

OSL

= 3.3V; shorted for 30s, max.

Figure 5: DC Measurement Diagram

= 2.0V

= 0.8V

= 0.4V

= 2.4V

= 3.3V

Figure 6: AC Measurement Diagram

1.5V

2.4V

0.4V

3.3V

Figure 7: HOST Clock V

Crossover Point

HOST_P

HOST_N

Figure 8: HOST Clock Test Circuit

Test node

From output

under test

AMERICAN MICROSYSTEMS, INC.

September 2000

9.18.00

FS6232-01

Two-Way MP Motherboard Clock Generator IC

ISO9001

Table 14: AC Timing Specifications

Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature T

= 25°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and

are not currently production tested to any specific limits. MIN and MAX characterization data are

f rom typical. Spread spectrum modulation is disabled except for Rise/Fall time measurements.

PARAMETER

SYMBOL

CONDITIONS/DESCRIPTION

MIN.

TYP.

MAX.

UNITS

Overall

Spread Spectrum Modulation
Frequency *

SS_EN# low

31.5

kHz

Spread Spectrum Modulation
Index *

SS_EN# low

-0.5

Clock Offset

CK66 leads @ 1.5V, C

=30pF to PCI @ 1.5V,

= 30pF (measured on rising edges)

1.5

3.5

Output Tristate Enable Delay *

DZL,

DZH

SEL_A:B = 00, SEL133/100# = 0

1.0

Output Tristate Disable Delay *

DLZ,

DHZ

SEL_A:B = 11, SEL133/100# = 0

1.0

Power-up PLL Lock Time

via PWR_DWN#

3.0

HOST_P1:4, HOST_N1:4 Clock Outputs

Clock Skew *

sk(o)

HOST pair to HOST pair @ V

IREF

= 475

= 6

REF

, R

= 33.2

, R

= 49.9

150

Duty Cycle *

Ratio of high pulse width to one clock period at V

IREF

= 475

, I

= 6

REF,

=33.2

, R

=49.9

Jitter, Period (peak-peak) *

Rising edge to rising edge at V

IREF

= 475

= 6

REF

= 33.2

, R

= 49.9

200

Rise Time *

Measured at 20% 80% of V

; R

IREF

= 475

= 6

REF

= 33.2

, R

= 49.9

175

450

Rise/Fall Time Matching*

Measured at 20% 80% of V

; R

IREF

= 475

= 6

REF

= 33.2

, R

= 49.9

MREF_P, MREF_N Clock Outputs

Duty Cycle *

Ratio of high pulse width to one clock period,
measured at 1.5V

Jitter, Period (peak-peak) *

From rising edge to rising edge at 1.5V, C

=30pF

250

r min

Measured @ 0.4V 2.4V; C

=10pF

0.4

Rise Time *

r max

Measured @ 0.4V 2.4V; C

=30pF

1.6

f min

Measured @ 2.4V 0.4V; C

=10pF

0.4

Fall Time *

f max

Measured @ 2.4V 0.4V; C

=30pF

1.6

AMERICAN MICROSYSTEMS, INC.

September 2000

9.18.00

FS6232-01

Two-Way MP Motherboard Clock Generator IC

ISO9001

Table 15: AC Timing Specifications, continued

Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature T

= 25°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and

are not currently production tested to any specific limits. MIN and MAX characterization data are

f rom typical. Spread spectrum modulation is disabled except for Rise/Fall time measurements.

PARAMETER

SYMBOL

CONDITIONS/DESCRIPTION

MIN.

TYP.

MAX.

UNITS

PCI_0:9 Clock Outputs

Duty Cycle *

Ratio of high pulse width to one clock period,
measured at 1.5V

Clock Skew *

sk(o)

One clock output relative to another at 1.5V

500

Jitter, Period (peak-peak) *

From rising edge to rising edge at 1.5V, C

= 30pF

500

r min

Measured at 0.4V 2.4V; C

= 10pF

0.5

Rise Time *

r max

Measured at 0.4V 2.4V; C

= 30pF

2.0

f min

Measured at 2.4V 0.4V; C

= 10pF

0.5

Fall Time *

f max

Measured at 2.4V 0.4V; C

= 30pF

2.0

CK66_0:3 Clock Outputs

Duty Cycle *

Ratio of high pulse width to one clock period,
measured at 1.5V

Clock Skew *

sk(o)

One clock output relative to another at 1.5V

250

Jitter, Period (peak-peak) *

From rising edge to rising edge at 1.5V, C

= 30pF

300

r min

Measured at 0.4V 2.4V; C

= 10pF

0.5

Rise Time *

r max

Measured at 0.4V 2.4V; C

= 30pF

2.0

f min

Measured at 2.4V 0.4V; C

= 10pF

0.5

Fall Time *

f max

Measured at 2.4V 0.4V; C

= 30pF

2.0

REF_0:1 Clock Outputs

Duty Cycle *

Ratio of high pulse width to one clock period,
measured at 1.5V

Jitter, Period (peak-peak) *

From rising edge to rising edge at 1.5V, C

= 20pF

1000

r min

Measured at 0.4V 2.4V; C

= 10pF

1.0

Rise Time *

r max

Measured at 0.4V 2.4V; C

= 20pF

4.0

f min

Measured at 2.4V 0.4V; C

= 10pF

1.0

Fall Time *

f max

Measured at 2.4V 0.4V; C

= 20pF

4.0

CK48_0:1 Clock Outputs

Duty Cycle *

Ratio of high pulse width to one clock period,
measured at 1.5V

Jitter, Period (peak-peak) *

From rising edge to rising edge at 1.5V, C

= 20pF

350

r min

Measured at 0.4V 2.4V; C

= 10pF

1.0

Rise Time *

r max

Measured at 0.4V 2.4V; C

= 20pF

4.0

f min

Measured at 2.4V 0.4V; C

= 10pF

1.0

Fall Time *

f max

Measured at 2.4V 0.4V; C

= 20pF

4.0

AMERICAN MICROSYSTEMS, INC.

September 2000

9.18.00

FS6232-01

Two-Way MP Motherboard Clock Generator IC

ISO9001

Table 16: MCLK_P, MCLK_N, PCI_0:9, CK66_0:3 Clock Outputs

High Drive Current (mA)

Low Drive Current (mA)

Voltage

(V)

MIN.

TYP.

MAX.

Voltage

(V)

MIN.

TYP.

MAX.

-49

-83

-132

0.2

-48

-83

-131

0.4

-48

-82

-130

0.6

-47

-81

-129

0.8

-47

-80

-127

1.0

-46

-79

-126

1.2

103

1.2

-46

-78

-124

1.4

112

1.4

-45

-76

-121

1.6

117

1.6

-43

-74

-117

1.8

120

1.8

-41

-70

-112

2.0

121

2.0

-37

-65

-105

2.2

122

2.2

-33

-59

-97

2.4

123

2.4

-28

-52

-87

2.6

123

2.6

-22

-43

-74

2.8

124

2.8

-14

-32

-60

3.0

124

3.0

-6

-20

-45

3.2

124

3.2

-7

-27

3.4

125

3.4

-7

-150

-125

-100

-75

-50

-25

100

125

150

0.5

1.5

2.5

3.5

Output Voltage (V)

Out

put

rrent

(

)

30
50
90

Data in this table represents nominal characterization data only

Table 17: REF_0:1, CK48_0:1 Clock Outputs

High Drive Current (mA)

Low Drive Current (mA)

Voltage

(V)

MIN.

TYP.

MAX.

Voltage

(V)

MIN.

TYP.

MAX.

-38

-64

-102

0.2

-37

-64

-101

0.4

-37

-63

-100

0.6

-37

-63

-99

0.8

-36

-62

-98

1.0

-36

-61

-97

1.2

-35

-60

-95

1.4

-34

-59

-93

1.6

-33

-57

-90

1.8

-31

-54

-87

2.0

-29

-50

-81

2.2

-25

-46

-75

2.4

-21

-40

-67

2.6

-17

-33

-57

2.8

-11

-25

-47

3.0

-5

-16

-34

3.2

-6

-21

3.4

-5

-120

-100

-80

-60

-40

-20

100

120

0.5

1.5

2.5

3.5

Output Voltage (V)

Out

put

rrent

(

)

30
50
90

Data in this table represents nominal characterization data only

AMERICAN MICROSYSTEMS, INC.

September 2000

9.18.00

FS6232-01

Two-Way MP Motherboard Clock Generator IC

ISO9001

7.0 Package

Information

Table 18: 56-pin SSOP (0.300") Package Dimensions

DIMENSIONS

INCHES

MILLIMETERS

MIN.

MAX.

MIN.

MAX.

0.095

0.110

2.41

2.79

0.008

0.016

0.20

0.41

0.008

0.0135

0.20

0.34

0.005

0.010

0.13

0.25

0.720

0.730

18.29

18.54

0.395

0.420

10.03

10.67

0.291

0.299

7.39

7.59

0.025 BSC

0.64 BSC

0.015

0.025

0.38

0.64

0.020

0.040

0.51

1.01

AMERICAN MICROSYSTEMS, INC.

SEATING PLANE

h × 45°

Table 19: 56-pin SSOP (0.300") Package Characteristics

PARAMETER

SYMBOL

CONDITIONS/DESCRIPTION

TYP.

UNITS

Thermal Impedance, Junction to Free-Air

Air flow = 0 m/s

°C/W

Longest trace + wire

6.41

Lead Inductance, Self

Shortest trace + wire

2.49

Longest trace + wire to first adjacent trace

3.65

Shortest trace + wire to first adjacent trace

1.35

Longest trace + wire to next adjacent trace

2.50

Lead Inductance, Mutual

Shortest trace + wire to next adjacent trace

0.90

Longest trace + wire to V

0.94

Lead Capacitance, Bulk

Shortest trace + wire to V

0.50

Longest trace + wire to first adjacent trace

0.48

Shortest trace + wire to first adjacent trace

0.20

Longest trace + wire to next adjacent trace

0.07

Lead Capacitance, Mutual

Shortest trace + wire to next adjacent trace

0.02

AMERICAN MICROSYSTEMS, INC.

September 2000

9.18.00

FS6232-01

Two-Way MP Motherboard Clock Generator IC

ISO9001

Table 20: 56-pin TSSOP (6.1mm) Package Dimensions

DIMENSIONS

INCHES

MILLIMETERS

MIN.

MAX.

MIN.

MAX.

0.047

1.20

0.002

0.006

0.05

0.15

0.0067

0.011

0.17

0.27

0.0035

0.008

0.09

0.20

0.547

0.555

13.9

14.1

0.318 BSC

8.10 BSC

0.236

0.244

6.00

6.20

0.019 BSC

0.50 BSC

0.018

0.030

0.45

0.75

0.008

0.20

12° REF

AMERICAN MICROSYSTEMS, INC.

SEATING PLANE

Table 21: 56-pin TSSOP (6.1mm) Package Characteristics

PARAMETER

SYMBOL

CONDITIONS/DESCRIPTION

TYP.

UNITS

Thermal Impedance, Junction to Free-Air

Air flow = 0 m/s

°C/W

Longest trace + wire

4.04

Lead Inductance, Self

Shortest trace + wire

1.38

Longest trace + wire to first adjacent trace

2.20

Shortest trace + wire to first adjacent trace

0.72

Longest trace + wire to next adjacent trace

1.43

Lead Inductance, Mutual

Shortest trace + wire to next adjacent trace

0.48

Longest trace + wire to V

0.63

Lead Capacitance, Bulk

Shortest trace + wire to V

0.21

Longest trace + wire to first adjacent trace

0.31

Shortest trace + wire to first adjacent trace

0.07

Longest trace + wire to next adjacent trace

0.04

Lead Capacitance, Mutual

Shortest trace + wire to next adjacent trace

0.01

AMERICAN MICROSYSTEMS, INC.

September 2000

9.18.00

FS6232-01

Two-Way MP Motherboard Clock Generator IC

ISO9001

8.0 Ordering

Information

Table 22: Device Ordering Codes

DEVICE NUMBER

ORDERING CODE

PACKAGE TYPE

OPERATING

TEMPERATURE RANGE

SHIPPING

CONFIGURATION

11995-801

Tape and Reel

11995-811

56-pin (0.300") SSOP

Tubes

11995-201

Tape and Reel

FS6232-01

11995-211

56-pin (6.1mm) TSSOP

C to 70

C (Commercial)

Tubes

Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI
makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom
of the described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI re-
serves the right to discontinue production and change specifications and prices at any time and without notice. AMI's products are
intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental require-
ments, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recom-
mended without additional processing by AMI for such applications.

American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796,
WWW Address:

http://www.amis.com

E-mail:

tgp@amis.com

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: FS6232-01

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: FS6232-01