A29400 Series

512K X 8 Bit / 256K X 16 Bit CMOS 5.0 Volt-only,

Preliminary

Boot Sector Flash Memory

PRELIMINARY (December, 2002, Version 0.2)

AMIC Technology, Corp.

Features

5.0V

10% for read and write operations

Access times:

- 55/70/90 (max.)

Current:

- 20 mA typical active read current
- 30 mA typical program/erase current
- 1

A typical CMOS standby

Flexible sector architecture

16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX7 sectors

8 Kword/ 4 KwordX2/ 16 Kword/ 32 KwordX7 sectors

Any combination of sectors can be erased

Supports full chip erase

Sector protection:
A hardware method of protecting sectors to prevent
any inadvertent program or erase operations within
that sector

Top or bottom boot block configurations available

Embedded Erase Algorithms

- Embedded Erase algorithm will automatically erase

the entire chip or any combination of designated
sectors and verify the erased sectors

- Embedded Program algorithm automatically writes

and verifies bytes at specified addresses

Typical 100,000 program/erase cycles per sector

20-year data retention at 125

- Reliable operation for the life of the system

Compatible with JEDEC-standards

- Pinout and software compatible with single-power-

supply Flash memory standard

Superior inadvertent write protection

Data

Polling and toggle bits

Provides a software method of detecting completion
of program or erase operations

Erase Suspend/Erase Resume

Suspends a sector erase operation to read data from,

or program data to, a non-erasing sector, then
resumes the erase operation

Hardware reset pin (

RESET

)

Hardware method to reset the device to reading array
data

Package options

44-pin SOP or 48-pin TSOP (I)

General Description

The A29400 is a 5.0 volt only Flash memory organized as
524,288 bytes of 8 bits or 262,144 words of 16 bits each. The
A29400 offers the

RESET

function. The 512 Kbytes of data are

further divided into eleven sectors for flexible sector erase
capability. The 8 bits of data appear on I/O

- I/O

while the

addresses are input on A1 to A17; the 16 bits of data appear on
I/O

~I/O

. The A29400 is offered in 44-pin SOP and 48-Pin

TSOP packages. This device is designed to be programmed in-
system with the standard system 5.0 volt VCC supply. Additional
12.0 volt VPP is not required for in-system write or erase
operations. However, the A29400 can also be programmed in
standard EPROM programmers.

The A29400 has the first toggle bit, I/O

, which indicates whether

an Embedded Program or Erase is in progress, or it is in the
Erase Suspend. Besides the I/O

toggle bit, the A29400 has a

second toggle bit, I/O

, to indicate whether the addressed sector

is being selected for erase. The A29400 also offers the ability to
program in the Erase Suspend mode. The standard A29400
offers access times of 55, 70 and 90 ns, allowing high-speed
microprocessors to operate without wait states. To eliminate bus
contention the device has separate chip enable (

), write

enable (

) and output enable (

) controls.

The device requires only a single 5.0 volt power supply for both
read and write functions. Internally generated and regulated
voltages are provided for the program and erase operations.
The A29400 is entirely software command set compatible with
the JEDEC single-power-supply Flash standard. Commands are
written to the command register using standard microprocessor
write timings. Register contents serve as input to an internal
state-machine that controls the erase and programming circuitry.
Write cycles also internally latch addresses and data needed for
the programming and erase operations. Reading data out of the
device is similar to reading from other Flash or EPROM devices.
Device programming occurs by writing the proper program
command sequence. This initiates the Embedded Program
algorithm - an internal algorithm that automatically times the
program pulse widths and verifies proper program margin.
Device erasure occurs by executing the proper erase command
sequence. This initiates the Embedded Erase algorithm - an
internal algorithm that automatically preprograms the array (if it
is not already programmed) before executing the erase
operation. During erase, the device automatically times the
erase pulse widths and verifies proper erase margin.

A29400 Series

PRELIMINARY (December, 2002, Version 0.2)

AMIC Technology, Corp.

The host system can detect whether a program or erase
operation is complete by reading the I/O

(

Data

Polling) and

I/O

(toggle) status bits. After a program or erase cycle has

been completed, the device is ready to read array data or
accept another command.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data
contents of other sectors. The A29400 is fully erased when
shipped from the factory.
The hardware sector protection feature disables operations
for both program and erase in any combination of the

Pin Configurations

sectors of memory. This can be achieved via programming
equipment.
The Erase Suspend feature enables the user to put erase on
hold for any period of time to read data from, or program data
to, any other sector that is not selected for erasure. True
background erase can thus be achieved.
Power consumption is greatly reduced when the device is
placed in the standby mode.
The hardware RESET pin terminates any operation in
progress and resets the internal state machine to reading
array data.

SOP

TSOP (I)

RY/BY

A17

VSS

I/O

(A-1)

VSS

BYTE

A16

A15

A14

A12

A11

A10

A13

A29400

RESET

I/O

VCC

A29400V

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

A14
A13
A12
A11
A10

A9
A8

RESET

NC
NC

RY/BY

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

I/O

VCC

I/O

(A-1)

VSS

BYTE

A16

A15

17
18
19
20

22
23
24

I/O

VSS
CE

A17

A7
A6
A5

A3
A2
A1

A29400 Series

PRELIMINARY (December, 2002, Version 0.2)

AMIC Technology, Corp.

Absolute Maximum Ratings*

Ambient Operating Temperature . . . . . -55

C to + 125

Storage Temperature . . . . . . . . . . . . . . -65

C to + 125

Ground to VCC . . . . . . . . . . . . . . . . . . . . . . -2.0V to 7.0V
Output Voltage (Note 1) . . . . . . . . . . . . . . . -2.0V to 7.0V
A9,

& RESET (Note 2) . . . . . . . . . . . -2.0V to 12.5V

All other pins (Note 1) . . . . . . . . . . . . . . . . . -2.0V to 7.0V
Output Short Circuit Current (Note 3) . . . . . . . . . . 200mA

Notes:

1. Minimum DC voltage on input or I/O pins is -0.5V.

During voltage transitions, inputs may undershoot VSS
to -2.0V for periods of up to 20ns. Maximum DC voltage
on output and I/O pins is VCC +0.5V. During voltage
transitions, outputs may overshoot to VCC +2.0V for
periods up to 20ns.

2. Minimum DC input voltage on A9 pins is -0.5V. During

voltage transitions, A9,

and RESET may overshoot

VSS to -2.0V for periods of up to 20ns. Maximum DC
input voltage on A9 and

is +12.5V which may

overshoot to 13.5V for periods up to 20ns.

3. No more than one output is shorted at a time. Duration

of the short circuit should not be greater than one
second.

*Comments

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above
those indicated in the operational sections of these
specification is not implied or intended. Exposure to
the absolute maximum rating conditions for extended
periods may affect device reliability.

Operating Ranges

Commercial (C) Devices
Ambient Temperature (T

) . . . . . . . . . . . . . . 0

C to +70

VCC Supply Voltages
VCC for

10% devices . . . . . . . . . . . . . . +4.5V to +5.5V

Operating ranges define those limits between which the
functionally of the device is guaranteed.

Device Bus Operations

This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memory location. The
register is composed of latches that store the commands,
along with the address and data information needed to

execute the command. The contents of the register serve
as inputs to the internal state machine. The state machine
outputs dictate the function of the device. The appropriate
device bus operations table lists the inputs and control
levels required, and the resulting output. The following
subsections describe each of these operations in further
detail.

Table 1. A29400 Device Bus Operations

I/O

- I/O

Operation

RESET

A0 - A17

I/O

- I/O

BYTE

Read

OUT

High-Z

Write

High-Z

CMOS Standby

VCC

0.5 V

VCC

0.5 V

High-Z

TTL Standby

High-Z

Output Disable

High-Z

Hardware Reset

High-Z

Temporary Sector
Unprotect (See Note)

Legend:
L = Logic Low = V

, H = Logic High = V

, V

= 12.0

0.5V, X = Don't Care, D

= Data In, D

OUT

= Data Out, A

= Address In

Note:
See the "Sector Protection/Unprotection" section and Temporary Sector Unprotect for more information.

A29400 Series

PRELIMINARY (December, 2002, Version 0.2)

AMIC Technology, Corp.

Word/Byte Configuration

The

BYTE

pin determines whether the I/O pins I/O

-I/O

operate in the byte or word configuration. If the

BYTE

is set at logic "1", the device is in word configuration, I/O

I/O

are active and controlled by

and

If the

BYTE

pin is set at logic "0", the device is in byte

configuration, and only I/O

-I/O

are active and controlled

and

. I/O

-I/O

are tri-stated, and I/O

pin is

used as an input for the LSB(A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive
the

and

pins to V

is the power control and

selects the device.

is the output control and gates

array data to the output pins.

should remain at V

all

the time during read operation. The internal state machine
is set for reading array data upon device power-up, or after
a hardware reset. This ensures that no spurious alteration
of the memory content occurs during the power transition.
No command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid data
on the device data outputs. The device remains enabled for
read access until the command register contents are
altered.
See "Reading Array Data" for more information. Refer to the
AC Read Operations table for timing specifications and to
the Read Operations Timings diagram for the timing
waveforms, l

CC1

in the DC Characteristics table represents

the active current specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive

and

, and

to V

. An erase operation can erase one

sector, multiple sectors, or the entire device. The Sector
Address Tables indicate the address range that each sector
occupies. A "sector address" consists of the address inputs
required to uniquely select a sector. See the "Command
Definitions" section for details on erasing a sector or the
entire chip, or suspending/resuming the erase operation.
After the system writes the autoselect command sequence,
the device enters the autoselect mode. The system can
then read autoselect codes from the internal register (which
is separate from the memory array) on I/O

- I/O

. Standard

read cycle timings apply in this mode. Refer to the
"Autoselect Mode" and "Autoselect Command Sequence"
sections for more information.
I

CC2

in the DC Characteristics table represents the active

current specification for the write mode. The "AC
Characteristics" section contains timing specification tables
and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system may
check the status of the operation by reading the status bits
on I/O

- I/O

. Standard read cycle timings and I

read

specifications apply. Refer to "Write Operation Status" for
more information, and to each AC Characteristics section
for timing diagrams.

Standby Mode

When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs are
placed in the high impedance state, independent of the

input.
The device enters the CMOS standby mode when the

& RESET pins are both held at V

0.5V. (Note that this

is a more restricted voltage range than V

.) The device

enters the TTL standby mode when

is held at V

, while

RESET is held at VCC

0.5V. The device requires the

standard access time (t

) before it is ready to read data.

If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
I

CC3

in the DC Characteristics tables represents the standby

current specification.

Output Disable Mode

When the

input is at V

, output from the device is

disabled. The output pins are placed in the high impedance
state.

RESET

: Hardware Reset Pin

The RESET pin provides a hardware method of resetting
the device to reading array data. When the system drives
the RESET pin low for at least a period of t

, the device

immediately terminates any operation in progress, tristates
all data output pins, and ignores all read/write attempts for
the duration of the RESET pulse. The device also resets
the internal state machine to reading array data. The
operation that was interrupted should be reinitiated once
the device is ready to accept another command sequence,
to ensure data integrity.
The RESET pin may be tied to the system reset circuitry. A
system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from the
Flash memory.
Refer to the AC Characteristics tables for RESET
parameters and diagram.

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