LP62S4096E-T Series

512K X 8 BIT LOW VOLTAGE CMOS SRAM

(January, 2002, Version 2.0)

AMIC Technology, Inc.

Features

Power supply range: 2.7V to 3.6V

Access times: 55ns / 70ns (max.)

Current:

Very low power version: Operating: 30mA (max.)

Standby: 10

A (max.)

Full static operation, no clock or refreshing required

All inputs and outputs are directly TTL-compatible

Common I/O using three-state output

Data retention voltage: 2V (min.)

Available in 32-pin TSOP/TSSOP 36-ball CSP package

General Description

The LP62S4096E-T is a low operating current 4,194,304-bit
static random access memory organized as 524,288 words
by 8 bits and operates on a low power supply range: 2.7V to
3.3V. It is built using AMIC's high performance CMOS
process.
Inputs and three-state outputs are TTL compatible and allow
for direct interfacing with common system bus structures.
Two chip enable inputs are provided for POWER-DOWN and
device enable and an output enable input is included for easy
interfacing.
Data retention is guaranteed at a power supply voltage as low
as 2V.

CE2 pin for CSP package only

Product Family

Power Dissipation

Product Family

Operating

Temperature

VCC

Range

Speed

Data Retention

CCDR

, Typ.)

Standby

SB1

, Typ.)

Operating

CC2

, Typ.)

Package

Type

LP62S4096E-T

-25

C ~ +85

C 2.7V~3.6V

55ns / 70ns

0.08

0.3

5mA

32L TSOP

32L TSSOP

36B CSP

1. Typical values are measured at VCC = 3.0V, T

= 25

C and not 100% tested.

2. Data retention current VCC = 2.0V.

Pin Configurations

TSOP/(TSSOP)

CSP (Chip Size Package)

36-pin Top View

LP62S4096EV-T

(LP62S4096EX-T)

Pin No.

Pin
Name

Pin No.

Pin
Name

A13

A17

A15

VCC

A18

I/O

A16

A14

A12

I/O

GND

I/O

A11

CE1

A10

I/O

GND

VCC

I/O

A10

A11

CE1

A12

A13

A14

A16

A18

A17

A15

I/O

GND

VCC

CE2

LP62S4096E-T Series

(January, 2002, Version 2.0)

AMIC Technology, Inc.

Block Diagram

ROW

DECODER

1024 X 4096

MEMORY ARRAY

INPUT DATA

CIRCUIT

COLUMN I/O

CONTROL

CIRCUIT

I/O

A18

A17

A16

VCC

GND

CE1
CE2
OE

Pin Description

Symbol

Description

A0 - A18

Address Inputs

I/O

- I/O

Data Input/Outputs

GND

Ground

CE1, CE2

Chip Enable

Output Enable

Write Enable

VCC

Power Supply

Recommended DC Operating Conditions

= -25

C to + 85

Symbol

Parameter

Min.

Typ.

Max.

Unit

VCC

Supply Voltage

2.7

3.0

3.6

GND

Ground

Input High
Voltage

2.2

VCC

+ 0.3

Input Low Voltage

-0.3

+0.6

Output Load

TTL

Output Load

LP62S4096E-T Series

(January, 2002, Version 2.0)

AMIC Technology, Inc.

Absolute Maximum Ratings*

VCC to GND ------------------------------------- -0.5V to + 4.0V
IN, IN/OUT Volt to GND--------------- -0.5V to VCC + 0.5V
Operating Temperature, Topr -------------- -25

C to + 85

Storage Temperature, Tstg --------------- -55

C to + 125

Temperature Under Bias, Tbias ----------- -10

C to + 85

Power Dissipation, P

--------------------------------------- 0.7W

*Comments

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.

DC Electrical Characteristics

= -25

C to + 85

C, VCC = 2.7V to 3.6V, GND = 0V)

Symbol

Parameter

LP62S4096E-55LLT / 70LLT

Unit

Conditions

Min.

Typ.

Max.

Input Leakage Current

= GND to VCC

Output Leakage Current

CE1= V

, CE2= V

OE = V

WE =V

I/O

= GND to VCC

Active Power Supply Current

CE1= V

, CE2= V

I/O

= 0mA

CC1

Dynamic Operating Current

Min. Cycle, Duty = 100%,

CE1= V

CE2= V

, I

I/O

= 0mA

CC2

Dynamic Operating Current

CE1= V

, CE2= V

IH,

= VCC

= 0V, f = 1MH

I/O

= 0mA

Standby Power

VCC

3.3V

CE1= V

IH,

CE2= V

SB1

Supply Current

0.3

VCC

3.3V

CE1

VCC - 0.2V, or CE2

0.2V

Output Low Voltage

0.4

= 2.1mA

Output High Voltage

2.2

= -1.0mA

LP62S4096E-T Series

(January, 2002, Version 2.0)

AMIC Technology, Inc.

Truth Table

Mode

CE1

CE2

I/O Operation

Supply Current

Standby

High Z

, I

SB1

Standby

High Z

, I

SB1

Output Disable

High Z

CC,

CC1,

CC2

Read

OUT

CC,

CC1,

CC2

Write

CC,

CC1,

CC2

Note: X = H or L

Capacitance

= 25

C, f = 1.0MHz)

Symbol

Parameter

Min.

Max.

Unit

Conditions

Input Capacitance

= 0V

I/O

Input/Output Capacitance

I/O

= 0V

* These parameters are sampled and not 100% tested.

AC Characteristics

= -25

C to + 85

C, VCC = 2.7V to 3.6V)

Symbol

Parameter

LP62S4096E-55LLT

LP62S4096E-70LLT

Unit

Min.

Max.

Min.

Max.

Read Cycle

Read Cycle Time

Address Access Time

ACE1,

ACE2

Chip Enable Access Time

Output Enable to Output Valid

CLZ1,

CLZ2

Chip Enable to Output in Low Z

OLZ

Output Enable to Output in Low Z

CHZ1,

CHZ2

Chip Disable to Output in High Z

OHZ

Output Disable to Output in High Z

Output Hold from Address Change

LP62S4096E-T Series

(January, 2002, Version 2.0)

AMIC Technology, Inc.

AC Characteristics (continued)

Symbol

Parameter

LP62S4096E-55LLT

LP62S4096E-70LLT

Unit

Min.

Max.

Min.

Max.

Write Cycle

Write Cycle Time

CW1

Chip Enable to End of Write

Address Setup Time

Address Valid to End of Write

Write Pulse Width

Write Recovery Time

WHZ

Write to Output in High Z

Data to Write Time Overlap

Data Hold from Write Time

Output Active from End of Write

Notes: t

CHZ,

OHZ

and t

WHZ

are defined as the time at which the outputs achieve the open circuit condition and are

not referred to output voltage levels.

Timing Waveforms Read Cycle 1

(1)

Address

OLZ5

OHZ5

OUT

ACE1 ,

ACE2

CHZ1 ,

CHZ2

CLZ1 ,

CLZ2

CE1

CE2

LP62S4096E-T Series

(January, 2002, Version 2.0)

AMIC Technology, Inc.

Timing Waveforms (continued)

Read Cycle 2

(1, 2, 4)

Address

OUT

Read Cycle 3

(1, 3, 4)

Notes: 1. WE is high for Read Cycle.

2. Device is continuously enabled, CE1 = V

CE2=

IH.

3. Address valid prior to or coincident with CE1 transition low or CE2 transition high.

4. OE = V

5. Transition is measured

500mV from steady state. This parameter is sampled and not 100% tested.

ACS1 ,

ACS2

OUT

CS2

CS1

CHZ1 ,

CHZ2

CLZ1 ,

CLZ2

LP62S4096E-T Series

(January, 2002, Version 2.0)

AMIC Technology, Inc.

Write Cycle 2

(6)

(Chip Enable Controlled)

Address

WR3

(4)

CW1

CW2

WHZ7

OUT

WP2

CE2

CE1

Notes: 1. t

is measured from the address valid to the beginning of Write.

2. A Write occurs during the overlap (t

) of a low CE1 or high CE2 , and a low WE .

3. t

is measured from the earliest of CE1 or WE going high or CE2 going low WE going high to the end of the

Write cycle.

4. If the CE1 low or CE2 high transition occurs simultaneously with the WE low transition or after the WE

transition, outputs remain in a high impedance state.

5. t

is measured from the later of CE1 going low or CE2 going high to the end of Write.

6. OE level is high or low.

7. Transition is measured

500mV from steady state. This parameter is sampled and not 100% tested.

LP62S4096E-T Series

(January, 2002, Version 2.0)

AMIC Technology, Inc.

AC Test Conditions

Input Pulse Levels

0.4V to 2.4V

Input Rise and Fall Time

5 ns

Input and Output Timing Reference Levels

1.5V

Output Load

See Figures 1 and 2

30pF

* Including scope and jig.

TTL

5pF

TTL

Figure 1. Output Load

Figure 2. Output Load for t

CLZ

OHZ

, t

CHZ

, t

WHZ

, and t

Data Retention Characteristics

= -25

C to 85

Symbol

Parameter

Min.

Typ.

Max.

Unit

Conditions

VCC for Data Retention

2.0

3.6

CE1

VCC - 0.2V, or

CE2

0.2V

VCC = 2.0V,

CCDR

Data Retention Current

LL-Version

0.08

CE1

VCC - 0.2V, or

CE2

0.2V

CDR

Chip Disable to Data Retention Time

Operation Recovery Time

See Retention Waveform

VCC Rising Time from Data Retention Voltage to
Operating Voltage

* LP62S4096E-55LLT / 70LLT

CCDR

: max. 1

A at T

= 0

C to + 40

LP62S4096E-T Series

(January, 2002, Version 2.0)

AMIC Technology, Inc.

Low VCC Data Retention Waveform (1) (

CE1

Controlled)

VCC

CDR

2.7V

DATA RETENTION MODE

CE1

- 0.2V

CE1

Low VCC Data Retention Waveform (2) (CE2 Controlled)

VCC

CE2

CDR

2.7V

DATA RETENTION MODE

0.2V

CE2

Ordering Information

Part No.

Access Time(ns)

Operating Current

Max.(mA)

Standby Current

Max.(uA)

Package

LP62S4096EV-55LLT

32L TSOP

LP62S4096EX-55LLT

32L TSSOP

LP62S4096EU-55LLT

36L CSP

LP62S4096EV-70LLT

32L TSOP

LP62S4096EX-70LLT

32L TSSOP

LP62S4096EU-70LLT

36L CSP

LP62S4096E-T Series

(January, 2002, Version 2.0)

AMIC Technology, Inc.

Package Information

TSOP 32L TYPE I (8 X 20mm) Outline Dimensions

unit: inches/mm

GAUGE PLANE

0.25

BSC

Detail "A"

D y

Detail "A"

0.10(0.004)

12.0

Symbol

Dimensions in inches

Dimensions in mm

0.047 Max.

1.20 Max.

0.004±0.002

0.10±0.05

0.039±0.002

1.00±0.05

0.008±0.001

0.20±0.03

0.006±0.001

0.15±0.02

0.724±0.004

18.40±0.10

0.315±0.004

8.00±0.10

0.020 TYP.

0.50 TYP.

0.787±0.007

20.00±0.20

0.020±0.004

0.50±0.10

0.031 TYP.

0.80 TYP.

0.0167 TYP.

0.425 TYP.

0.004 Max.

0.10 Max.

~ 6

Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e

is for PC Board surface mount pad pitch design

reference only.
4. Dimension S includes end flash.

LP62S4096E-T Series

(January, 2002, Version 2.0)

AMIC Technology, Inc.

Package Information

TSSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions

unit: inches/mm

Detail "A"

0.10MM

Detail "A"

GAUGE PLANE

0.25

BSC

Detail "A"

SEATING PLANE

12.0

Symbol

Dimensions in inches

Dimensions in mm

0.049 Max.

1.25 Max.

0.002 Min.

0.05 Min.

0.039±0.002

1.00±0.05

0.008±0.001

0.20±0.03

0.006±0.0003

0.15±0.008

0.315±0.004

8.00±0.10

0.020 TYP.

0.50 TYP.

0.528±0.008

13.40±0.20

0.465±0.004

11.80±0.10

0.02±0.008

0.50±0.20

0.0266 Min.

0.675 Min.

0.0109 TYP.

0.278 TYP.

0.004 Max.

0.10 Max.

~ 6

Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e

is for PC Board surface mount pad pitch design

reference only.
4. Dimension S includes end flash.

LP62S4096E-T Series

(January, 2002, Version 2.0)

AMIC Technology, Inc.

Package Information

36LD CSP (6 x 8 mm) Outline Dimensions

unit: mm

A
B
C
D
E
F

G
H

TOP VIEW

Ball#A1 CORNER

SIDE VIEW

SEATING PLANE

0.25

(0.36)

A
B
C
D
E
F

G
H

1 2 3 4 5 6

0.10

0.25

A B

b (36X)

BOTTOM VIEW

Ball*A1 CORNER

0.20(4X)

0.10

Dimensions in mm

Symbol

MIN.

NOM. MAX.

1.00

1.10

1.20

0.16

0.21

0.26

0.48

0.53

0.58

5.80

6.00

6.20

7.80

8.00

8.20

---

3.75

---

5.25

---

0.75

---

0.25

0.30

0.35

Note:
1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS

ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY).

2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL

CROWNS OF THE SOLDER BALLS.

3. DIMENSION b IS MEASURED AT THE MAXIMUM.

THEERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF

THE SOLDER BALL AND THE BODY EDGE.

4. BALL PAD OPENING OF SUBSTRATE IS

0.25mm (SMD)

SUGGEST TO DESIGN THE PCB LAND SIZE AS

0.25mm (NSMD)

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