Data Sheet AS1100
Revision 1.32, Oct. 2004
Page 1 of 12
Key Features
-
10MHz Serial Interface
-
Individual LED Segment Control
-
Decode/No-Decode Digit Selection
-
20A Low-Power Shutdown (Data Retained)
-
Extremely low Operating Current 0.5mA in open loop
-
Digital and Analog Brightness Control
-
Display Blanked on Power-Up
-
Drive Common-Cathode LED Display
-
Software Reset
1
-
Optional External clock
-
24-Pin DIP and SO Packages
-
Fully compatible to MAX7219
General Description
The AS1100 is an LED driver for 7 segment numeric
displays of up to 8 digits. The AS1100 can be programmed
via a conventional 4 wire serial interface. It includes a BCD
code-B decoder, a multiplex scan circuitry, segment and
display drivers and a 64 Bit memory. The memory is used to
store the LED settings, so that continuous reprogramming is
not necessary.
1
Software Reset and external clock are not supported by
MAX7219
Every individual segment can be addressed and updated
separately. Only one external resistor is required to set the
current through the LED display. Brightness can be
controlled either in an analog or digital way. The user can
choose the internal code-B decoder to display numeric
digits or to address each segment directly. The AS1100
features an extremely low shutdown current of only 20A.
and an operational current of less than 500A. The number
of visible digits can be programmed as well. The AS1100
can be reset by software and an external clock can be used.
Several test modes support easy debugging.
The AS1100 is fully compatible to the MAX 7219. AS1100 is
offered in a 24 pins PDIP and SOIC package.
Applications
-
Bar-Graph Displays
-
Industrial Controllers
-
Panel Meters
-
LED Matrix Displays
-
White Goods
Serially Interfaced, 8-Digit LED Driver
AS1100
DATA SHEET
8-Digit P Display
8 Segments
8 Digits
9.53k
+5V
MOSI
P I/O
SCK
LOAD
CLK
GND GND
DIG0-DIG7
SEG A-G
SEP DP
VDD
4
9
1
12
1
18
19
ISET
DIN
Pin Configuration
Typical Application Circuit
AS1100
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
DIP/SO 24
DIN
DIG0
DIG1
DIG2
DIG3
DIG4
DIG5
DIG6
DIG7
GND
GND
LOAD
DOUT
VDD
ISET
CLK
SEG A
SEG B
SEG C
SEG D
SEG E
SEG F
SEG G
SEG DP
TOP
Data Sheet AS1100
Revision 1.32, Oct. 2004
Page 2 of 12
Absolute Maximum Ratings
Voltage (with respect to GND)
VDD
-0.3V to 6V
DIN, CLK, LOAD
-0.3V to 6V
All Other Pins
-0.3V to (VDD +0.3V)
Current
DIG0DIG7 Sink Current
500mA
SEGAG, DP Source Current
100mA
Continuous Power Dissipation (TA = +85C)
Narrow Plastic DIP (derate 13.3mW/C above
+70C
1066mW
Wide SO (derate 11.8mW/C above +70C)
941mW
Operating Temperature Ranges (T
MIN
to T
MAX
)
AS1100xL
0C to +70C
AS1100xE
-40C to +85C
Storage Temperature Range
-65C to +150C
Package body temperature
2
+240C
Electrical Characteristics
(VDD = 5V, R
SET
= 9.53k
1%, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Parameter
Symbol Conditions
Min
Typ
Max
Units
Operating Supply Voltage
VDD
4.0
5.0
5.5
V
Shutdown Supply Current
IDD
SD
All digital inputs at VDD or GND, T
A
=
+25C
20
50
A
R
SET
= open circuit
500
A
Operating Supply Current
IDD
All segments and decimal point on, I
SEG
= -
40mA
330
mA
Display Scan Rate
f
OSC
8 digits scanned
500
800
1300
Hz
Digit Drive Sink Current
I
DIGIT
V
OUT
= 0.65V
320
mA
Segment Drive Source Current
I
SEG
T
A
= +25C, V
OUT
= (VDD -1V)
-30
-40
-45
mA
Segment Drive Current
Matching
I
SEG
3.0
%
Digit Drive Source Current
I
DIGIT
Digit off, V
DIGIT
= (VDD -0.3V)
-2
mA
Segment Drive Sink Current
I
SEG
Segment off, V
SEG
= 0.3V
5
mA
Logic Inputs
2
The reflow peak soldering temperature (body temperature) is specified according IPC/JEDEC J-STD-020B "Moisture/Reflow Sensitivity
Classification for non-hermetic Solid State Surface Mount Devices".
Data Sheet AS1100
Revision 1.32, Oct. 2004
Page 3 of 12
Parameter
Symbol Conditions
Min
Typ
Max
Units
Input Current DIN, CLK, LOAD
I
IH
, I
IL
V
IN
= 0V or VDD
-1
1
A
Logic High Input Voltage
V
IH
3.5
V
Logic Low Input Voltage
V
IL
0.8
V
Output High Voltage
V
OH
DOUT, I
SOURCE
= -1mA
VDD - 1
V
Output Low Voltage
V
OL
DOUT, I
SINK
= 1.6mA
0.4
V
Hysteresis Voltage
V
I
DIN, CLK, LOAD
1
V
Timing Characteristics
CLK Clock Period
t
CP
100
ns
CLK Pulse Width High
t
CH
50
ns
CLK Pulse Width Low
t
CL
50
ns
CLK Rise to LOAD Rise Hold
Time
t
CSH
0
ns
DIN Setup Time
t
DS
25
ns
DIN Hold Time
t
DH
0
ns
Output Data Propagation Delay
t
DO
C
LOAD
= 50pF
25
ns
LOAD Rising Edge to Next
Clock Rising Edge
t
LDCK
50
ns
Minimum LOAD Pulse High
t
CSW
50
ns
Data-to-Segment Delay
t
DSPD
2.25
ms
Pin Description
Pin
Name
Function
1
DIN
Data input. Data is programmed into the 16Bit shift register on the rising CLK edge
2, 3, 58, 10,
11
DIG 0DIG 7
8 digit driver lines that sink the current from the common cathode of the display.
In shutdown mode the AS1100 switches the outputs to VDD
4, 9
GND
both GND pins must be connected
12
LOAD
Strobe input. With the rising edge of the LOAD signal the 16 bit of serial data is latched into
the register.
13
CLK
Clock input. The interface is capable to support clock frequencies up to 10MHz. The serial
data is clocked into the internal shift register with the rising edge of the CLK signal. On the
DOUT pin the data is applied with the falling edge of CLK.
1417, 2023
SEG AG,
DP
Seven segment driver lines including the decimal point. When a segment is turned off the
output is connected to GND.
18
ISET
The current into I
SET
determines the peak current through the segments and therefore the
brightness.
19
VDD
Positive Supply Voltage (+5V)
24
DOUT
Serial data output for cascading drivers. The output is valid after 16.5 clock cycles. The
output is never set to high impedance.
Data Sheet AS1100
Revision 1.32, Oct. 2004
Page 4 of 12
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
Address
MSB Data LSB
Table 1: Serial data format (16 bits)
Detailed Description
Serial-Addressing Modes
Programming of the AS1100 is done via the 4 wire serial
interface. A programming sequence consists of 16-bit
packages. The data is shifted into the internal 16 Bit
register with the rising edge of the CLK signal. With the
rising edge of the LOAD signal the data is latched into a
digital or control register depending on the address. The
LOAD signal must go to high after the 16
th
rising clock
edge. The LOAD signal can also come later but just before
the next rising edge of CLK, otherwise data would be lost.
The content of the internal shift register is applied 16.5
clock cycles later to the DOUT pin. The data is clocked out
at the falling edge of CLK. The Bits of the 16Bit-
programming package are described in table 1. The first 4
Bits D15-D12 are "don't care, D11-D8 contain the address
and D7-D0 contain the data. The first bit is D15, the most
significant bit (MSB). The exact timing is given in figure 1.
Digit and Control Registers
The AS1100 incorporates 15 registers, which are listed in
Table 2. The digit and control registers are selected via the
4Bit address word. The 8 digit registers are realized with a
64bit memory. Each digit can be controlled directly without
rewriting the whole contents. The control registers consist
of decode mode, display intensity, number of scanned
digits, shutdown, display test and reset/external clock
register.
Shutdown Mode
The AS1100 features a shutdown mode, where it consumes
only 20A current. The shutdown mode is entered via a
write to register 0Ch. Then all segment current sources are
pulled to ground and all digit drivers are connected to VDD,
so that nothing is displayed. All internal digit registers keep
the programmed values. The shutdown mode can either be
used for power saving or for generating a flashing display
by repeatedly entering and leaving the shutdown mode. The
AS1100 needs typically 250s to exit the shutdown mode.
During shutdown the AS1100 is fully programmable. Only
the display test function overrides the shutdown mode.
Initial Power-Up
After powering up the system all register are reset, so that
the display is blank. The AS1100 starts the shutdown mode.
All registers should be programmed for normal operation.
The default settings enable only scan of one digit, the
internal decoder is disabled, data register and intensity
register are set to the minimum value.
Figure 1: Timing diagram
LOAD
CLK
DIN
DOUT
t
DS
t
DH
t
CL
t
CH
D15
D14
D1
D0
t
DO
t
CP
t
CS
t
LDCK
t
CSW
Data Sheet AS1100
Revision 1.32, Oct. 2004
Page 5 of 12
Decode-Mode Register
In the AS1100 a BCD decoder is included. Every digit can
be selected via register 09h to be decoded. The BCD code
consists of the numbers 0-9, E,H, L,P and -. In register 09h
a logic high enables the decoder for the appropriate digit. In
case that the decoder is bypassed (logic low) the data Bits
D7-D0 correspond to the segment lines of the AS1100. In
table 4 some possible settings for register 09h are shown.
Bit D7, which corresponds to the decimal point, is not
affected by the settings of the decoder. Logic high means
that the decimal point is displayed. In table 5 the font of the
Code B decoder is shown. In table 6 the correspondence of
the register to the appropriate segments of a 7 segment
display is shown (see figure 2)
Intensity Control and Interdigit Blanking
Brightness of the display can be controlled in an analog way
by changing the external resistor (R
SET
). The current, which
flows between VDD and I
SET
, defines the current that flows
through the LEDs. The LED current is 100 times the I
SET
current. The minimum value of R
SET
should be 9.53k
,
which corresponds to 40mA segment current. The
brightness of the display can also be controlled digitally via
register 0Ah. The brightness can be programmed in 16
steps and is shown in table 7. An internal pulse width
modulator controls the intensity of the display.
Scan-Limit Register
The scan limit register 0Bh selects the number of digits
displayed. When all 8 digits are displayed the update
frequency is typically 800Hz. If the number of digits
displayed is reduced, the update frequency is reduced as
well. The frequency can be calculated using 8fOSC/N,
where N is the number of digits. Since the number of
displayed digits influences the brightness, the resistor R
SET
should be adjusted accordingly. Table 9 shows the
maximum allowed current, when fewer than 4 digits are
used. To avoid differences in brightness the scan limit
register should not be used to blank portions of the display
(leading zeros).
Address
Register
D15D12 D11 D10 D9 D8
Hex
Code
No-Op
X
0
0
0 0
0xX0
Digit 0
X
0
0
0 1
0xX1
Digit 1
X
0
0
1 0
0xX2
Digit 2
X
0
0
1 1
0xX3
Digit 3
X
0
1
0 0
0xX4
Digit 4
X
0
1
0 1
0xX5
Digit 5
X
0
1
1 0
0xX6
Digit 6
X
0
1
1 1
0xX7
Digit 7
X
1
0
0 0
0xX8
Decode
Mode
X
1
0
0 1
0xX9
Intensity
X
1
0
1 0
0xXA
Scan Limit
X
1
0
1 1
0xXB
Shutdown
X
1
1
0 0
0xXC
Not used
X
1
1
0 1
0xXD
Reset and
ext. Clock
X
1
1
1 0
0xXE
Display
Test
X
1
1
1 1
0xXF
Table 2: Register address map
Register Data
Mode
Address Code
(Hex)
D7 D6 D5 D4 D3 D2 D1 D0
Shutdown
Mode
0xXC
X X X X X X X 0
Normal
Operation
0xXC
X X X X X X X 1
Table 3: Shutdown register format (address (hex) = 0xXC)
Data Sheet AS1100
Revision 1.32, Oct. 2004
Page 6 of 12
Register Data
Decode Mode
D7
D6
D5
D4
D3
D2
D1
D0
Hex Code
No decode for digits 70
0
0
0
0
0
0
0
0
0x00
Code B decode for digit 0
No decode for digits 71
0
0
0
0
0
0
0
1
0x01
Code B decode for digits
30
No decode for digits 74
0
0
0
0
1
1
1
1
0x0F
Code B decode for digits
70
1
1
1
1
1
1
1
1
0xFF
Table 4: Decode-mode register examples (address (hex) = 0xX9)
Register Data
On Segments = 1
7-Segment
Character
D7* D6D4
D3
D2
D1
D0 DP*
A
B
C
D
E
F
G
0
X
0
0
0
0
1
1
1
1
1
1
0
1
X
0
0
0
1
0
1
1
0
0
0
0
2
X
0
0
1
0
1
1
0
1
1
0
1
3
X
0
0
1
1
1
1
1
1
0
0
1
4
X
0
1
0
0
0
1
1
0
0
1
1
5
X
0
1
0
1
1
0
1
1
0
1
1
6
X
0
1
1
0
1
0
1
1
1
1
1
7
X
0
1
1
1
1
1
1
0
0
0
0
8
X
1
0
0
0
1
1
1
1
1
1
1
9
X
1
0
0
1
1
1
1
1
0
1
1
--
X
1
0
1
0
0
0
0
0
0
0
1
E
X
1
0
1
1
1
0
0
1
1
1
1
H
X
1
1
0
0
0
1
1
0
1
1
1
L
X
1
1
0
1
0
0
0
1
1
1
0
P
X
1
1
1
0
1
1
0
0
1
1
1
blank
X
1
1
1
1
0
0
0
0
0
0
0
Table 5: Code B font
*The decimal point is set by bit D7 = 1
Register Data
D7
D6
D5
D4
D3
D2
D1
D0
Corresponding
Segment Line
DP
A
B
C
D
E
F
G
Table 6: No-decode mode data bits and corresponding segment lines
Data Sheet AS1100
Revision 1.32, Oct. 2004
Page 7 of 12
Duty Cycle
D7 D6 D5 D4 D3 D2 D1 D0 Hex Code
1/32 (min on)
X X X X 0 0 0 0
0xX0
3/32
X X X X 0 0 0 1
0xX1
5/32
X X X X 0 0 1 0
0xX2
7/32
X X X X 0 0 1 1
0xX3
9/32
X X X X 0 1 0 0
0xX4
11/32
X X X X 0 1 0 1
0xX5
13/32
X X X X 0 1 1 0
0xX6
15/32
X X X X 0 1 1 1
0xX7
17/32
X X X X 1 0 0 0
0xX8
19/32
X X X X 1 0 0 1
0xX9
21/32
X X X X 1 0 1 0
0xXA
23/32
X X X X 1 0 1 1
0xXB
25/32
X X X X 1 1 0 0
0xXC
27/32
X X X X 1 1 0 1
0xXD
29/32
X X X X 1 1 1 0
0xXE
31/32 (max on) X X X X 1 1 1 1
0xXF
Table 7: Intensity register format (address (hex) = 0xXA)
Register Data
Scan Limit
D7
D6
D5
D4
D3
D2
D1
D0
Hex Code
Display digit 0 only
X
X
X
X
X
0
0
0
0xX0
Display digits 0 & 1
X
X
X
X
X
0
0
1
0xX1
Display digits 0 1 2
X
X
X
X
X
0
1
0
0xX2
Display digits 0 1 2 3
X
X
X
X
X
0
1
1
0xX3
Display digits 0 1 2 3 4
X
X
X
X
X
1
0
0
0xX4
Display digits 0 1 2 3 4 5
X
X
X
X
X
1
0
1
0xX5
Display digits 0 1 2 3 4 5
6
X
X
X
X
X
1
1
0
0xX6
Display digits 0 1 2 3 4 5
6 7
X
X
X
X
X
1
1
1
0xX7
Table 8: Scan-limit register format (address (hex) = 0xXB)
Figure 2: Standard 7-segment LED
DP
A
F
E
D
B
C
G
Data Sheet AS1100
Revision 1.32, Oct. 2004
Page 8 of 12
Display Test Register
With the display test register 0Fh all LED can be tested. In
the test mode all LEDs are switched on at maximum
brightness (duty cycle 31/32). All programming of digit and
control registers is maintained. The format of the register is
given in table 10.
Number of
Digits
Displayed
Maximum
Segment Current
(mA)
1
10
2
20
3
30
Table 9: Maximum segment current for 1-, 2-, or 3-digit displays
Register Data
Mode
D7 D6 D5 D4 D3 D2 D1 D0
Normal Operation X
X
X
X
X
X
X
0
Display Test
Mode
X
X
X
X
X
X
X
1
Table 10: Display-test register format (address (hex) = 0xXF)
Note: The AS1100 remains in display-test mode until the
display-test register is reconfigured for normal operation.
No-Op Register (Cascading of As1100)
The no-operation register 00h is used when AS1100s are
cascaded in order to support more than 8 digit displays. The
cascading must be done in a way that all DOUT are
connected to DIN of the following AS1100. The LOAD and
CLK signals are connected to all devices. For a write
operation for example to the fifth device the command must
be followed by four no-operation commands. When the
LOAD signal finally goes to high all shift registers are
latched. The first four devices have got no-operation
commands and only the fifth device sees the intended
command and updates its register.
Reset and external Clock Register
3
This register is addressed via the serial interface. It allows
to switch the device to external clock mode (If D0=1 the
CLK pin of the serial interface operates as system clock
input.) and to apply an external reset (D1). This brings all
registers (except reg. E) to default state. For standard
operation the register contents should be "00h".
3
This register is not used by MAX7219, since it does not support
software reset and external clocks
Register Data
Mode
Address
code (hex)
D7 D6 D5 D4 D3 D2 D1 D0
Normal Operation,
internal clock
0xXE
X X X X X X 0 0
Normal Operation,
external clock
0xXE
X X X X X X 0 1
Reset state,
internal clock
0xXE
X X X X X X 1 0
Reset state,
external clock
0xXE
X X X X X X 1 1
Table 11: Reset and external Clock register (address (hex) = 0xXE)
Applications Information
Supply Bypassing and Wiring
In order to achieve optimal performance the AS1100 shall
be placed very close to the LED display to minimize effects
of electromagnetic interference and wiring inductance.
Furthermore it is recommended to connect a 10F
electrolytic and a 0.1F ceramic capacitor between VDD
and GND to avoid power supply ripple. Also, both GNDs
must be connected to ground.
Selecting R
SET
Resistor and Using External Drivers
The current through the segments is controlled via the
external resistor R
SET
. Segment current is about 100 times
the current in I
SET
. The right values for I
SET
are given in
table 12. The maximum current the AS1100 can drive is
40mA. If higher currents are needed, external drivers must
be used. In that case it is no longer necessary that the
AS1100 drives high currents. A recommended value for
R
SET
is 47k
. In cases that the AS1100 only drives few
digits table 9 specifies the maximum currents and R
SET
must
be set accordingly. Refer to absolute maximum ratings to
calculate acceptable limits for ambient temperature,
segment current, and the LED forward-voltage drop.
V
LED
(V)
I
SEG
(mA)
1.5
2.0
2.5
3.0
3.5
40
12.2
11.8
11.0
10.6
9.69
30
17.8
17.1
15.8
15.0
14.0
20
29.8
28.0
25.9
24.5
22.6
10
66.7
63.7
59.3
55.4
51.2
Table 12: RSET vs. segment current and LED forward voltage
Data Sheet AS1100
Revision 1.32, Oct. 2004
Page 9 of 12
8x8 LED Dot Matrix Driver
The example in Figure 3 uses the AS1100 to drive an 8x8 LED dot matrix. The LED columns have common cathode
and are connected to the DIG0-7 outputs. The rows are connected to the segment drivers. Each of the 64 LEDs can
be addressed separately. The columns are selected via the digits as shown in Table 2. The decode mode register
(0xX9) has to be programmed to `00000000' as stated in Table 4. The single LEDs in a column can be addressed as
stated in Table 6, where D0 corresponds to segment G and d/ to segment DP. For a multiple digit dot matrix several
AS1100 have to be cascaded.
Cascading Drivers
The AS1100 can be cascaded as well. The DOUT pin must be connected to the DIN pin of the following AS1100.
Package
Thermal Resistance (
JA
)
24 Narrow DIP
+75C/W
24 Wide SO
+85C/W
Maximum Junction Temperature (T
J
) = +150C
Maximum Ambient Temperature (T
A
) = +85C
Table 13: Package thermal resistance data
Figure 3: Application example as LED dot matrix driver
P
DIG 7
8x8 LED Dot
M t i
9.53k
VBAT
LOA
CLK
GND GND
DIG 0-
SEG A-G
SEP DP
VDD
4
9
1
12
1
18
19
ISET
DIN
DIG 0
SEG B
SEG A
SEG DP
SEG E
SEG D
SEG C
SEG F
SEG G
8x8 LED Dot
M t i
9.53k
VBAT
LOA
CLK
GND GND
DIG 0-
SEG A-G
SEP DP
VDD
4
9
1
12
1
18
19
ISET
DIN
DIG 0
SEG B
SEG A
SEG DP
SEG E
SEG D
SEG C
SEG F
SEG G
DIG 7
DOUT
24
Diode Arrangement
Data Sheet AS1100
Revision 1.32, Oct. 2004
Page 10 of 12
Computing Power Dissipation
The upper limit for power dissipation (PD) for the AS1100 is determined from the following equation:
PD = (VDD x 0.5mA) + (VDD - V
LED
)(DUTY x I
SEG
x N)
where:
VDD = supply voltage
DUTY = duty cycle set by intensity register
N = number of segments driven (worst case is 8)
V
LED
= LED forward voltage
I
SEG
= segment current set by R
SET
Dissipation Example:
I
SEG
= 40mA, N = 8, DUTY = 31/32, V
LED
= 1.8V at 40mA, VDD = 5.25V
PD = 5.25V(0.5mA) + (5.25V - 1.8V)(31/32 x 40mA x 8) = 1.07W
Thus, for a PDIP package
JA
= +75C/W (from Table 13), the maximum allowed ambient temperature T
A
is given by:
T
J,MAX
= T
A
+ PD x
JA
= 150C = T
A
+1.07W x 75C/W.
where T
A
= +69.7C.
The T
A
limit for SO Packages in the dissipation example above is +59.0C.
Package Information
Inches
Millimeters
Dim Min
Max
Min
Max
A
0.093 0.104 2.35
2.65
A1 0.004 0.012 0.10
0.30
B
0.014 0.019 0.35
0.49
C 0.009 0.013 0.23
0.32
D 0.598 0.614 15.20
15.60
e
0.050
1.27
E
0.291 0.299 7.40
7.60
H 0.394 0.419 10.00
10.65
L
0.016 0.050 0.40
1.27
Figure 4: SOIC-24 package dimensions
Data Sheet AS1100
Revision 1.32, Oct. 2004
Page 11 of 12
Inches
Millimeters
Dim
Min
Max
Min
Max
A
---
0.180
---
4.572
A1 0.015
---
0.380
---
A2 0.125 .0175 3.180 4.450
A3 0.055 0.080 1.400 2.030
B
0.015 0.022 0.381 0.560
B1 0.045 0.065 1.140 1.650
C
0.008 0.014 0.200 0.355
D
1.140 1.265 28.96 32.13
D1 0.005 0.080 0.130 2.030
E
0.300 0.325 7.620 8.260
E1 0.240 0.310 6.100 7.870
e
0.100 BSC
2.54 BSC.
eA
0.300 BSC
7.62 BSC.
eB
0.400 BSC
10.2 BSC.
L
0.115 0.150 2.921 3.810
Figure 5: PDIP-24 package dimensions
Figure 6: Segment driver capability
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
0
5
10
15
20
25
30
35
40
45
50
Segment Driver Capability, VDD = 5V, Logic Level = High
Voltage below VDD at output in V
S
egm
en
t
C
u
r
r
e
nt
i
n
m
A
Lower Limit
Upper Limit
Data Sheet AS1100
Revision 1.32, Oct. 2004
Page 12 of 12
Ordering Information
Part
Temp Range
Pin
Package
Delivery
Form
AS1100PL
0C to +70C 24 Narrow
Plastic DIP
Tubes
AS1100WL
0C to +70C 24 Wide SO Tubes
AS1100PE
-40C to +85C 24 Narrow
Plastic DIP
Tubes
AS1100WE
-40C to +85C 24 Wide SO Tubes
AS1100WL-T
0C to +70C 24 Wide SO T&R
AS1100WE-T -40C to +85C 24 Wide SO T&R
For Pb-free package use suffix `-Z`
Contact
austriamicrosystems AG
A 8141 Schloss Premsttten, Austria
T. +43 (0) 3136 500 0
F. +43 (0) 3136 525 01
info@austriamicrosystems.com
Copyright
Copyright 2004 austriamicrosystems. Trademarks
registered . All rights reserved. The material herein may
not be reproduced, adapted, merged, translated, stored, or
used without the prior written consent of the copyright
owner. To the best of its knowledge, austriamicrosystems
asserts that the information contained in this publication is
accurate and correct.
Austriamicrosystems reserves the right to change the circuitry and
specifications without notice at any time.
Figure 7: Segment Current versa R
SET
10
1
10
2
0
5
10
15
20
25
30
35
40
45
50
Segment Current = f(R
SET
)
R
SET
in kOhm
I
SE
G
M
E
N
T
in
m
A
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