AS1108
4-Digit LED Display Driver
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D a ta S h e e t
1 General Description
The AS1108 is a compact display driver for 7-segment
numeric displays of up to 4 digits. The device can be
programmed via SPI, QSPI, and Microwire as well as a
conventional 4-wire serial interface.
The device includes an integrated BCD code-B/HEX
decoder, multiplex scan circuitry, segment and display
drivers, and a 32-bit memory. Internal memory stores
the LED settings, eliminating the need for continuous
device reprogramming.
Every segment can be individually addressed and
updated separately. Only one external resistor (R
SET
) is
required to set the current through the LED display. LED
brightness can be controlled by analog or digital means.
The device can be programmed to use the internal
code-B/HEX decoder to display numeric digits or to
directly address each segment.
The AS1108 features an extremely low shutdown cur-
rent of typically 3A, and an operational current of less
than 500A. The number of digits can be programmed,
the device can be reset by software, and an external
clock is also supported. Additionally, segment blinking
can be synchronized across multiple drivers.
The AS1108 provides several test modes for easy appli-
cation debugging.
The device is available in a 20-pin DIP and a 20-pin
SOIC package.
Figure 1. Typical Application Diagram
2 Key Features
!
10MHz SPI-, QSPI-, Microwire-Compatible
Serial I/O
!
Individual LED Segment Control
!
Segment Blinking Control (can be synchronized
across multiple drivers)
!
Hexadecimal- or BCD-Code/No-Decode
Digit Selection
!
3A Low-Power Shutdown Current (typ;
data retained)
!
Extremely Low Operating Current 0.5mA in
Open-Loop
!
Digital and Analog Brightness Control
!
Display Blanked on Power-Up
!
Drive Common-Cathode LED Displays
!
Supply Voltage Range: +2.7 to +5.5V
!
Software Reset
!
Optional External Clock
!
Packages:
- 20-pin DIP
- 20-pin SOIC
3 Applications
The AS1108 is ideal for bar-graph displays, instrument-
panel meters, LED matrix displays, dot matrix displays,
set-top boxes, white goods, professional audio equip-
ment, medical equipment, industrial controllers and
panel meters.
AS1108
4-Digit Microprocessor Display
DIG0 to
DIG3
SEG A to G
SEP DP
4 Digits
8 Segments
I/O
I/O
SCK
V
DD
I
SET
DIN
CLK
GND
GND
LOAD/CSN
+5V
9.53k
Micro-
processor
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Data Sheet
4 Absolute Maximum Ratings
Stresses beyond those listed in Table 1 may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in Section 5 Electrical
Characteristics on page 3 is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Table 1. Absolute Maximum Ratings
Parameter
Min
Max
Units
Notes
Voltage (with respect to
GND)
V
DD
-0.3
7
V
DIN, CLK, LOAD/CSN
-0.3
7
V
All Other Pins
-0.3
7 or
V
DD
+
0.3
V
Current
DIG 0:DIG 3
Sink Current
500
mA
SEG A:SEG G, SEG DP
100
mA
Continuous Power
Dissipation (T
AMB
= +85C)
Narrow Plastic DIP
1066
mW
Derate 13.3mW/C above +70C
Wide SOIC
941
mW
Derate 11.8mW/C above +70C
Operating Temperature Ranges (T
MIN
toT
MAX
) 0
+70
C
Storage Temperature Range
-65
+150
C
Package Body Temperature (Wide SOIC)
1
1. The reflow peak soldering temperature (body temperature) is specified according to IPC/JEDEC J-STD-020C
"Moisture/Reflow Sensitivity Classification for non-hermetic Solid State Surface Mount Devices".
+260
C
Soldering Temperature (Narrow DIP)
2
2. Specified according JESD22-B106 "Resistance to Soldering Temperature for Through-Hole Mounted Devices".
+260
C
Humidity
5
85
%
Non-condensing
Electrostatic Discharge
3
3. Norm: MIL 883 E method 3015.
Digital Outputs
1000
V
All Other Pins
1000
V
Latch-Up Immunity
4
4. Norm: JEDEC 17.
200
mA
All pins.
Except pin 11: 180mA.
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Data Sheet
5 Electrical Characteristics
Conditions: V
DD
= 2.7 to 5.5V, R
SET
= 9.53k
1%, T
AMB
= T
MIN
to T
MAX
(unless otherwise specified).
Note: See Figure 9 on page 6 for additional timing information.
Table 2. Electrical Characteristics
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Operating Supply Voltage
V
DD
2.7
5.0
5.5
V
Shutdown Supply Current
I
DDSD
All digital inputs at V
DD
or GND,
T
AMB
= +25C
10
A
Operating Supply Current
I
DD
R
SET
= open circuit.
1
mA
All segments and decimal point
on; I
SEG
= -40mA.
330
Display Scan Rate
f
OSC
4 digits scanned
1000
1600 2600
Hz
Digit Drive Sink Current
I
DIGIT
V
OUT
= 0.65V
320
mA
Segment Drive Source Current
I
SEG
V
DD
= 5.0V, V
OUT
= (V
DD
-1V)
-30
-40
-45
mA
Segment Drive Current Matching
I
SEG
3.0
%
Digit Drive Source Current
I
DIGIT
Digit off, V
DIGIT
= (V
DD
- 0.3V)
-2
mA
Segment Drive Sink Current
I
SEG
Segment off, V
SEG
= 0.3V
5
mA
Slow Segment Blink Period (ON
phase, Internal Oscillator)
t
SLOWBLINK
0.64
1
1.65
s
Fast Segment Blink Period
(ON phase, Internal Oscillator)
t
FASTBLINK
0.32
0.5
0.83
s
Fast or Slow Segment Blink Duty
Cycle (Guaranteed by design)
49.9
50
50.1
%
Table 3. Logic Inputs/Outputs Characteristics
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Input Current DIN, CLK, LOAD/CSN
I
IH
, I
IL
V
IN
= 0V or V
DD
-1
1
A
Logic High Input Voltage
V
IH
0.7 x V
DD
V
Logic Low Input Voltage
V
IL
V
DD
= 5.0V 10%
0.8
V
V
DD
= 3.0V 10%
0.6
Output High Voltage
V
OH
DOUT, I
SOURCE
= -1mA,
V
DD
= 5.0V 10%
V
DD
- 1
V
DOUT, I
SOURCE
= -1mA,
V
DD
= 3.0V 10%
V
DD
- 0.5
Output Low Voltage
V
OL
DOUT, I
SINK
= 1.6mA
0.4
V
Hysteresis Voltage
V
I
DIN, CLK, LOAD/CSN
1 V
Table 4. Timing Characteristics
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
CLK Clock Period
t
CP
100
ns
CLK Pulse Width High
t
CH
50
ns
CLK Pulse Width Low
t
CL
50
ns
CSMFall-to-CLK Rise Setup Time
(AS1108 SPI-programmed)
t
CSS
25
ns
CLK Rise-to -LOAD/CSN Rise Hold Time
t
CSH
0
ns
DIN Setup Time
t
DS
25
ns
DIN Hold Time
t
DH
0
ns
Output Data Propagation Delay
t
DO
C
LOAD
= 50pF
25
ns
LOAD Rising Edge-to-Next Clock Rising Edge
t
LDCK
50
ns
Minimum LOAD/CSN Pulse High
t
CSW
50
ns
Data-to-Segment Delay
t
DSPD
2.25
ms
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Data Sheet
6 Typical Operating Characteristics
V
DD
= 5V, R
SET
= 9.53k
, T
AMB
= 25C (unless otherwise specified).
Figure 2. Scan Frequency vs.Temperature
Figure 3. Scan Frequency vs. V
DD
Figure 4. I
SEG
vs. Temperature
Figure 5. I
SEG
vs. V
DD
Figure 6. I
SEG
vs. V
OUT
Figure 7. I
SEG
vs. V
OUT
1860
1880
1900
1920
1940
1960
1980
-40
-20
0
20
40
60
80
T
AMB
(C)
F
OSC
(Hz)
1800
1820
1840
1860
1880
1900
1920
1940
1960
2
3
4
5
6
V
DD
(V)
F
OSC
(Hz)
0
5
10
15
20
25
30
35
40
45
50
-40
-20
0
20
40
60
80
T
AMB
(C)
I
SEG
(mA)
0
10
20
30
40
50
60
2
2.5
3
3.5
4
4.5
5
5.5
6
V
DD
(V)
I
SEG
(mA)
V
DD
= 5V, V
OUT
= 2.4V
V
DD
= 5V, V
OUT
= 4V
V
DD
= 2.7V, V
OUT
= 2V
V
DD
= 2.7V, V
OUT
= 2.4V
V
OUT
= 1.7V
V
OUT
= 2.4V
V
OUT
= 4V
0
5
10
15
20
25
30
35
40
45
50
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
V
OUT
(V)
I
SEG
(mA)
V
DD
= 2.7V
0
5
10
15
20
25
0
0.5
1
1.5
2
2.5
V
OUT
(V)
I
SEG
(mA)
R
SET
= 10k
R
SET
= 20k
R
SET
= 40k
R
SET
= 40k
R
SET
= 10k
R
SET
= 20k
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Data Sheet
Figure 8. I
SEG
vs. R
SET
0
10
20
30
40
50
60
0
10
20
30
40
50
60
70
80
R
SET
(k)
I
SEG
(mA)
V
OUT
= 2.4V
V
OUT
= 4V
V
OUT
= 2V
V
OUT
= 1.7V
V
DD
= 2.7V
V
DD
= 5V
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Data Sheet
Serial-Addressing Format
7 Detailed Description
Serial-Addressing Format
Programming the AS1108 is accomplished by writing to the device's internal registers (see Digit- and Control-Registers
on page 7) via the 4-wire serial interface. A programming sequence consists of 16-bit packages as depicted in Table 5.
The data is shifted into the internal 16-bit register with the rising edge of the CLK signal. With the rising edge of the
LOAD/CSN signal the data is latched into a digit- or control-register. The LOAD/CSN signal must go high after the 16th
rising clock edge.
The LOAD/CSN signal can also come later but this must happen just before the next rising edge of CLK, otherwise the
data will be lost. The contents of the internal shift register are applied 16.5 clock cycles later to pin DOUT. The data is
clocked out at the falling edge of CLK.
The first 4 bits (D15:D12) are "don't care" settings, bits D11:D8 contain the register address, and bits D7:D0 contain the
data. The first bit is D15, the most significant bit (MSB). The exact timing is shown in Figure 9.
Initial Power-Up
On initial power-up, the AS1108 registers are reset to their default values, the display is blanked, and the device goes
into shutdown mode. All registers should be programmed for normal operation at this time.
Note: The default settings enable only scanning of one digit; the internal decoder is disabled and the Intensity Control
Register (see page 10) is set to the minimum values.
Figure 9. Interface Timing
Table 5. 16-Bit Serial Data Format
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
Register Address (see Table 6) MSB
Data
LSB
t
CL
LOAD/
CSN
CLK
DIN
DOUT
D15
D14
D1
D0
t
DO
t
CSS
t
DS
t
DH
t
CH
t
CP
t
CSH
t
CSW
t
LDCK
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Data Sheet
Shutdown Mode
Shutdown Mode
The AS1108 features a shutdown mode, consuming only 10A (max) current. Shutdown mode is entered via a write to
the Shutdown Register (see Table 7). At that point, all segment current sources are pulled to ground and all digit driv-
ers are connected to V
DD
, so that all segments are blanked.
Note: During shutdown mode the Digit-Registers maintain their data.
Shutdown mode can either be used as a means to reduce power consumption or for generating a flashing display
(repeatedly entering and leaving shutdown mode). For minimum supply current in shutdown mode, logic input should
be at GND or V
DD
(CMOS logic level).
The device needs typically 250s to exit shutdown mode, and during shutdown mode the AS1108 is fully programma-
ble. Only the display test mode (see page 9) overrides shutdown mode.
When entering or leaving shutdown mode, the Feature Register is reset to its default values (all 0s) when Shutdown
Register bit D7 (page 8) = 0. When bit D7 = 1, the Feature Register is left unchanged when entering or leaving shut-
down mode.
Note: If the AS1108 is used with an external clock, Shutdown Register bit D7 should be set to 1 when writing to the
Shutdown Register.
Digit- and Control-Registers
The AS1108 contains four Digit-Registers and six control-registers, which are listed in Table 6. All registers are
selected using a 4-bit address word, and communication is done via the serial interface.
!
Digit Registers These registers are realized with an on-chip 32-bit memory. Each digit can be controlled directly
without rewriting the whole register contents.
!
Control Registers These registers consist of decode mode, display intensity, number of scanned digits, shut-
down, display test and features selection registers.
Table 6. Register Address Map
Register
HEX Code
Address
Page
D15:D12
D11
D10
D9
D8
No-Op
0xX0
X
0
0
0
0
11
Digit 0
0xX1
X
0
0
0
1
N/A
Digit 1
0xX2
X
0
0
1
0
N/A
Digit 2
0xX3
X
0
0
1
1
N/A
Digit 3
0xX4
X
0
1
0
0
N/A
Decode-Mode
0xX9
X
1
0
0
1
8
Intensity Control
0xXA
X
1
0
1
0
10
Scan Limit
0xXB
X
1
0
1
1
10
Shutdown
0xXC
X
1
1
0
0
8
N/A
0xXD
X
1
1
0
1
N/A
Feature
0xXE
X
1
1
1
0
11
Display Test
0xXF
X
1
1
1
1
9
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Data Sheet
Digit- and Control-Registers
Shutdown Register (0xXC)
The Shutdown Register controls AS1108 shutdown mode (see Shutdown Mode on page 7).
Decode Enable Register (0xX9)
The Decode Enable Register sets the decode mode. BCD/HEX decoding (either BCD code characters 0:9, E, H, L,
P, and -, or HEX code characters 0:9 and A:F) is selected by bit D2 (page 11) of the Feature Register. The Decode
Enable Register is used to select the decode mode or no-decode for each digit. Each bit in the Decode Enable Regis-
ter corresponds to its respective display digit (i.e., bit D0 corresponds to digit 0, bit D1 corresponds to digit 1 and so
on). Table 9 lists some examples of the possible settings for the Decode Enable Register bits.
Note: A logic high enables decoding and a logic low bypasses the decoder altogether.
When decode mode is used, the decoder looks only at the lower-nibble (bits D3:D0) of the data in the Digit-Registers,
disregarding bits D6:D4. Bit D7 sets the decimal point (SEG DP) independent of the decoder and is positive logic (bit
D7 = 1 turns the decimal point on). Table 9 lists the code-B font; Table 10 lists the HEX font.
When no-decode mode is selected, data bits D7:D0 of the Digit-Registers correspond to the segment lines of the
AS1108. Table 11 shows the 1:1 pairing of each data bit and the appropriate segment line.
Figure 10. Standard 7-Segment LED Intensity Control and Inter-Digit Blanking
Table 7. Shutdown Register Format (Address (HEX) = 0xXC))
Mode
HEX Code
Register Data
D7
D6
D5
D4
D3
D2
D1
D0
Shutdown Mode,
Reset Feature Register to Default Settings
0x00
0
X
X
X
X
X
X
0
Shutdown Mode, Feature Register Unchanged
0x80
1
X
X
X
X
X
X
0
Normal Operation,
Reset Feature Register to Default Settings
0x01
0
X
X
X
X
X
X
1
Normal Operation, Feature Register Unchanged
0x81
1
X
X
X
X
X
X
1
Table 8. Decode Enable Register Format (Address (HEX) = 0xX9))
Decode Mode
HEX Code
Register Data
D7
D6
D5
D4
D3
D2
D1
D0
No decode for digits 3:0
0x00
X
X
X
X
0
0
0
0
Code-B/HEX decode for digit 0. No decode for digits 3:1
0x01
X
X
X
X
0
0
0
1
Code-B/HEX decode for digits 3:0
0xFF
X
X
X
X
1
1
1
1
Table 9. Code-B Font
7-Segment
Character
Register Data
On Segments = 1
D7
D6:D4
D3
D2
D1
D0
DP
A
B
C
D
E
F
G
0
X
0
0
0
0
1
1
1
1
1
1
0
1
X
0
0
0
1
0
1
1
0
0
0
0
2
X
0
0
1
0
1
1
0
1
1
0
1
3
X
0
0
1
1
1
1
1
1
0
0
1
4
X
0
1
0
0
0
1
1
0
0
1
1
5
X
0
1
0
1
1
0
1
1
0
1
1
A
B
G
F
E
D
C
DP
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Data Sheet
Digit- and Control-Registers
Display-Test Register (0xXF)
The AS1108 can operate in two modes: normal mode and display test mode. In display test mode all LEDs are
switched on at maximum brightness (duty cycle is 15/16). The device remains in display-test mode until the Display-
Test Register is set for normal operation.
Note: All settings of the Digit- and Control-Registers are maintained.
6
X
0
1
1
0
1
0
1
1
1
1
1
7
X
0
1
1
1
1
1
1
0
0
0
0
8
X
1
0
0
0
1
1
1
1
1
1
1
9
X
1
0
0
1
1
1
1
1
0
1
1
-
X
1
0
1
0
0
0
0
0
0
0
1
E
X
1
0
1
1
1
0
0
1
1
1
1
H
X
1
1
0
0
0
1
1
0
1
1
1
L
X
1
1
0
1
0
0
0
1
1
1
0
P
X
1
1
1
0
1
1
0
0
1
1
1
Blank
X
1
1
1
1
0
0
0
0
0
0
0
The decimal point is enabled by setting bit D7 = 1.
Table 10. HEX Font
7-Segment
Character
Register Data
On Segments = 1
D7
D6:D4
D3
D2
D1
D0
DP
A
B
C
D
E
F
G
0
X
0
0
0
0
1
1
1
1
1
1
0
1
X
0
0
0
1
0
1
1
0
0
0
0
2
X
0
0
1
0
1
1
0
1
1
0
1
3
X
0
0
1
1
1
1
1
1
0
0
1
4
X
0
1
0
0
0
1
1
0
0
1
1
5
X
0
1
0
1
1
0
1
1
0
1
1
6
X
0
1
1
0
1
0
1
1
1
1
1
7
X
0
1
1
1
1
1
1
0
0
0
0
8
X
1
0
0
0
1
1
1
1
1
1
1
9
X
1
0
0
1
1
1
1
1
0
1
1
A
X
1
0
1
0
1
1
1
0
1
1
1
b
X
1
0
1
1
0
0
1
1
1
1
1
C
X
1
1
0
0
1
0
0
1
1
1
0
d
X
1
1
0
1
0
1
1
1
1
0
1
E
X
1
1
1
0
1
0
0
1
1
1
1
F
X
1
1
1
1
1
0
0
0
1
1
1
The decimal point is enabled by setting bit D7 = 1.
Table 11. No-Decode Mode Data Bits and Corresponding Segment Lines
D7
D6
D5
D4
D3
D2
D1
D0
Corresponding Segment Line
DP
A
B
C
D
E
F
G
Table 12. Display-Test Register Format (Address (HEX) = 0xXF))
Mode
Register Data
D7
D6
D5
D4
D3
D2
D1
D0
Normal Operation
X
X
X
X
X
X
X
0
Display Test Mode
X
X
X
X
X
X
X
1
Table 9. Code-B Font (Continued)
7-Segment
Character
Register Data
On Segments = 1
D7
D6:D4
D3
D2
D1
D0
DP
A
B
C
D
E
F
G
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Data Sheet
Digit- and Control-Registers
Intensity Control Register (0xXA)
The brightness of the display can be controlled by digital means using the Intensity Control Register and by analog
means using R
SET
(see Selecting RSET Resistor Value and Using External Drivers on page 12).
Display brightness is controlled by an integrated pulse-width modulator which is controlled by the lower-nibble of the
Intensity Control Register. The modulator scales the average segment-current in 16 steps from a maximum of 31/32
down to 1/32 of the peak current set by R
SET
.
Scan-Limit Register (0x0B)
The Scan-Limit Register controls which of the digits are to be displayed. When all 4 digits are to be displayed, the
update frequency is typically 1600Hz. If the number of digits displayed is reduced, the update frequency is increased.
The frequency can be calculated using 8fOSC/N, where N is the number of digits. Since the number of displayed digits
influences the brightness, R
SET
should be adjusted accordingly. Table 15 lists the maximum allowed current when
fewer than 4 digits are used.
Note: To avoid differences in brightness this register should not be used to blank parts of the display (leading zeros).
Table 13. Intensity Register Format (Address (HEX) = 0xXA))
Duty Cycle
HEX Code
Register Data
AS1108
D7
D6
D5
D4
D3
D2
D1
D0
1/32 (min on)
0xX0
X
X
X
X
0
0
0
0
3/32
0xX1
X
X
X
X
0
0
0
1
5/32
0xX2
X
X
X
X
0
0
1
0
7/32
0xX3
X
X
X
X
0
0
1
1
9/32
0xX4
X
X
X
X
0
1
0
0
11/32
0xX5
X
X
X
X
0
1
0
1
13/32
0xX6
X
X
X
X
0
1
1
0
15/32
0xX7
X
X
X
X
0
1
1
1
17/32
0xX8
X
X
X
X
1
0
0
0
19/32
0xX9
X
X
X
X
1
0
0
1
21/32
0xXA
X
X
X
X
1
0
1
0
23/32
0xXB
X
X
X
X
1
0
1
1
25/32
0xXC
X
X
X
X
1
1
0
0
27/32
0xXD
X
X
X
X
1
1
0
1
29/32
0xXE
X
X
X
X
1
1
1
0
31/32 (max on)
0xXF
X
X
X
X
1
1
1
1
Table 14. Scan-Limit Register Format (Address (HEX) = 0xXB))
Scan Limit
HEX Code
Register Data
D7
D6
D5
D4
D3
D2
D1
D0
Display digit 0 only (see Table 15)
0xX0
X
X
X
X
X
0
0
0
Display digits 0:1 (see Table 15)
0xX1
X
X
X
X
X
0
0
1
Display digits 0:2 (see Table 15)
0xX2
X
X
X
X
X
0
1
0
Display digits 0:3
0xX3
X
X
X
X
X
0
1
1
Table 15. Maximum Segment Current for 1-, 2-, or 3-Digit Displays
Number of Digits Displayed
Maximum Segment Current (mA)
1
10
2
20
3
30
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Data Sheet
Digit- and Control-Registers
Feature Register
(0xXE)
The Feature Register is used for switching the device into external clock mode, applying an external reset, selecting
code-B or HEX decoding, enabling or disabling blinking, enabling or disabling the SPI-compatible interface, setting the
blinking rate, and resetting the blink timing.
Note: At power-up the Feature Register is initialized to 0.
No-Op Register (0xX0)
The No-Op Register is used when multiple AS1108 devices are cascaded in order to support displays with more than 4
digits. The cascading must be done in such a way that all DOUT pins are connected to DIN of the next AS1108 (see
Figure 11 on page 14). The LOAD/CSN and CLK signals are connected to all devices.
For example, if five devices are cascaded, in order to perform a write operation to the fifth device, the write-command
must be followed by four no-operation commands. When the LOAD/CSN signal goes high, all shift registers are
latched. The first four devices will receive no-operation commands and only the fifth device will receive the intended
operation command, and subsequently update its register.
Table 16. Feature Register Summary
D7
D6
D5
D4
D3
D2
D1
D0
blink_
start
sync
blink_
freq_sel
blink_en
spi_en
decode_sel
reg_res
clk_en
Table 17. Feature Register Bit Descriptions (Address (HEX) = 0xXE))
Addr: 0xXE
Feature Register
Enables and disables various device features.
Bit
Bit Name
Default
Access
Bit Description
D0
clk_en
0
R/W
External clock select.
0 = Internal oscillator is used for system clock.
1 = Pin CLK of the serial interface operates as system clock input.
D1
reg_res
0
R/W
Resets all control registers except the Feature Register.
0 = Reset Disabled. Normal operation.
1 = All control registers are reset to default state (except the Feature
Register) identically after power-up.
Note: The Digit Registers maintain their data.
D2
decode_sel
0
R/W
Selects display decoding.
0 = Enable Code-B decoding (see Table 9 on page 8).
1 = Enable HEX decoding (see Table 10 on page 9).
D3
spi_en
0
R/W
Enables the SPI-compatible interface.
0 = Disable SPI-compatible interface.
1 = Enable the SPI-compatible interface.
D4
blink_en
0
R/W
Enables blinking.
0 = Disable blinking.
1 = Enable blinking.
D5 blink_freq_sel
0
R/W
Sets blink with low frequency (with the internal oscillator enabled):
0 = Blink period typically is 1 second (0.5s on, 0.5s off).
1 = Blink period is 2 seconds (1s on, 1s off).
D6
sync
0
R/W
Synchronizes blinking on the rising edge of pin LOAD/CSN. The
multiplex and blink timing counter is cleared on the rising edge of pin
LOAD/CSN. By setting this bit in multiple AS1108 devices, the blink
timing can be synchronized across all the devices.
D7
blink_start
0
R/W
Start Blinking with display enabled phase. When bit D4 (blink_en) is set,
bit D7 determines how blinking starts.
0 = Blinking starts with the display turned off.
1 = Blinking starts with the display turned on.
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Data Sheet
Supply Bypassing and Wiring
8 Typical Application
Supply Bypassing and Wiring
In order to achieve optimal performance the AS1108 should be placed very close to the LED display to minimize
effects of electromagnetic interference and wiring inductance.
Furthermore, a 10F electrolytic and a 0.1F ceramic capacitor should be connected between pins V
DD
and GND to
avoid power supply ripple (see Figure 11 on page 14).
Note: Both GND pins must be connected to ground.
Selecting R
SET
Resistor Value and Using External Drivers
Brightness of the display segments is controlled via R
SET
. The current that flows between V
DD
and I
SET
defines the
current that flows through the LEDs.
Segment current is about 200 times the current in I
SET
. Typical values for R
SET
for different segment currents, operat-
ing voltages, and LED voltage drop (V
LED
) are given in Tables 18 - 22. The maximum current the AS1108 can drive is
40mA. If higher currents are needed, external drivers must be used, in which case it is no longer necessary that the
device drive high currents.
In cases where the device drives only a few digits, Table 15 specifies the maximum currents, and R
SET
must be set
accordingly.
Note: The display brightness can also be logically controlled (see Selecting RSET Resistor Value and Using External
Drivers on page 12).
Table 18. R
SET
vs. Segment Current and LED Forward Voltage, V
DD
= 2.7V
I
SEG
(mA)
V
LED
(V)
1.5
2.0
40
5k
4.4k
30
6.9k
5.9k
20
10.7k
9.6k
10
22.2k
20.7k
Table 19. R
SET
vs. Segment Current and LED Forward Voltage, V
DD
= 3.3V
I
SEG
(mA)
V
LED
(V)
1.5
2.0
2.5
40
6.7k
6.4k
5.7k
30
9.1k
8.8k
8.1k
20
13.9k
13.3k
12.6k
10
28.8k
27.7k
26k
Table 20. R
SET
vs. Segment Current and LED Forward Voltage, V
DD
= 3.6V
I
SEG
(mA)
V
LED
(V)
1.5
2.0
2.5
3.0
40
7.5k
7.2k
6.6k
5.5k
30
10.18k
9.8k
9.2k
7.5k
20
15.6k
15k
14.3k
13k
10
31.9k
31k
29.5k
27.3k
Table 21. R
SET
vs. Segment Current and LED Forward Voltage, V
DD
= 4.0V
I
SEG
(mA)
V
LED
(V)
1.5
2.0
2.5
3.0
3.5
40
8.6k
8.3k
7.9k
7.6k
5.2k
30
11.6k
11.2k
10.8k
9.9k
7.8k
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AS1108
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Data Sheet
Selecting RSET Resistor Value and Using External Drivers
20
17.7k
17.3k
16.6k
15.6k
13.6k
10
36.89k
35.7k
34.5k
32.5k
29.1k
Table 22. R
SET
vs. Segment Current and LED Forward Voltage, V
DD
= 5.0V
I
SEG
(mA)
V
LED
(V)
1.5
2.0
2.5
3.0
3.5
4.0
40
11.35k
11.12k
10.84k
10.49k
10.2k
9.9k
30
15.4k
15.1k
14.7k
14.4k
13.6k
13.1k
20
23.6k
23.1k
22.6k
22k
21.1k
20.2k
10
48.9k
47.8k
46.9k
45.4k
43.8k
42k
Table 23. Package Thermal Data
Package
Thermal Resistance (
JA
)
20 Narrow DIP
+75C/W
20 Wide SOIC
+85C/W
Table 21. R
SET
vs. Segment Current and LED Forward Voltage, V
DD
= 4.0V (Continued)
I
SEG
(mA)
V
LED
(V)
1.5
2.0
2.5
3.0
3.5
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AS1108
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Data Sheet
4x8 LED Dot Matrix Driver
4x8 LED Dot Matrix Driver
The application example in Figure 11 shows the AS1108 as a 4x8 LED dot matrix driver.
The LED columns have common cathodes and are connected to the DIG0:3 outputs. The rows are connected to the
segment drivers. Each of the 32 LEDs can be addressed separately. The columns are selected via the digits as listed
in Table 6 on page 7.
The Decode Enable Register (see page 8) must be set to `00000000' as described in Table 8 on page 8. Single LEDs
in a column can be addressed as described in Table 11 on page 9, where bit D0 corresponds to segment G and bit D7
corresponds to segment DP.
Note: For a multiple-digit dot matrix, multiple AS1108 devices must be cascaded.
Figure 11. Application Example as LED Dot Matrix Driver
Cascading Drivers
If more than 4 digits or 32 LEDs are needed, it is recommended to use the AS1106/AS1107, although several AS1108
devices can be cascaded.
The example in Figure 4 drives 2 dot matrix digits using a 4-wire microprocessor interface. All Scan-Limit Registers
should be set to the same value so that one display will not appear brighter than the other.
For example, to display 6 digits, set both Scan-Limit Registers to display 3 digits so that both displays have a 1/3 duty
cycle per digit. If 5 digits are needed, set both Scan-Limit Registers to display 3 digits and leave one digit unconnected.
Otherwise, if one driver is set to display 3 digits and the other to display 2 digits one display will appear brighter
because its duty cycle per digit will be 1/2 and the other display's duty cycle will be 1/3.
Note: Refer to No-Op Register (0xX0) on page 11 for additional information.
SEG G
DIG0:3
I
SET
DIN
GND
GND
LOAD/CSN
CLK
V
DD
SEG A:G
SEG DP
9.53k
DIG0:3
I
SET
DIN
GND
GND
LOAD/CSN
CLK
V
DD
SEG A:G
SEG DP
9.53k
DOUT
4x8 LED
Dot Matrix
Diode Arrangement
V
BAT
V
BAT
Micro-
Processor
SEG A
SEG DP
SEG B
SEG C
SEG D
SEG E
SEG F
SEG G
4x8 LED
Dot Matrix
SEG A
SEG DP
SEG B
SEG C
SEG D
SEG E
SEG F
AS1108
AS1108
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AS1108
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Data Sheet
Pin Assignments
9 Pinout and Packaging
Pin Assignments
Figure 12. DIP and SO Pin Assignments (Top View)
Pin Descriptions
Table 24. Pin Descriptions
Pin
Name
Pin
Number
Description
DOUT
1
Serial-Data Output. The data into pin DIN is valid at pin DOUT 16.5 clock
cycles later. This pin is used to daisy-chain several AS1108 devices and is
never high-impedance.
DIN
2
Serial-Data Input. Data is loaded into the internal 16-bit shift register on the
rising edge of pin CLK.
DIG 0:DIG 3
3, 5, 6, 8
Digit Drive Lines. 4 four-digit drive lines that sink current from the display
common cathode. The AS1108 pulls the digit outputs to V
DD
when turned
off.
GND
4, 7
Ground. Both GND pins must be connected.
LOAD/CSN
9
Load-Data Input. The last 16 bits of serial data are latched on the rising
edge of this pin.
Chip-Select Input (AS1108 SPI-enabled only). Serial data is loaded into the
shift register while this pin is low. The last 16 bits of serial data are latched
on the rising edge of this pin.
CLK
10
Serial-Clock Input. 10MHz maximum rate. Data is shifted into the internal
shift register on the rising edge of this pin. Data is clocked out of DOUT on
the falling edge of this pin. On the AS1108 SPI-enabled, the CLK input is
active only while pin LOAD/CSN is low.
SEG A:SEG G, SEG DP
11, 12, 13,
14, 17, 18,
19, 20
Seven Segment and Decimal Point Drive Lines. 8 seven-segment drives
and decimal point drive that source current to the display. When a segment
driver is turned off it is pulled to GND.
I
SET
15
Set Segment Current. Connect to V
DD
through R
SET
to set the peak
segment current (see Selecting RSET Resistor Value and Using External
Drivers on page 12).
V
DD
16
Positive Supply Voltage. Connect to +2.7 to +5.5V supply.
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
SEG D
SEG DP
SEG E
SEG C
V
DD
I
SET
SEG G
SEG B
SEG F
SEG A
DOUT
DIN
DIG 0
GND
DIG 2
DIG 3
GND
DIG 1
LOAD/CSN
CLK
AS1108
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AS1108
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Data Sheet
Package Drawings and Markings
Package Drawings and Markings
The AS1108 is available in a 20-pin DIP and a 20-pin SOIC package.
Figure 13. 20-pin DIP Package
Symbol
Inches
Min
Nom
Max
A
.210
A1
.015
A2
.115
.130
.195
b
0.15
0.18
0.22
b1
0.14
0.18
0.20
b2
0.55
0.60
0.65
c
.008
.010
.012
c1
.008
.010
.011
D
1.025
1.030
1.035
D1
.030
.035
.040
E
.300
.325
E1
.240
.252
.260
e
.100 BSC
eA
.300 BSC
eB
.430
eC
.000
.060
L
.125
.135
N
20
Q1
.055
.060
.065
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AS1108
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Data Sheet
Package Drawings and Markings
Figure 14. 20-pin SOIC Package
Symbol
Millimeters
Min
Max
A
2.44
2.64
A1
0.10
0.30
A2
2.24
2.44
B
0.36
0.46
C
0.23
0.32
e
1.27 BSC
H
10.11
10.51
h
0.31
0.71
J
0.53
0.73
K
7 BSC
L
0.51
1.01
R
0.63
0.89
ZD
0.66 REF
0
8
Notes:
1. Lead coplanarity should be 0 to 0.10mm (.004") max.
2. Package surface finishing:
(2.1) Top: matte (charmilles #18-30).
(2.2) All sides: matte (charmilles #18-30).
(2.3) Bottom: smooth or matte (charmilles #18-30).
3. All dimensions exclusive of mold flash, and end flash from the pack-
age body shall not exceed 0.24mm (0.10") per side (D).
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AS1108
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Data Sheet
10 Ordering Information
The AS1108 is available in a 20-pin DIP and a 20-pin SOIC package.
Table 25. Ordering Information
Part
Temperature Range
Delivery Form
Package
AS1108PL
0 to +70C
Tubes
20-pin Narrow Plastic DIP, Pb-free
AS1108WL
0 to +70C
Tubes
20-pin Wide SO, Pb-free
AS1108WL-T
0 to +70C
Tape and Reel
20-pin Wide SO, Pb-free
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AS1108
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Data Sheet
Copyrights
Copyright 1997-2005, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe.
Trademarks Registered . All rights reserved. The material herein may not be reproduced, adapted, merged, trans-
lated, stored, or used without the prior written consent of the copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing
in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding
the information set forth herein or regarding the freedom of the described devices from patent infringement. austriami-
crosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior
to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information.
This product is intended for use in normal commercial applications. Applications requiring extended temperature
range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-
sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for
each application.
The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However,
austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to
personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or
consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the tech-
nical data herein. No obligation or liability to recipient or any third party shall arise or flow out of
austriamicrosystems AG rendering of technical or other services.
Contact Information
Headquarters
austriamicrosystems AG
A-8141 Schloss Premstaetten, Austria
Tel: +43 (0) 3136 500 0
Fax: +43 (0) 3136 525 01
e-mail:
info@austriamicrosystems.com
For Sales Offices, Distributors and Representatives, please visit:
http://www.austriamicrosystems.com
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