AS1530, AS1531
12-Bit, Single-Supply, Low-Power, 400/300ksps
A/D Converters
austria
micro
systems
D a ta S h e e t
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Revision 0.96
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1 General Description
The AS1530/AS1531 are low-power, 4/8-channel, 400/
300ksps, 12-bit analog-to-digital (A/D) converters specif-
ically designed to operate with single-supply devices.
Superior AC characteristics, very low power consump-
tion, and highly-reliable packaging make these ultra-
small devices perfect for battery-powered remote-sen-
sor and data-acquisition devices.
The successive-approximation register (SAR), high-
speed sampling, high-bandwidth track/hold circuitry, and
multi-mode operation combine to make these devices
highly-flexible and configurable.
Both devices require low supply current (2.8mA @
400ksps, AS1530; 2.2mA @ 300ksps, AS1531) and fea-
ture a reduced-power mode and a power-down mode to
lower power consumption at slower throughput rates.
The devices operate from a single supply (+4.5 to +5.5V,
AS1530; +2.7 to +3.6V, AS1531). Both devices contain
an internal 2.5V reference, an integrated reference
buffer, and feature support for an external reference (1V
to V
DD
).
Data accesses are made via the high-speed, 4-wire,
SPI, QSPI-, and Microwire-compatible serial interface.
The devices are available in a 20-pin TSSOP package.
For lower-speed versions of these devices, contact aus-
triamicrosystems, AG regarding the AS1526/AS1527
A/D converters.
Figure 1. Block Diagram and Pin Assignments
2 Key Features
!
Single-Supply Operation:
- +4.5 to +5.5V (AS1530)
- +2.7 to +3.6V (AS1531)
!
Sampling Rate:
- 400ksps (AS1530)
- 300ksps (AS1531)
!
Software-Configurable Analog Input Types:
- 8-Channel Single-Ended
- 8-Channel Pseudo Differential Referenced to COM
- 4-Channel Pseudo Differential
- 4-Channel Fully Differential
!
Software-Configurable Input Range
!
Internal +2.5V Reference
!
Low-Current Operation:
- 2.8mA @ 400ksps (AS1530)
- 2.2mA @ 300ksps (AS1531)
- 0.4mA in Reduced-Power Mode
- 0.5A in Full Power-Down Mode
!
SPI/QSPI/Microwire/TMS320-Compatible
!
20-pin TSSOP Package
3 Applications
The devices are ideal for remote sensors, data-acquisi-
tion and data-logging devices, pen-digitizers, process
control, or any other space-limited A/D application with
low power-consumption requirements.
AS1530/
AS1531
Control
Logic
Output
Shift
Register
12-Bit
SAR
IN
OUT
REF
Analog
Input
+1.2V
REF
Input Shift
Register
Track/
Hold
17k
A
v
2.05
+2.50V
15
SSTRB
17
CSN
14
DOUT
20
V
DD1
19
V
DD2
13
GND
18
SCLK
16
DIN
1:8
CH0:CH7
9
COM
12
REFADJ
11
REF
10
V
DD3
AS1530/
AS1531
1
CH0
2
CH1
3
CH2
4
CH3
5
CH4
6
CH5
7
CH6
8
CH7
9
COM
10
V
DD3
20 V
DD1
19 V
DD2
18 SCLK
17 CSN
16 DIN
15 SSTRB
14 DOUT
13 GND
12 REFADJ
11 REF
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AS1530, AS1531
austria
micro
systems
Data Sheet
Contents
1 General Description ................................................................................................................................ 1
2 Key Features .......................................................................................................................................... 1
3 Applications ............................................................................................................................................ 1
4 Absolute Maximum Ratings .................................................................................................................... 3
5 Electrical Characteristics ........................................................................................................................ 4
AS1530 Electrical Characteristics .......................................................................................................................... 4
AS1531 Electrical Characteristics .......................................................................................................................... 6
Timing Characteristics ............................................................................................................................................ 8
6 Typical Operating Characteristics ......................................................................................................... 10
7 Pinout ................................................................................................................................................... 13
Pin Assignments ................................................................................................................................................... 13
Pin Descriptions ................................................................................................................................................... 13
8 Detailed Description ............................................................................................................................. 14
Analog Input ......................................................................................................................................................... 14
Input Protection ............................................................................................................................................. 14
Track/Hold ............................................................................................................................................................ 14
Control Register ................................................................................................................................................... 15
Analog Input Configuration ................................................................................................................................... 15
Channel Selection ................................................................................................................................................ 16
Single-Ended Input ........................................................................................................................................ 16
Differential Input ............................................................................................................................................ 16
Starting a Conversion ........................................................................................................................................... 17
Transfer Functions ................................................................................................................................................ 18
Power Modes ....................................................................................................................................................... 19
Reduced Power Mode ................................................................................................................................... 20
Full Power-Down Mode ................................................................................................................................. 20
Reference ............................................................................................................................................................. 21
Internal Reference ......................................................................................................................................... 21
External Reference ....................................................................................................................................... 22
9 Application Information ......................................................................................................................... 23
Initialization ........................................................................................................................................................... 23
Serial Interface ..................................................................................................................................................... 23
Serial Interface Configuration ........................................................................................................................ 23
QSPI Interface ............................................................................................................................................... 24
Quick Evaluation Circuit ....................................................................................................................................... 25
Layout Considerations .......................................................................................................................................... 26
10 Package Drawings and Markings ....................................................................................................... 27
11 Ordering Information ........................................................................................................................... 28
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AS1530, AS1531
austria
micro
systems
Data Sheet
4 Absolute Maximum Ratings
Stresses beyond those listed in
Table 1
may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in
Electrical Character-
istics on page 4
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 1. Absolute Maximum Ratings
Parameter
Min
Max
Units
Comments
V
DD1
, V
DD2
, V
DD3
to GND
-0.3
+7
V
V
DD1
to V
DD2
to V
DD3
-0.3
+0.3
V
CH0:CH7, COM to GND
-0.3
V
DD1
+
+0.3
V
REF, REFADJ to GND
-0.3
V
DD1
+
+0.3
V
DIN, SCLK, CSN, to GND
-0.3
V
DD2
+
+0.3
V
DOUT, SSTRB to GND
-0.3
V
DD2
+
+0.3
V
DOUT, SSTRB Sink Current
25
mA
Continuous Power Dissipation
(T
AMB
= +70C)
559
mW
Derate 7.0mW/C above +70C
Operating Temperature Range
-40
+85
C
Storage Temperature Range
-60
+150
C
Package Body Temperature
+260
C
The reflow peak soldering temperature (body
temperature) specified is in accordance with
IPC/JEDEC J-STD-020C "Moisture/Reflow
Sensitivity Classification for Non-Hermetic
Solid State Surface Mount Devices".
The lead finish for Pb-free leaded packages is
matte tin (100% Sn).
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AS1530, AS1531
austria
micro
systems
Data Sheet
5 Electrical Characteristics
AS1530 Electrical Characteristics
V
DD1
= V
DD2
= V
DD3
= +4.5 to +5.5V, COM = GND, f
SCLK
= 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle
(400ksps), external +2.5V at REF, REFADJ = V
DD1
, T
AMB
= T
MIN
to T
MAX
(unless otherwise specified). Typ values at
T
AMB
= +25C.
Table 2. AS1530 Electrical Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DC Accuracy
1
Resolution 12
Bits
INL
Relative Accuracy
2
-1
+1
LSB
DNL
Differential Nonlinearity
No missing codes over temperature
-1
+1
LSB
Offset Error
-6
+6
LSB
Gain Error
3
-6
+6
LSB
Gain-Error Temperature
Coefficient
1.6
ppm/
C
Channel-to-Channel
Offset Error Matching
0.2
LSB
Dynamic Specifications: 100kHz sinewave input, 2.5Vp-p, 400ksps, 6.4MHz clock, bit
RANGE (page 15)
= 0,
pseudo-differential input mode
SINAD
Signal-to-Noise plus
Distortion Ratio
70
dB
THD
Total Harmonic Distortion
Up to the 5th harmonic
-82
dB
SFDR
Spurious-Free
Dynamic Range
83
dB
IMD Intermodulation
Distortion
f
IN1
= 99kHz, f
IN2
= 102kHz
76
dB
Channel-to-Channel
Crosstalk
4
f
IN
= 200kHz, V
IN
= 2.5Vp-p
-85
dB
Full-Power Bandwidth
-3dB point
6
MHz
Full-Linear Bandwidth
SINAD > 68dB
450
kHz
Conversion Rate
t
CONV
Conversion Time
5
2.5
s
t
ACQ
Track/Hold
Acquisition
Time
390
ns
t
AD
Aperture Delay
7
ns
t
AJ
Aperture Jitter
<50
ps
f
SCLK
Serial
Clock
Frequency
0.5
6.4
MHz
Duty Cycle
40
60
%
Analog Inputs: CH0:CH7, COM
V
CHx
-
V
CHy
(COM)
Input Voltage Range: Single-
Ended, Pseudo-Differential,
and Differential
6
Bit
RANGE (page 15)
= 1
0
V
REF
V
Bit
RANGE (page 15)
= 0
-V
REF
/2
+V
REF
/2
Multiplexer Leakage Current On/off leakage current, V
CHx
= 0 or V
DD1
-1
0.001
+1 A
Input Capacitance
18
pF
Internal Reference
V
REF
REF Output Voltage
T
AMB
= +25C
2.48
2.50
2.52
V
REF Short-Circuit Current
30
mA
T
CVREF
REF Output Temperature
Coefficient
25
ppm/
C
Load Regulation
7
0 to 1mA output load
1.2
4.0
mV/
mA
C
BYPREF
Capacitive Bypass at REF
4.7
10
F
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AS1530, AS1531
austria
micro
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Data Sheet
C
BYPREF
ADJ
Capacitive Bypass at
REFADJ
0.01 10
F
REFADJ Output Voltage
1.22
V
REFADJ Input Range
For small adjustments, from 1.22V
100
mV
REFADJ Buffer Disable
Threshold
To power down the internal reference
1.4
V
DD1
-
1
V
Buffer Voltage Gain
2.045
V/V
External Reference: Reference buffer disabled, reference applied to pin REF
REF Input Voltage Range
8
1.0
V
DD1
+
50mV
V
REF Input Current
V
REF
= 2.50V,
f
SCLK
= 6.4MHz
200
350
A
V
REF
= 2.50V, f
SCLK
= 0
320
Power-Down, f
SCLK
= 0
5
Digital Inputs: DIN, SCLK, CSN
V
INH
Input
High
Voltage
0.7 x
V
DD
V
V
INL
Input
Low
Voltage
0.3 x
V
DD
V
V
HYST
Input
Hysteresis
0.2
V
I
IN
Input
Leakage
V
IN
= 0 or V
DD2
-1
+1
A
C
IN
Input
Capacitance
5
pF
Digital Outputs: DOUT, SSTRB
V
OL
Output
Voltage
Low
I
SINK
= 5mA
0.4
V
V
OH
Output Voltage High
I
SOURCE
= 1mA
4
V
I
L
Tri-State Leakage Current
CSN = V
DD2
-10
+10 A
C
OUT
Tri-State Output Capacitance
CSN = V
DD2
5
pF
Power Supply
V
DD1
,
V
DD2
,
V
DD3
Positive Supply Voltage
9
4.5 5.5
V
I
VDD1
,
I
VDD2
,
I
VDD3
Supply Current
V
DD1
= V
DD2
=
V
DD3
= 5.5V
Normal Operation with
External Reference
10
2.8
3.3
mA
Normal Operation with
Internal Reference
10
3.3
3.8
Reduced-Power Mode
11
0.4
0.8
Full Power-Down Mode
0.5
2
A
PSR Power-Supply
Rejection
V
DD1
= V
DD2
= V
DD3
= 5V 10%
-2
0.1
+2
mV
1. Tested at V
DD1
= V
DD2
= V
DD3
= +5V, COM = GND, bit
RANGE (page 15)
= 1, single-ended input mode.
2. Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error
and offset error have been nulled.
3. Offset nulled.
4. Ground on channel; sinewave applied to all off channels.
5. Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty
cycle.
6. The absolute voltage range for the analog inputs (CH0:CH7, and COM) is from GND to V
DD1
.
7. External load should not change during conversion for specified accuracy. Guaranteed specification of 4mV/mA
is a result of production test limitations.
8. AS1530/AS1531 performance is limited by the device noise floor, typically 300Vp-p.
Table 2. AS1530 Electrical Characteristics (Continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
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AS1530, AS1531
austria
micro
systems
Data Sheet
AS1531 Electrical Characteristics
V
DD1
= V
DD2
= V
DD3
= +2.7 to +3.6V, COM = GND, f
SCLK
= 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle
(300ksps), external +2.5V at REF, REFADJ = V
DD1
, T
AMB
= T
MIN
to T
MAX
(unless otherwise specified). Typ values at
T
AMB
= +25C.
9. Electrical characteristics are guaranteed from V
DD1(MIN)
= V
DD2(MIN)
= V
DD3(MIN)
to V
DD1(MAX)
= V
DD2(MAX)
=
V
DD3(MAX)
. For operations beyond this range, see
Typical Operating Characteristics on page 10
. For guaranteed
specifications beyond the limits, contact austriamicrosystems, AG.
10. AIN = mid-scale; bit
RANGE (page 15)
= 1; tested with 20pF on DOUT, 20pF on SSTRB, and f
SCLK
= 6.4MHz
@ GND to V
DD2
.
11. SCLK = DIN = GND, CSN = V
DD2
.
Table 3. AS1531 Electrical Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DC Accuracy
1
Resolution 12
Bits
INL
Relative Accuracy
2
-1
+1
LSB
DNL
Differential Nonlinearity
No missing codes over temperature
-1
+1
LSB
Offset Error
-6
+6
LSB
Gain Error
3
-6
+6
LSB
Gain-Error Temperature
Coefficient
1.6
ppm/
C
Channel-to-Channel Offset
Error Matching
0.2 LSB
Dynamic Specifications: 75kHz sinewave input, 2.5Vp-p, 300ksps, 4.8MHz clock, bit
RANGE (page 15)
= 0,
pseudo-differential input mode
SINAD
Signal-to-Noise plus
Distortion Ratio
70 dB
THD
Total Harmonic Distortion
Up to the 5th harmonic
-81
dB
SFDR
Spurious-Free Dynamic
Range
84 dB
IMD Intermodulation
Distortion
f
IN1
= 73kHz, f
IN2
= 77kHz
76
dB
Channel-to-Channel
Crosstalk
4
f
IN
= 150kHz, V
IN
= 2.5Vp-p
-80
dB
Full-Power Bandwidth
-3dB point
6
MHz
Full-Linear Bandwidth
SINAD > 68dB
350
kHz
Conversion Rate
t
CONV
Conversion Time
5
Normal operation
3.3
s
t
ACQ
Track/Hold Acquisition Time
Normal operation
520
ns
t
AD
Aperture Delay
7
ns
t
AJ
Aperture Jitter
<50
ps
f
SCLK
Serial Clock Frequency
Normal operation
0.5
4.8
MHz
Duty Cycle
40
60
%
Analog Inputs: CH0:CH7, COM
V
CHx
-
V
CHy
(COM)
Input Voltage Range: Single-
Ended, Pseudo-Differential,
and Differential
6
Bit
RANGE (page 15)
= 1
0
V
REF
V
Bit
RANGE (page 15)
= 0
-V
REF
/2
+V
REF
/2
Multiplexer Leakage Current On/off leakage current, V
CHx
= 0 or A
VDD
-1
0.001
+1 A
Input Capacitance
18
pF
Internal Reference
V
REF
REF Output Voltage
T
AMB
= +25C
2.48
2.50
2.52
V
REF Short-Circuit Current
30
mA
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AS1530, AS1531
austria
micro
systems
Data Sheet
T
CVREF
REF Output
Temperature Coefficient
25
ppm/
C
Load Regulation
7
0 to 0.75mA output load
0.6
2.0
mV/
mA
C
BYPREF
Capacitive Bypass at REF
4.7
10
F
C
BYPREF
ADJ
Capacitive Bypass
at REFADJ
0.01 10
F
REFADJ Output Voltage
1.22
V
REFADJ Input Range
For small adjustments, from 1.22V
100
mV
REFADJ Buffer
Disable Threshold
To power down the internal reference
1.4
V
DD1
- 1
V
Buffer Voltage Gain
2.045
V/V
External Reference: Reference buffer disabled, reference applied to REF
REF Input Voltage Range
8
1.0
V
DD1
+
50mV
V
REF Input Current
V
REF
= 2.50V, f
SCLK
= 4.8MHz
200
350
A
V
REF
= 2.50V, f
SCLK
= 0
320
In power-down, f
SCLK
= 0
5
Digital Inputs: DIN, SCLK, CSN
V
INH
Input
High
Voltage
0.7 x
V
DD
V
V
INL
Input
Low
Voltage
0.3 x
V
DD
V
V
HYST
Input
Hysteresis
0.8
V
I
IN
Input
Leakage
V
IN
= 0 or V
DD2
-1
+1
A
C
IN
Input
Capacitance
5
pF
Digital Outputs: DOUT, SSTRB
V
OL
Output Voltage Low
I
SINK
= 5mA
0.4
V
V
OH
Output Voltage High
I
SOURCE
= 0.5mA
V
DD2
-
0.5V
V
I
L
Tri-State Leakage Current
CSN = V
DD2
-10
+10 A
C
OUT
Tri-State Output
Capacitance
CSN = V
DD2
5
pF
Power Supply
V
DD1
,
V
DD2
,
V
DD3
Positive Supply Voltage
9
2.7 3.6
V
I
VDD1
,
I
VDD2
,
I
VDD3
Supply Current
V
DD1
= V
DD2
=
V
DD3
= 5.5V
Normal Operation
with External
Reference
10
2.2
2.7
Normal Operation
with Internal
Reference
10
2.7
3.2
mA
Reduced-Power
Mode
11
0.4
0.8
Full Power-Down
Mode
11
0.5 2 A
PSR Power-Supply
Rejection
V
DD1
= V
DD2
= V
DD3
= 2.7 to 3.6V,
Mid-Scale Input
-2
0.1
+2 mV
1. Tested at V
DD1
= V
DD2
= V
DD3
= +3V; COM = GND; bit
RANGE (page 15)
= 1, single-ended input mode.
Table 3. AS1531 Electrical Characteristics (Continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
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AS1530, AS1531
austria
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systems
Data Sheet
Timing Characteristics
2. Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error
and offset error have been nulled.
3. Offset nulled.
4. Ground on channel; sinewave applied to all off channels.
5. Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty
cycle.
6. The absolute voltage range for the analog inputs (CH0:CH7, and COM) is from GND to V
DD1
.
7. External load should not change during conversion for specified accuracy. Guaranteed specification of 2mV/mA
is a result of production test limitations.
8. AS1530/AS1531 performance is limited by the device noise floor, typically 300Vp-p.
9. Electrical characteristics are guaranteed from V
DD1(MIN)
= V
DD2(MIN)
= V
DD3(MIN)
to V
DD1(MAX)
= V
DD2(MAX)
=
V
DD3(MAX)
. For operations beyond this range, see
Typical Operating Characteristics on page 10
. For guaran-
teed specifications beyond the limits, contact austriamicrosystems, AG.
10. AIN = mid-scale; bit
RANGE (page 15)
= 1; tested with 20pF on DOUT, 20pF on SSTRB, and f
SCLK
= 4.8MHz
@ GND to V
DD2
.
11. SCLK = DIN = GND, CSN = V
DD2
.
Table 4. AS1530 Timing Characteristics (Figures
2
,
3
,
21
,
23
; V
DD1
= V
DD2
= V
DD3
= +4.5 to +5.5V; T
AMB
= T
MIN
to
T
MAX
(unless otherwise specified).
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
CP
SCLK
Period
156
ns
t
CH
SCLK Pulse Width High
62
ns
t
CL
SCLK Pulse Width Low
62
ns
t
DS
DIN to SCLK Setup
35
ns
t
DH
DIN to SCLK Hold
0
ns
t
CSS
CSN Fall to SCLK Rise Setup
35
ns
t
CS0
SCLK Rise to CSN Fall Ignore
35
ns
t
DOH
SCLK Rise to DOUT Hold
C
LOAD
= 20pF
10
20
ns
t
STH
SCLK Rise to SSTRB Hold
C
LOAD
= 20pF
10
20
ns
t
STV
SCLK Rise to DOUT Valid
C
LOAD
= 20pF
80
ns
t
DOV
SCLK Rise to SSTRB Valid
C
LOAD
= 20pF
80
ns
t
DOD
CSN Rise to DOUT Disable
C
LOAD
= 20pF
10
65
ns
t
STD
CSN Rise to SSTRB Disable
C
LOAD
= 20pF
10
65
ns
t
DOE
CSN Fall to DOUT Enable
C
LOAD
= 20pF
65
ns
t
STE
CSN Fall to SSTRB Enable
C
LOAD
= 20pF
65
ns
t
CSW
CSN Pulse Width High
100
ns
Table 5. AS1531 Timing Characteristics (Figures
2
,
3
,
21
,
23
; V
DD1
= V
DD2
= V
DD3
= +2.7 to +3.6V; T
AMB
= T
MIN
to
T
MAX
(unless otherwise specified).
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
CP
SCLK
Period
208
ns
t
CH
SCLK Pulse Width High
83
ns
t
CL
SCLK Pulse Width Low
83
ns
t
DS
DIN to SCLK Setup
45
ns
t
DH
DIN to SCLK Hold
0
ns
t
CSS
CSN Fall to SCLK Rise Setup
45
ns
t
CS0
SCLK Rise to CSN Fall ignore
45
ns
t
DOH
SCLK Rise to DOUT Hold
C
LOAD
= 20pF
13
20
ns
t
STH
SCLK Rise to SSTRB Hold
C
LOAD
= 20pF
13
20
ns
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AS1530, AS1531
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Data Sheet
Figure 2. DOUT Enable-Time Load Circuits
Figure 3. DOUT Disable-Time Load Circuits
t
DOV
SCLK Rise to DOUT Valid
C
LOAD
= 20pF
100
ns
t
STV
SCLK Rise to SSTRB Valid
C
LOAD
= 20pF
100
ns
t
DOD
CSN Rise to DOUT Disable
C
LOAD
= 20pF
13
85
ns
t
STD
CSN Rise to SSTRB Disable
C
LOAD
= 20pF
13
85
ns
t
DOE
CSN Fall to DOUT Enable
C
LOAD
= 20pF
85
ns
t
STE
CSN Fall to SSTRB Enable
C
LOAD
= 20pF
85
ns
t
CSW
CSN Pulse Width High
100
ns
Table 5. AS1531 Timing Characteristics (Figures
2
,
3
,
21
,
23
; V
DD1
= V
DD2
= V
DD3
= +2.7 to +3.6V; T
AMB
= T
MIN
to
T
MAX
(unless otherwise specified). (Continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
C
LOAD
20pF
C
LOAD
20pF
6k
GND
DGND
DOUT
DOUT
High-impedance to V
OH
and V
OL
to V
OH
V
DD2
High-impedance to V
OL
and V
OH
to V
OL
6k
DGND
6k
C
LOAD
20pF
C
LOAD
20pF
6k
DGND
GND
DGND
DOUT
DOUT
V
OH
to high-impedance
V
DD2
V
OL
to high-impedance
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AS1530, AS1531
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Data Sheet
6 Typical Operating Characteristics
Figure 4. INL vs. Digital Output Code
Figure 5. DNL vs. Digital Output Code
Figure 6. FFT @ 10kHz; RANGE = 1, MODE = 1
Figure 7. FFT @ 75kHz; RANGE = 0, MODE = 1
Figure 8. ENOB vs. V
REF
; 1st Order 300kHz
Figure 9. ENOB vs. Input Signal Frequency; 1st
Low Pass Filter
Order 300kHz Low Pass Filter
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Digital Output Code
INL (LSB)
e
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0
500 1000 1500 2000 2500 3000 3500 4000 4500
Digital Output Code
DNL (LSB)
e
-180
-160
-140
-120
-100
-80
-60
-40
-20
0
20
0
20
40
60
80 100 120 140 160
Input Signal Frequency (kHz)
FFT (d
BC)
e
-180
-160
-140
-120
-100
-80
-60
-40
-20
0
20
0
20
40
60
80 100 120 140 160
Input Signal Frequency (kHz)
FFT (d
BC)
e
10.7
10.8
10.9
11
11.1
11.2
11.3
11.4
11.5
11.6
1
1.4
1.8
2.2
2.6
3
Voltage (V)
ENOB (Bit)
11.05
11.1
11.15
11.2
11.25
11.3
11.35
11.4
11.45
0
50
100 150 200 250 300 350
Frequency (kHz)
ENOB (Bit)
e
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AS1530, AS1531
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Data Sheet
Figure 10. I
VDD
vs. V
DD
(Static)
Figure 11. I
VDD
vs. Temperature; Internal Reference
Figure 12. I
VDD
vs. V
DD
(Converting)
Figure 13. I
VDD
vs. Temperature (Static)
Figure 14. V
REF
vs. Temperature
Figure 15. Offset Error vs. V
DD
2.5
2.75
3
3.25
3.5
3.75
4
-40
-15
10
35
60
85
Temperature (C)
Supply Current (mA)
e
AS1530
AS1531
0
0.5
1
1.5
2
2.5
3
3.5
4
2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5
Supply Voltage (V)
Supply Current (mA)
e
Internal Reference
External Reference
0
0.5
1
1.5
2
-40
-15
10
35
60
85
Temperature (C)
Supply Current (mA
)
AS1530, Reduced Power Mode, Internal Ref.
AS1531, Reduced Power Mode, Internal Ref.
AS1530, Reduced Power Mode, External Ref.
AS1531, Reduced Power Mode, External Ref.
0
0.5
1
1.5
2
2.5
3
2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5
Supply Voltage (V)
Supply Current (mA)
e
Normal Operation; Internal Reference
Reduced Power Mode; Internal Reference
Reduced Power Mode; External Reference
2.49
2.495
2.5
2.505
2.51
-40
-15
10
35
60
85
Temperature (C)
Reference Voltage (V)
.
-1.8
-1.6
-1.4
-1.2
-1
2.7
3.4
4.1
4.8
5.5
Supply Voltage (V)
Offset Error (LSB)
.
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AS1530, AS1531
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Data Sheet
Figure 16. Offset Error vs. Temperature
Figure 17. Gain Error vs. V
DD
Figure 18. Gain Error vs. Temperature
-1.8
-1.6
-1.4
-1.2
-1
-40
-15
10
35
60
85
Temperature (C)
Offset Error (LSB)
.
-3
-2
-1
0
1
2
3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
V
DD
(V)
Gain Error (LSB)
e
0
1
2
3
4
5
-40
-15
10
35
60
85
Temperature (C)
Gain Error (LSB)
e
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AS1530, AS1531
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Data Sheet
7 Pinout
Pin Assignments
Figure 19. Pin Assignments (Top View)
Pin Descriptions
Table 6. Pin Descriptions
Pin Number
Pin Name
Description
1:8
CH0:CH7
Analog Sampling Inputs.
These eight pins serve as analog sampling inputs.
9
COM
Common Analog Inputs
. Tie this pin to ground in single-ended mode.
10
V
DD3
Positive Supply Voltage
11
REF
Reference-Buffer Output/A/DC Reference Input
. This pin serves as the reference
voltage for analog-to-digital conversions. In internal reference mode, the reference
buffer provides a +2.50V nominal output, externally adjustable at pin REFADJ. In
external reference mode, disable the internal buffer by pulling pin REFADJ to V
DD1
.
12
REFADJ
Reference-Buffer Amplifier Input
. To disable the reference-buffer amplifier, tie this
pin to V
DD1
.
13
GND
Analog and Digital Ground
14
DOUT
Serial Data Output
. Data is clocked out at the rising edge of pin SCLK. DOUT is high
impedance when CSN is high.
15
SSTRB
Serial Strobe Output
. SSTRB pulses high for one clock period before the MSB is
clocked out. SSTRB is high impedance when CSN is high.
16
DIN
Serial Data Input
. Data is clocked in at the rising edge of SCLK.
17
CSN
Active-Low Chip Select
. Data will not be clocked into pin DIN unless CSN is low.
When CSN is high, pins DOUT and SSTRB are high impedance.
18
SCLK
Serial Clock Input
. This pin clocks data into and out of the serial interface, and is used
to set the conversion speed.
Note:
The duty cycle must be between 40 and 60%.
19
V
DD2
Positive Supply Voltage
20
V
DD1
Positive Supply Voltage
AS1530/
AS1531
1
CH0
2
CH1
3
CH2
4
CH3
5
CH4
6
CH5
7
CH6
8
CH7
9
COM
10
V
DD3
20 V
DD1
19 V
DD2
18 SCLK
17 CSN
16 DIN
15 SSTRB
14 DOUT
13 GND
12 REFADJ
11 REF
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AS1530, AS1531
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Data Sheet
Analog Input
8 Detailed Description
Analog Input
The equivalent input circuit (
Figure 20
) shows the input architecture: track/hold circuitry, input multiplexer, input com-
parator, switched-capacitor DAC, and internal reference. A flexible serial interface provides easy connections to vari-
ous microprocessors.
Figure 20. Equivalent Input Circuit
The input tracking circuitry has a 6MHz small-signal bandwidth, thus it is possible to under-sample (digitize high-speed
transient events) and measure periodic signals modulated at frequencies exceeding the AS1530/AS1531 sampling
rate.
Note:
To avoid high-frequency signals being aliased into the frequency band of interest, antialias filtering is recom-
mended
Input Protection
Internal protection diodes (which clamp the analog input to V
DD1
and GND) allow the channel inputs to swing from
(GND to 0.3V) to (V
DD1
+ 0.3V) without damaging the devices. However, for accurate conversions near full scale, the
inputs must not exceed V
DD1
by more than 50mV or be lower than GND by 50mV.
Note:
If the analog input exceeds 50mV beyond the supply voltage, do not allow the input current to exceed 2mA.
Track/Hold
The track/hold stage enters tracking mode on the rising edge of SCLK which clocks in bit MODE of the 8-bit control
byte (see
Figure 21 on page 17
). The track/hold stage enters hold mode on the falling clock edge after bit PD0 of the 8-
bit control byte has been shifted in.
The time required for the track/hold circuit to acquire an input signal is a function of how quickly the input capacitance
is charged. If the input signal source impedance is high, the acquisition time lengthens. The acquisition time (t
ACQ
) is
the maximum time the device takes to acquire the signal and is also the minimum time needed for the signal to be
acquired.
t
ACQ
is never less than 390ns (AS1530) or 520ns (AS1531), and is calculated by:
tACQ = 9(RS + RIN)18pF (EQ 1)
(EQ 1)
Where:
:
R
IN
= 800
R
S
= the source impedance of the input signal.
Note:
Source impedances below 2k
do not significantly affect the AC performance of the devices.
+
+
Comparator
R
IN
C
SWITCH
11F
C
HOLD
13F
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
REF
AIN+
C
SWITCH
11F
+
C
HOLD
13F
Sample
Switch
C
SWITCH
includes all parasitics
Analog Input
Multiplexer
AIN-
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AS1530, AS1531
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Data Sheet
Control Register
Control Register
The control register on the AS1530/AS1531 is a 8-bit, write-only register. Data is written to this register using the CSN,
DIN and SCLK pins. The control register format is shown in
Table 7
and the function of the bits are defined in
Table 8
.
The AS1530/AS1531 operating modes are selected by sending an 8-bit data word to the internal shift register via pin
DIN. After pin CSN is pulled low, the first logic 1 on pin DIN is interpreted as a start bit. A start bit is defined as one of
the following:
!
The first logic 1 bit clocked into pin DIN (with CSN low) any time the AS1530/AS1531 is idle, e.g., after V
DD1
and
V
DD2
are applied.
!
The first logic 1 bit clocked into pin DIN after bit 6 of a conversion in progress is clocked out of pin DOUT.
Figure 22 on page 17
shows the serial-interface timing necessary to perform a conversion every 16 SCLK cycles. If
CSN is tied low and SCLK is continuous, guarantee a start bit by first clocking in sixteen 0s. The fastest speed at which
the devices can operate is 16 clocks per conversion (with CSN held low between conversions).
Analog Input Configuration
Table 7. Control Byte Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
START
(MSB)
SEL2 SEL1 SEL0
RANGE
MODE
PD1
PD0
(LSB)
Table 8. Bit Descriptions
Bit
Name
Description
7
START
The first logic 1 bit after CSN goes low signifies the start of a control byte.
6:4 SEL2:SEL0
These three bits select which of the eight channels and pin COM are used for
the conversion (see
Table 10
and
Table 11
).
3 RANGE
This bit selects the analog input range of the AS1530/AS1531.
0 = The analog input range extends from -V
REF
/2 to +V
REF
/2.
1= The analog input range extends from 0V to V
REF
.
2 MODE
This bit in conjunction with bit RANGE changes the analog input configuration.
0 = The voltage difference between two selectable channels is converted. This
setting selects two's complement coding (see
Table 10 on page 16
and
Table 11 on page 16
).
1 = One of the eight input channels is referenced to COM. This setting also
selects binary coding.
1:0
PD1:PD0
Selects the AS1530/AS1531 operating mode:
PD1
PD0 Mode
0
0
Full power-down mode.
0 1
Reduced-power
mode.
1 0
Reduced-power
mode.
1 1
Normal
operation.
Table 9. Analog Input Configuration
Analog Input Configuration
Mode Range
Coding
Comments
8-Channel Single-Ended
1
1
Binary
AIN+ from 0 to V
REF
.
COM should be tied to GND.
8-Channel Pseudo Differential
referenced to COM
1
1
Binary
AIN+ from COM to COM + V
REF
8-Channel Pseudo Differential
referenced to COM
1
0
Binary
AIN+ from -V
REF
/2+COM to + V
REF
/2+COM
4-Channel Pseudo Differential
0
1
Two's Complement
AIN+ - AIN- from 0 to V
REF
4-Channel Pseudo Differential
0
0
Two's Complement
AIN+ - AIN- from -V
REF
/2 to +V
REF
/2
4-Channel Fully Differential
0
0
Two's Complement
AIN+ - AIN- from -V
REF
/2 to +V
REF
/2,
fully differential input signal.
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AS1530, AS1531
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Data Sheet
Channel Selection
Channel Selection
Depending on the setting of bit
MODE (page 15)
, the internal inputs of the ADC (AIN+ and AIN-) are connected differ-
ently to the input channels (CH0:CH7 and COM).
Single-Ended Input
Note:
In single-ended mode pin COM should be connected to GND pin.
Differential Input
Table 10. Input Channel Selection for MODE = 1
SEL2
SEL1
SEL0
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
0 0 0
AIN+
AIN-
0 0 1
AIN+
AIN-
0 1 0
AIN+
AIN-
0 1 1
AIN+
AIN-
1 0 0
AIN+
AIN-
1 0 1
AIN+
AIN-
1 1 0
AIN+
AIN-
1 1 1
AIN+
AIN-
Table 11. Input Channel Selection for MODE = 0
SEL2
SEL1
SEL0
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
0 0 0
AIN+
AIN-
0 0 1
AIN+
AIN-
0 1 0
AIN+
AIN-
0 1 1
AIN+
AIN-
1 0 0
AIN-
AIN+
1 0 1
AIN-
AIN+
1 1 0
AIN-
AIN+
1 1 1
AIN-
AIN+
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AS1530, AS1531
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Data Sheet
Starting a Conversion
Starting a Conversion
A conversion is started by clocking a control byte into pin DIN.
With CSN low, each rising edge on SCLK clocks a bit from DIN into the internal shift register, starting with the MSB. A
conversion will only start when a logic 1 is written to the START bit of the 8-bit control register.
Figure 21. Single Conversion Timing Waveforms
Figure 22. Continuous 16-Clock Conversion Timing Waveforms
RANGE
B11 B10 B9
B8
B7
B0
B1
B2
B3
B4
B5
B6
t
ACQ
RB1
RB2
RB3
Single Conversion
Acquire
Idle
Idle
1
4
8
9
12
20
16
24
Start
High-Z
High-Z
High-Z
High-Z
CSN
SCLK
DIN
SSTRB
DOUT
SEL2 SEL1 SEL0
MODE
PD0
PD1
High-Z
CSN
DIN
SSTRB
SCLK
B11
B11
B0
B6
B6
B6
B0
...
Conversion Result 0
Conversion Result 1
Control Byte 0
Control Byte 1
Control Byte 2
High-Z
B11
1
12
8
16 1
12
8
16 1
12
8
16
S
S
S
S
DOUT
Conversion Result 2
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AS1530, AS1531
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Data Sheet
Transfer Functions
Figure 23. Detailed Serial Interface Timing Waveforms
The external serial clock shifts data in and out of the devices and drives the analog-to-digital conversion steps. Two
clock periods after the last bit of the control byte is written the output pin SSTRB pulses high for one clock period.
The serial data is shifted out at DOUT on each of the next 12 SCLK rising edges (see
Figure 21 on page 17
).
Pins SSTRB and DOUT go into a high-impedance state when CSN goes high. The conversion must complete in 120s
or less, or consequently, droop on the sample-and-hold capacitors may degrade conversion results.
Figure 23
shows
detailed serial-interface timing waveforms.
Transfer Functions
Output coding and transfer function depend on the control register bits
MODE (page 15)
and
RANGE (page 15)
.
Figure 24. Straight Binary Transfer Function for
Figure 25. Straight Binary Transfer Function for
RANGE = 1 and MODE = 1
RANGE = 0 and MODE = 1
t
DH
CSN
SCLK
DIN
SSTRB
DOUT
t
CSS
t
CP
t
CSW
t
CSO
t
CL
t
CH
t
DOH
t
DOV
t
DOD
t
STD
t
STH
t
DS
t
DOE
t
STE
t
STV
11...111
11...1110
11....101
00...011
00...010
00...001
00...000
Outpu
t
Code
0
1
2
3
Input Voltage AIN+ - AIN- (LSB)
FS - 3/2LSB
Full Scale (FS)
Transition
Full Scale = V
REF
Zero Scale = 0
1LSB = V
REF
/4096
11...111
11...1110
11....101
00...011
00...010
00...001
00...000
Outpu
t
Code
ZS ZS+1LSB
Input Voltage AIN+ - AIN- (LSB)
FS - 3/2LSB
Full Scale (FS)
Transition
Full Scale = +V
REF
/2
Zero Scale = -V
REF
/2
1LSB = V
REF
/4096
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AS1530, AS1531
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Data Sheet
Power Modes
Figure 26. Two's Complement Transfer Function for
Figure 27. Two's Complement Transfer Function for
RANGE = 1 and MODE = 0
RANGE = 0 and MODE = 0
Power Modes
Power consumption can be reduced by placing the AS1530/AS1531 in reduced power mode or in full power-down
mode between conversions.
The power mode is selected using bits PD1 and PD0 of the 8-bit control byte.
Table 12
lists the three operating modes with the corresponding supply current and active device circuits. For data
rates achievable in full power-down mode (see
Full Power-Down Mode on page 20
).
*
Circuit operation between conversions; during conversion all circuits are fully powered up.
The selected power-down mode (as shown in
Table 12
) is initiated after an analog-to-digital conversion is completed.
In all power modes the serial interface remains active, waiting for a new control byte to start conversion (see
Figure 30
on page 21
). Once the conversion is completed, the AS1530/AS1531 goes into the selected power mode until a new
control byte is shifted in. In reduced power mode the AS1530/AS1531 will be able to start conversion immediately
when running at decreased clock rates. In full power down mode wait until the internal reference has stabilized (depen-
dant on the values of the capacitance of REF and REFADJ).
During initialization the AS1530/AS1531 immediately go into normal operation mode and are ready to convert after 4s
when using an external reference. When using the internal reference, wait until the internal reference has stabilized
(dependant on the values of the capacitance of REF and REFADJ).
Table 12. Software Controlled Power Modes
PD1/PD0
(page 23)
Mode
Total Supply Current
Device Circuits
*
During Conversion
After Conversion
Input
Comparator
Reference
AS1530
AS1531
AS1530
AS1531
00
Full Power-Down Mode
2.8mA
2.2mA
0.5A
0.5A
Off
Off
01
Reduced-Power Mode
2.8mA
2.2mA
0.4mA
0.4mA
Reduced
Power
On
10
11 Normal
Operation
2.8mA
2.2mA
2.0mA
1.8mA
Full
Power
On
011....111
011...110
000...010
000...001
000...000
111...111
111...110
111...101
100...001
100...000
Outpu
t
Code
-FS
ZS
Input Voltage AIN+ - AIN- (LSB)
+FS - 1LSB
Full Scale = V
REF
-Full Scale = 0
Zero Scale = V
REF
/2
1LSB = V
REF
/4096
011....111
011...110
000...010
000...001
000...000
111...111
111...110
111...101
100...001
100...000
Outpu
t
Code
-FS
ZS
Input Voltage AIN+ - AIN- (LSB)
+FS - 1LSB
Full Scale = +V
REF
/2
-Full Scale = -V
REF
/2
Zero Scale = 0
1LSB = V
REF
/4096
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AS1530, AS1531
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Data Sheet
Power Modes
Reduced Power Mode
Reduced power mode is activated using bits PD1 and PD0
(see Table 12)
. When reduced power mode is asserted, the
AS1530/AS1531 completes any conversion in progress and enters reduced power mode.
The next start of conversion puts the AS1530/AS1531 into normal operation mode. The 8-bit control byte shifted into
the control register determines the next power mode. For example, if the 8-bit control byte contains PD1 = 0 and PD0
= 1, reduced power down mode starts immediately after the conversion (see
Figure 28
)
.
The reduced-power mode achieves the lowest power consumption at speeds close to the maximum sample rate.
Figure 29
shows the AS1531 power consumption in reduced-power mode and normal operating mode
(see Table 12
on page 19)
with the internal reference and maximum clock speed.
Figure 28. Reduced-Power Mode Timing Waveforms (AS1531)
Note:
The clock speed in reduced-power mode should be limited to 4.8MHz. Full power-down mode may provide
increased power savings in applications where the devices are inactive for long periods of time, where intermit-
tent bursts of high-speed conversions are required.
Figure 29. Normal Operation and Reduced Power Down using Internal Reference (AS1531)
Full Power-Down Mode
Full power-down is activated using bits PD1 and PD0
(see Table 12)
. Full power-down mode offers the lowest power
consumption at up to 1000 conversions per-channel per-second. When full power-down is asserted, the AS1530/
AS1531 completes any conversion in progress and powers down into specified low-quiescent current state.
The start of the next conversion puts the AS1530/AS1531 into normal operation mode. The 8-bit control byte shifted
into the control register determines the next power mode. For example, if the 8-bit control byte contains PD1 = 0 and
PD0 = 0, full power-down mode starts immediately after the conversion (see
Figure 30 on page 21
)
DIN
1
V
DD1
+V
DD2
+V
DD3
1
1
1
1
1
0
0
0
Reduced-
Power
Reduced-
Power
Reduced-
Power
2.50V (Always On)
2.2mA
2.2mA
2.2mA
0.4mA
0.4mA
0.4mA
REF
Normal Mode
Conversion
Reduced
Power Down
Normal Mode
Conversion
Reduced
Power Down
Normal Mode
Conversion
Reduced
Power Down
0
500
1000
1500
2000
2500
3000
0.001
0.1
10
1000
Sampling Rate (ksps)
Supply Current
(A)
.
Reduced Power Mode
Normal Operation
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Data Sheet
Reference
A 0.01F bypass capacitor plus the internal 17k
reference resistor at REFADJ form an R/C filter with a 200s time
constant. To achieve full 12-bit accuracy, 10 time constants (2ms) are required after power-up if the bypass capacitor is
fully discharged between conversions. Waiting this 2ms in reduced-power mode instead of normal operation mode can
further reduce power consumption. This is achieved by using the sequence shown in
Figure 30 on page 21
.
Figure 31 on page 21
shows the AS1531 power consumption for conversions using full power-down mode (PD1 = PD0
= 0
(see Table 12)
, an external reference, and the maximum clock speed. One dummy conversion to power-up the
device is required, but no wait-time is necessary to start the second conversion, thereby achieving lower power con-
sumption up to the full sampling rate.
Figure 30. Full Power-Down Timing Waveforms (AS1531)
Figure 31. Average Supply Current vs. Sampling Rate (AS1531, FULLPD, and External Reference)
Reference
The AS1530/AS1531 can operate with the internal or an external reference.
Internal Reference
The internal reference is selected by placing a capacitor between REFADJ and GND. The internally trimmed 1.22V
bandgap voltage available at REFADJ is buffered with a gain of 2.045V/V to pin REF, where 2.5V are available. A
decoupling capacitor is needed at pin REF.
DIN
1
0
1
1
1
0
0
0
0
Full Power-
Down
Reduced-
Power
REF
1
REFADJ
I
VDD1
+I
VDD2
+I
VDD3
Full Power-
Down
1.22V
2.5V
2.2mA
2.2mA
2.2mA
2.5V
1.22V
0mA
0mA
0.4mA
= R/C = 17
k x 0.01F
Full Power-
Down
Normal Mode
Conversion
Normal Mode
Dummy
Conversion
Reduced
Power Down
Normal Mode
Conversion
Full Power-
Down
1 Channel
0.1
100
100000
0.001
0.01
0.1
1
10
100
Sampling Rate (ksps)
Supply Current
(A)
.
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AS1530, AS1531
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Data Sheet
Reference
Additionally the bandgap voltage can be adjusted about 100mV by forcing a voltage to the REFADJ pin. The REFADJ
input impedance is typically 17k
.
Figure 32
shows a possible arrangement.
Figure 32. Reference Adjust Circuit
External Reference
An external reference can be connected directly at pin REF. To use the external reference, the internal buffer must be
disabled by connecting pin REFADJ to pin VDD. The input resistance is typically 15k
.
During conversion, an external reference at pin REF must deliver up to 350A DC load current and have 10
or less
output impedance. If the reference has a higher output impedance or is noisy, bypass it with a 4.7F capacitor placed
as close to pin REF as possible.
Note:
Using the REFADJ input makes buffering the external reference unnecessary.
C
LOAD
0.01F
GND
100k
DGND
24k
510k
+3.3V
12
REFADJ
AS1530/
AS1531
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Data Sheet
Initialization
9 Application Information
Initialization
When power is first applied to the AS1530/AS1531 internal power-on reset circuitry sets the devices for normal opera-
tion. At this point, the devices can perform data conversions with CSN held low.
Note:
The device requires 10s after the power supplies stabilize; no conversions should be initiated during this time.
The digital output at pin DOUT will be all 0s until an analog-to-digital conversion is initiated.
Serial Interface
The AS1530/AS1531 fully support SPI, QSPI, and Microwire interfaces. For SPI, select the correct clock polarity and
sampling edge in the SPI control registers (set CPOL = 0 and CPHA = 0).
Note:
Microwire, SPI, and QSPI all transmit a byte and receive a byte at the same time.
Using the circuit shown in
Figure 33 on page 24
, the simplest software interface requires only three 8-bit transfers to
perform a conversion (one 8-bit transfer to configure the AS1530/AS1531, and two more 8-bit transfers to clock out the
12-bit conversion result).
Serial Interface Configuration
The following steps describe how to configure the serial interface:
1. Confirm that the CPU serial interface is in master mode (so the CPU generates the serial clock).
2. Choose a clock frequency from 500kHz to 6.4MHz (AS1530) or 4.8MHz (AS1531).
3. Set up the control byte and call it TB1. TB1 should be in the format 1XXXXXXX binary, where the Xs indicate the
selected channel, conversion mode, and power mode.
4. Use a general-purpose I/O line on the CPU to pull CSN low.
5. Transmit TB1 and simultaneously receive a byte (RB1). Ignore this byte.
6. Transmit a byte of all zeros ($00
h
) and simultaneously receive byte RB2.
7. Transmit a byte of all zeros ($00
h
) and simultaneously receive byte RB3.
8. Pull CSN high.
Bytes RB2 and RB3 (see
Figure 21
) contain the results of the conversion, padded with three leading zeros and one
trailing zero. The total conversion time is a function of the serial-clock frequency and the amount of idle time between
8-bit transfers. To avoid excessive track/hold droop, make sure the total conversion time does not exceed 120s.
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Data Sheet
Serial Interface
Figure 33. Operational Diagram
QSPI Interface
The AS1530/AS1531 can interface with QSPI using the circuit in
Figure 34
(f
SCLK
= 4.0MHz, CPOL = 0, CPHA = 0).
This QSPI circuit can be programmed to do a conversion on each of the eight channels. The result is stored in memory
without affecting CPU performance, since QSPI incorporates a micro-sequencer.
Figure 34. QSPI Interface Connections
+2.5V
Analog
Inputs
0.1F
12
REFADJ
20
V
DD1
4.7F
1
CH0
19
V
DD2
13
GND
17
CSN
14
DOUT
15
SSTRB
CPU
V
DD
I/O
18
SCLK
16
DIN
SCK (SK)
MOSI (SO)
MISO (SI)
V
SS
0.1F
+3 to +5V
11
REF
AS1530/
AS1531
10
V
DD3
.
.
.
8
CH7
9
COM
10F
+2.5V
Analog
Inputs
0.1F
12
REFADJ
11
REF
4.7F
1
CH0
8
CH7
13
GND
14
DOUT
15
SSTRB
CPU
PCSO
SCK
MOSI
MISO
GND
0.1F
17
CSN
16
DIN
18
SCLK
+
10F
Power
Supplies
+3 or
+5V
+3 or
+5V
AS1530/
AS1531
20
V
DD1
19
V
DD2
10
V
DD3
.
.
.
9
COM
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Data Sheet
Quick Evaluation Circuit
Quick Evaluation Circuit
In order to quickly evaluate the analog performance of the AS1530/AS1531, use the circuit shown in
Figure 35
.
Figure 35. Evaluation Circuit Diagram
Connecting DIN to V
DD2
shifts in control bytes of $FF
h
, which trigger single-ended conversions (bit
RANGE (page 15)
= 1) on CH7 without powering down between conversions. The SSTRB output pulses high for one clock period before
the MSB of the 12-bit conversion result is shifted out of DOUT. Varying the analog input to CH7 will alter the sequence
of bits from DOUT. A total of 16 clock cycles is required per conversion.
Note:
All SSTRB and DOUT output transitions occur 25ns (typ) after the rising edge of SCLK.
+2.5V
Analog
Input
0.1F
12
REFADJ
11
REF
4.7F
13
GND
17
CSN
14
DOUT
15
SSTRB
18
SCLK
16
DIN
0.1F
To
V
DD2
0.1F
10F
+3 or
+5V
External
Clock
8
CH7
AS1530/
AS1531
TBA
20
V
DD1
19
V
DD2
10
V
DD3
9
COM
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Data Sheet
Layout Considerations
Layout Considerations
The AS1530/AS1531 require proper layout and design procedures for optimum performance.
!
Use printed circuit boards; wirewrap boards should not be used.
!
Analog and digital traces should be separate and should not run parallel to each other (especially clock traces).
!
Digital traces should not run beneath the AS1530/AS1531.
!
Use a single-point analog ground at GND, separate from the digital ground (see
Figure 36
). Connect all other ana-
log grounds and DGND to this star ground point for further noise reduction. No other digital system ground should
be connected to this single-point analog ground. The ground return to the power supply for this ground should be
low impedance and as short as possible for noise-free operation.
!
High-frequency noise in the V
DD
power supply may affect the AS1530/AS1531 high-speed comparator. Bypass
this supply to the single-point analog ground with 0.1F and 4.7F bypass capacitors. Bypass capacitors should
be as close to the device as possible for optimum power supply noise-rejection. If the power supply is very noisy, a
10
resistor can be connected as a low-pass filter to attenuate supply noise (see
Figure 36
).
Figure 36. Recommended GND Design
Power
Supplies
Digital
Circuitry
+
+
10
(Optional)
9
COM
V
DD1
GND
GND
V
DD2
DGND
V
DD
19
V
DD2
13
GND
20
V
DD1
AS1530/
AS1531
10
V
DD3
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Data Sheet
10 Package Drawings and Markings
Figure 37. 20-pin TSSOP Package
Symbol
Min
Typ
Max
Notes
A
-
-
1.10
1,2
A1
0.05
-
0.15
1,2
A2
0.85
0.90
0.95
1,2
L
0.50
0.60
0.75
1,2
R
0.09
-
-
1,2
R1
0.09
-
-
1,2
b
0.19
-
0.30
1,2,5
b1
0.19
0.22
0.25
1,2
c
0.09
-
0.20
1,2
c1
0.09
-
0.16
1,2
1
0
-
8
1,2
L1
1.0REF
1,2
aaa
0.10
1,2
bbb
0.10
1,2
ccc
0.05
1,2
ddd
0.20
1,2
e
0.65BSC
1,2
2
12REF
1,2
3
12REF
1,2
Variations
D
6.40
6.50
6.60
1,2,3,8
E1
4.30
4.40
4.50
1,2,4,8
E
6.4BSC
1,2
e
0.65BSC
1,2
N
20
1,2,6
Notes:
1. All dimensions are in millimeters; angles in degrees.
2. Dimensioning and tolerancing per ASME Y14.5M 1994.
3. Dimension D does not include mold flash, protrusions, or gate
burrs. Mold flash, protrusions, and gate burrs shall not exceed
0.15mm per side.
4. Dimension E1 does not include interlead flash or protrusion.
Interlead flash or protrusions shall not exceed 0.25mm per
side.
5. Dimension b does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm total in excess of the b
dimension at maximum material condition. Dambar cannot be
located on the lower radius of the foot.
6. Terminal numbers are for reference only.
7. Datums A and B to be determined at datum plane H.
8. Dimensions D and E1 are to be determined at datum plane H.
9. This dimension applies only to variations with an even number
of leads per side.
10. Cross section A-A to be determined at 0.10 to 0.25mm from
the leadtip.
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Data Sheet
11 Ordering Information
The devices are available as the standard products shown in
Table 13
.
Table 13. Ordering Information
Model
Description
Delivery Form
Package
AS1530-T
12-bit ADC, 8-channel, 400ksps
Tape and Reel
20-pin TSSOP
AS1530
12-bit ADC, 8-channel, 400ksps
Tubes
20-pin TSSOP
AS1531-T
12-bit ADC, 8-channel, 300ksps
Tape and Reel
20-pin TSSOP
AS1531
12-bit ADC, 8-channel, 300ksps
Tubes
20-pin TSSOP
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Data Sheet
Copyrights
Copyright 1997-2006, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe.
Trademarks Registered . All rights reserved. The material herein may not be reproduced, adapted, merged, trans-
lated, stored, or used without the prior written consent of the copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing
in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding
the information set forth herein or regarding the freedom of the described devices from patent infringement. austriami-
crosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior
to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information.
This product is intended for use in normal commercial applications. Applications requiring extended temperature
range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-
sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for
each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard
production flow, such as test flow or test location.
The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However,
austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to
personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or
consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the tech-
nical data herein. No obligation or liability to recipient or any third party shall arise or flow out of
austriamicrosystems AG rendering of technical or other services.
Contact Information
Headquarters
austriamicrosystems AG
A-8141 Schloss Premstaetten, Austria
Tel: +43 (0) 3136 500 0
Fax: +43 (0) 3136 525 01
e-mail:
info@austriamicrosystems.com
For Sales Offices, Distributors and Representatives, please visit:
http://www.austriamicrosystems.com
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