12/2003
ACD2203
CATV/TV/Video Downconverter
with Dual Synthesizer
PRELIMINARY DATA SHEET - Rev 1.3
Figure 1: Downconverter Block Diagram
FEATURES
Integrated Downconverter
Integrated Dual Synthesizer
256 QAM Compatibility
Single +5 V Power Supply Operation
Low Power Consumption: <0.6 W
Low Noise Figure: 8 dB
High Conversion Gain: 10 dB
Low Distortion: -53 dBc
Two-Wire Interface
Small Size
-40 C to +85 C
APPLICATIONS
Set Top Boxes
CATV Video Tuners
Digital TV Tuners
CATV Data Tuners
Cable Modems
S8 Package
28 Pin SSOP
PRODUCT DESCRIPTION
The ACD2203 uses both GaAs and Si technology
to provide the downconverter and dual synthesizer
functions in a double conversion tuner gain block,
local oscillator, balanced mixer and dual synthesizer.
The specifications meet the requirements of
CATV/TV/Video and Cable Modem Data applications.
The ACD2203 is supplied in a 28 lead SSOP
package and requires a single +5 V supply voltage.
The IC is well suited for applications where small
size, low cost, low auxiliary parts count and a no-
compromise performance is important. It provides
for cost reduction by lowering the component and
packaged IC count and decreasing the amount of
labor-intensive production alignment steps, while
significantly improving performance and reliability.
Figure 2: Dual Synthesizer Block Diagram
RF2: 64/65
Prescaler
18 Bit RF2
N Counter
RF2
Phase
Detector
RF2
Charge
Pump
RF1
Phase
Detector
RF1
Charge
Pump
15 Bit RF2
R Counter
15 Bit RF1
R Counter
18 Bit RF1
N Counter
RF1: 64/65
Prescaler
Oscillator
24 Bit
Data Register
CP
U
CP
D
RF
D
REF
IN
REF
OUT
RF
U
Clock
Data
AS
2 Bit
A/D
V
IF
+
IF
OUT+
OSC
OUT
T
CKT
RF
IN
+
Phase Splitter
Low Noise
VGA
Mixer
RF
IN
-
V
IF
+
IF
OUT-
2
PRELIMINARY DATA SHEET - Rev 1.3
12/2003
ACD2203
Figure 3: Pinout
PRELIMINARY DATA SHEET - Rev 1.3
12/2003
3
ACD2203
Table 1: Pin Description
N
I
P
E
M
A
N
N
O
I
T
P
I
R
C
S
E
D
N
I
P
E
M
A
N
N
O
I
T
P
I
R
C
S
E
D
1
F
R
+
N
I
r
e
t
r
e
v
n
o
c
n
w
o
D
t
u
p
n
I
F
R
l
a
it
n
e
r
e
ff
i
D
8
2
V
F
I
F
I
+
+
T
U
O
r
e
t
r
e
v
n
o
c
n
w
o
D
t
u
p
t
u
O
F
I
l
a
it
n
e
r
e
ff
i
D
o
t
d
e
l
p
u
o
c
y
l
e
v
it
c
u
d
n
I
V
+
D
D
2
F
R
-
N
I
r
e
t
r
e
v
n
o
c
n
w
o
D
t
u
p
n
I
F
R
l
a
it
n
e
r
e
ff
i
D
7
2
V
F
I
F
I
+
T
U
O
-
r
e
t
r
e
v
n
o
c
n
w
o
D
t
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p
t
u
O
F
I
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it
n
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r
e
ff
i
D
o
t
d
e
l
p
u
o
c
y
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v
it
c
u
d
n
I
V
+
D
D
3
D
N
G
d
n
u
o
r
G
r
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v
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n
w
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D
)
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c
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c
e
b
t
s
u
M
(
6
2
D
N
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d
n
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r
G
r
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v
n
o
c
n
w
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D
)
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(
4
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5
2
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+
(
y
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p
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p
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D
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)
5
T
T
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a
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it
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ti
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c
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k
n
a
T
(
4
2
C
S
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ll
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n
n
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C
(
)
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p
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F
R
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t
n
y
S
6
C
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ti
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k
n
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T
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)
d
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3
2
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(
7
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6
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2
2
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9
1
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1
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8
1
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1
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3
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h
t
n
y
S
V
+
(
D
D
)
4
PRELIMINARY DATA SHEET - Rev 1.3
12/2003
ACD2203
ELECTRICAL CHARACTERISTICS
Table 2: Absolute Minimum and Maximum Ratings
Stresses in excess of the absolute ratings may cause permanent damage.
Functional operation is not implied under these conditions. Exposure to absolute
ratings for extended periods of time may adversely affect reliability.
The device may be operated safely over these conditions; however, parametric
performance is guaranteed only over the conditions defined in the electrical
specifications.
Table 3: Operating Ranges
Notes:
(1) Mixer operation is possible beyond these frequencies with slightly reduced
performance.
(2) Case Temperature is 15 C higher than Ambient Temperature, when Ambient
Temperature is +25 C, using the PC Board Layout shown in Figures 24-26.
R
E
T
E
M
A
R
A
P
N
I
M
X
A
M
T
I
N
U
)
8
2
&
7
2
,
5
2
s
n
i
p
(
e
g
a
tl
o
V
y
l
p
p
u
S
)
5
1
n
i
p
(
-
-
9
+
5
.
6
+
C
D
V
6
1
,
4
1
h
g
u
o
r
h
t
0
1
s
n
i
p
n
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g
a
tl
o
V
V
h
ti
w
9
1
h
g
u
o
r
h
t
S
S
V
0
=
3
.
0
-
V
N
Y
S
3
.
0
+
C
D
V
)
5
&
2
,
1
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(
s
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a
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t
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p
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I
-
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D
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)
2
&
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s
n
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p
(
r
e
w
o
P
t
u
p
n
I
)
5
n
i
p
(
)
9
1
&
6
1
,
3
1
s
n
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p
(
-
-
-
0
1
+
7
1
+
0
2
+
m
B
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t
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r
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p
m
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5
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1
+
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g
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4
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W
/
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(
)
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(
t
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p
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)
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I
(
t
u
p
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(
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a
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0
0
9
5
3
5
6
8
-
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1
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5
1
0
5
3
1
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M
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t
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D
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(
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N
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h
P
0
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2
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4
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2
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1
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M
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:
e
g
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y
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)
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2
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2
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2
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1
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n
i
p
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C
D
V
T
:
e
r
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t
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it
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b
m
A
A
)
2
(
0
4
-
-
5
8
+
C
PRELIMINARY DATA SHEET - Rev 1.3
12/2003
5
ACD2203
Table 4: Electrical Specifications - Downconverter Section
(T
A
= +25
C
(7)
, V
DD
= +5 VDC, RF
IN
= 1087 MHz, IF
OUT
= 45 MHz)
Notes:
(1) As measured in ANADIGICS test fixture with single-ended RF input.
(2) As measured in ANADIGICS test fixture with differential RF inputs.
(3) SSB noise figure will be approximately 3 dB higher with single-ended RF input.
(4) Two tones: 1085 and 1091 MHz, -20 dBm each, 1091 MHz tone AM-modulated
99% at 15 kHz.
(5) Two tones: 1085 and 1091 MHz, -15 dBm each.
(6) R1 = 10 Ohms.
(7) Case Temperature is 15 C higher than Ambient Temperature, when Ambient
Temperature is +25 C, using the PC Board Layout shown in Figures 24-26.
R
E
T
E
M
A
R
A
P
N
I
M
P
Y
T
X
A
M
T
I
N
U
n
i
a
G
n
o
i
s
r
e
v
n
o
C
)
1
(
n
i
a
G
n
o
i
s
r
e
v
n
o
C
)
2
(
8
1
1
0
1
3
1
4
1
7
1
B
d
e
r
u
g
i
F
e
s
i
o
N
B
S
S
)
3
(
,
)
2
(
-
4
7
B
d
n
o
it
a
l
u
d
o
M
s
s
o
r
C
)
6
(
,
)
4
(
,
)
2
(
-
6
5
-
3
5
-
c
B
d
3
d
r
n
o
it
r
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t
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D
n
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it
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r
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)
3
D
M
I
(
)
6
(
,
)
5
(
,
)
2
(
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3
5
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c
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d
3
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n
o
T
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2
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t
p
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t
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I
t
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d
r
O
)
3
P
II
(
)
6
(
,
)
5
(
,
)
2
(
2
1
+
-
-
m
B
d
)
t
e
s
ff
O
z
H
K
0
1
@
(
e
s
i
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s
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h
P
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L
)
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,
)
1
(
-
0
9
-
5
.
5
8
-
z
H
/
c
B
d
)
4
2
n
i
p
(
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e
w
o
P
t
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p
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m
B
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B
d
c
B
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2
n
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t
n
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p
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F
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(
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(
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1
(
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5
5
6
A
m
t
n
e
r
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p
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a
h
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/
c
s
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5
2
n
i
p
(
-
0
3
5
4
A
m
n
o
it
p
m
u
s
n
o
C
r
e
w
o
P
-
0
0
4
0
5
5
W
m
6
PRELIMINARY DATA SHEET - Rev 1.3
12/2003
ACD2203
Table 5: Electrical Specifications - Synthesizer Section
(T
A
= +25
C
(4)
, V
DD
= +5 VDC)
Notes:
(1) Measured at 250 kHz comparison frequency.
(2) Measured at 62.5 kHz comparison frequency.
(3) CP
U
and CP
D
= V
CC
/2.
(4) Case Temperature is 15 C higher than Ambient Temperature, when Ambient Temperature is +25 C, using the
PC Board Layout shown in Figures 24-26.
R
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T
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m
PRELIMINARY DATA SHEET - Rev 1.3
12/2003
7
ACD2203
Figure 4: Serial 2-Wire Data Input Timing
Table 6: Digital 2-Wire Interface Specifications
(T
A
= +25
C, V
DD
= +5 VDC, ref. Figure 4)
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DATA
CLK
t
F
t
LOW
t
R
S
t
HD;STA
t
HD;DAT
t
SU;DAT
t
HIGH
t
F
t
SU;STA
Sr
S
P
t
HD;STA
t
SP
t
R
t
BUF
t
SU;STO
Notes:
(1) C
b
is the total capacitance of one bus line in pF.
(2) For maximum 0.8 V level during Acknowledge Pulse.
3. All timing values are referred to minimum V
H
and maximum V
L
levels.
8
PRELIMINARY DATA SHEET - Rev 1.3
12/2003
ACD2203
Figure 10: Typical Local Oscillator Output Power
vs. Ambient Temperature
(V = +5 V, f
= 1042 MHz)
DD
LO2
-7.0
-6.5
-6.0
-5.5
-5.0
-4.5
25
35
45
55
65
75
85
Ambient Temperature (C)
Output
Power
(
dBm)
Figure 8: Typical Phase Noise at 10 kHz Offset
vs. Ambient Temperature
(V = +5 V, f
= 1042 MHz)
DD
LO2
-94
-92
-90
-88
-86
-84
25
35
45
55
65
75
85
Ambient Temperature (C)
Phase
Noise
(
dBc/Hz)
Figure 6: Typical Conversion Gain and Noise
Figure vs. Ambient Temperature
(V = +5 V, f
= 1042 MHz)
DD
LO2
10.0
11.0
12.0
13.0
14.0
15.0
25
35
45
55
65
75
85
Ambient Temperature (C)
Conversion
Gain
(dB)
3.0
3.4
3.8
4.2
4.6
5.0
Noise
F
igure
(
dB)
Conversion Gain
Noise Figure
PERFORMANCE DATA
13.0
13.2
13.4
13.6
13.8
14.0
4.7
4.8
4.9
5.0
5.1
5.2
5.3
Supply Voltage (V)
Conversion
Gain
(dB)
3.55
3.57
3.59
3.61
3.63
3.65
Noise
F
igure
(
dB)
Conversion Gain
Noise Figure
Figure 5: Typical Conversion Gain and Noise
Figure vs. Supply Voltage
(T = +25 C, f
= 1042 MHz)
A
LO2
Figure 7: Typical Phase Noise at 10 kHz Offset
vs. Supply Voltage
(T = +25 C, f
= 1042 MHz)
A
LO2
-95
-94
-93
-92
-91
-90
4.7
4.8
4.9
5.0
5.1
5.2
5.3
Supply Voltage (V)
Phase
Noise
(
dBc/Hz)
Figure 9: Typical Local Oscillator Output Power
vs. Supply Voltage
(T = +25 C, f
= 1042 MHz)
A
LO2
-7.0
-6.5
-6.0
-5.5
-5.0
-4.5
4.7
4.8
4.9
5.0
5.1
5.2
5.3
Supply Voltage (V)
Output
Power
(
dBm)
PRELIMINARY DATA SHEET - Rev 1.3
12/2003
9
ACD2203
Figure 11: Typical Upconverter Prescaler
Sensitivity vs. Local Oscillator Frequency
(T = +25 C, V = +5 V)
A
DD
-35
-30
-25
-20
-15
-10
-5
500
700
900
1100
1300
1500
1700
1900
2100
LO1 Frequency (MHz)
Prescalar
Sensitivity
(
dBm)
Figure 13: Typical Upconverter Prescaler
Sensitivity vs. Supply Voltage
(T = +25 C, f
= 2100 MHz)
A
LO1
-9.0
-8.5
-8.0
-7.5
-7.0
4.7
4.8
4.9
5.0
5.1
5.2
5.3
Supply Voltage (V)
Prescalar
Sensitivity
(
dBm)
Figure 15: Typical Upconverter Prescaler
Sensitivity vs. Ambient Temperature
(V = +5 V, f
= 2100 MHz)
DD
LO1
-8.5
-8.0
-7.5
-7.0
-6.5
-6.0
25
35
45
55
65
75
85
Ambient Temperature (C)
Prescalar
Sensitivity
(
dBm)
Figure 12: Typical Downconverter Prescaler
Sensitivity vs. Local Oscillator Frequency
(T = +25 C, V = +5 V)
A
DD
-24
-22
-20
-18
-16
-14
-12
400
600
800
1000
1200
1400
LO2 Frequency (MHz)
Prescalar
Sensitivity
(
dBm)
Figure 14: Typical Downconverter Prescaler
Sensitivity vs. Supply Voltage
(T = +25 C, f
= 1000 MHz)
A
LO2
-18.0
-17.5
-17.0
-16.5
-16.0
4.7
4.8
4.9
5.0
5.1
5.2
5.3
Supply Voltage (V)
Prescalar
Sensitivity
(
dBm)
Figure 16: Typical Downconverter Prescaler
Sensitivity vs. Ambient Temperature
(V = +5 V, f
= 1000 MHz)
DD
LO2
-17.5
-17.0
-16.5
-16.0
-15.5
-15.0
25
35
45
55
65
75
85
Ambient Temperature (C)
Prescalar
Sensitivity
(
dBm)
10
PRELIMINARY DATA SHEET - Rev 1.3
12/2003
ACD2203
Figure 17: Typical Conversion Gain and Noise
Figure vs. LNA/Mixer Current Control Resistor R1
(T = +25 C, V = +5 V, f
= 1042 MHz)
A
DD
LO2
10
11
12
13
14
15
0
5
10
15
20
25
R1Resistor Value(
W
)
C
o
n
ver
si
o
n
G
a
i
n
(
d
B
)
3.0
3.4
3.8
4.2
4.6
5.0
N
o
i
s
e
F
i
gur
e
(
dB
)
ConversionGain
NoiseFigure
Figure 18: Typical Total Current Consumption
vs. LNA/Mixer Current Control Resistor R1
(T = +25 C, V = +5 V)
A
DD
80
100
120
140
160
180
200
0
5
10
15
20
25
R1 Resistor Value (
W
)
Current
(
m
A
)
Figure 19: Typical Input IP3
vs. LNA/Mixer Current Control Resistor R1
(T = +25 C, V = +5 V)
A
DD
9
11
13
15
17
19
0
5
10
15
20
25
R1 Resistor Value (
W
)
IIP3
(
d
B
m
)
Figure 20: Typical Cross Modulation
vs. LNA/Mixer Current Control Resistor R1
(T = +25 C, V = +5 V)
A
DD
-65
-60
-55
-50
0
5
10
15
20
R1 Resistor Value (
W
)
Cross
M
odulation
(
dBc)
PRELIMINARY DATA SHEET - Rev 1.3
12/2003
11
ACD2203
LOGIC PROGRAMMING
The ACD2203 includes an interface for a two-wire
serial data control bus that ANADIGICS has
developed for use with its dual PLL synthesizers.
This interface saves one connection between the
host and the dual synthesizer, compared to a
standard CLOCK-DATA-ENABLE three-wire
interface. The interface is optimized for applications
in which the dual synthesizer is a slave receiver
device. Hosts that conform to the I
2
C-Bus
Specification standard can be used to program a
dual PLL that uses this interface.
Physical Interface
The two-wire interface consists of two digital signal
lines, CLOCK and DATA. The speed of the interface
is nominally 400 kbits/sec. For data transmission,
the signal on the DATA line must be stable when the
CLOCK signal is high, and the state of the data must
change only while the CLOCK signal is low. A logic
level transition on the DATA line during a high
CLOCK signal indicates the beginning or end of a
data transmission, as specified in the following
sections and shown in Figure 21.
(10) decodes an analog voltage input into two digital
logic output bits AS1 and AS2. The level of a DC
voltage applied to this pin determines the two-bit
logic state, AS2 and AS1 to address the synthesizer.
The software must be programmed with the
corresponding decimal equivalent of the 8b word
selected, as shown in Table 7. Once the dual PLL
has recognized the Start indicator and the
correct address word, it sends an address
acknowledgement to the host by pulling the DATA
line low for one clock pulse. The host can then begin
to send data to program the dual PLL.
Sending Data
After receiving the address byte acknowledgement
from the dual PLL, the host begins sending
programming data in 8-bit words. The MSB is sent
first, and the LSB last. Following the receipt of each
8-bit data word, the dual PLL acknowledges receipt
by pulling the DATA line low for one clock pulse. The
data acknowledgement tells the host it may send
the next data word. For the dual PLL, each group of
three data words (24 bits total) is a significant block
of information used to program one of four registers,
as described in "Programming the Dual PLL."
Completing Data Transmissions
After sending the final data word, the host sends a
Stop indicator to mark the end of data transmission.
A Stop is indicated by a low-to-high transition of the
DATA signal while the CLOCK signal is held high.
After receiving the Stop indicator, the dual PLL ceases
to send further acknowledgements and begins to
monitor the CLOCK and DATA signals for the next
Start indicator.
Note: The Stop indicator does not directly control
when the programming data is latched or takes
effect; the data takes effect immediately following
the receipt of each three-word block of data, which
represents a complete 24-bit divider register.
Resending Data
If, for some reason, the data transmission fails or is
interrupted, and the dual PLL fails to send an
address word or data word acknowledgement to
the host, the host can resend the data. To resend
data, a new Start indicator and address word must
be sent prior to any data words.
Programming The Dual PLL
Each synthesizer in the dual PLL contains
programmable Reference and Main dividers, which
DATA
CLOCK
Stop
Indicator:
DATA
CLOCK
Start
Indicator:
Figure 21: Transmission Indicators
Addressing The Dual PLL
The dual PLL monitors the CLOCK and DATA
signals for a Start indication from the host. A Start is
indicated by a high-to-low transition of the DATA
signal while the CLOCK signal is high. Immediately
following the Start indicator, the host sends an 8-bit
address word to the dual PLL. The 8-bit word
required to address the dual PLL is programmable
via a DC voltage level applied to the address select
pin. For example, a voltage of 4V<AS<5V
corresponds to a value of C6h, or 11000110b. (The
MSB is sent first, LSB last.) The Address Select pin
12
PRELIMINARY DATA SHEET - Rev 1.3
12/2003
ACD2203
allow a wide range of output frequencies. The 24-bit
registers that control the dividers and other functions
are each segmented into three 8-bit data words, and
are programmed via the two-wire interface.
Register Select Bits
The two least significant bits of each register are
register select bits that determine which register is
programmed during a particular data entry cycle.
Table 8 indicates the register select bit settings used
to program each of the available registers.
N
I
P
N
O
E
G
A
T
L
O
V
S
A
,
0
1
)
2
1
Y
R
A
N
I
B
(
C
1
S
A
2
S
A
X
E
H
L
A
M
I
C
E
D
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
B
V
S
S
V
8
.
0
<
S
A
<
1
1
0
0
0
0
1
0
2
C
4
9
1
V
7
.
1
<
S
A
<
V
1
.
1
1
1
0
0
0
0
0
0
0
C
2
9
1
V
7
.
2
<
S
A
<
V
1
.
2
1
1
0
0
0
1
0
0
4
C
6
9
1
V
5
6
.
3
<
S
A
<
V
5
1
.
3
1
1
0
0
0
0
0
0
0
C
2
9
1
V
<
S
A
<
V
2
.
4
D
D
1
1
0
0
0
1
1
0
6
C
8
9
1
Table 7: Address Select Decoding
(T
A
= +25 C
(1)
, V
DD
= +5 VDC)
Table 8: Register Select Bits
T
C
E
L
E
S
S
T
I
B
R
O
F
R
E
T
S
I
G
E
R
N
O
I
T
A
N
I
T
S
E
D
A
T
A
D
L
A
I
R
E
S
S
2
S
1
0
0
2
L
L
P
r
o
f
r
e
t
s
i
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e
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r
e
d
i
v
i
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e
c
n
e
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e
f
e
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0
1
2
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L
P
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o
f
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e
t
s
i
g
e
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r
e
d
i
v
i
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i
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L
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e
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1
1
1
L
L
P
r
o
f
r
e
t
s
i
g
e
R
r
e
d
i
v
i
D
n
i
a
M
Main Divider Programming
The main divider register for each synthesizer
consists of seven A counter bits, eleven B counter
bits, two program mode bits and the two register
select bits, as shown in Table 11. The main divider
divide ratio, N, is determined by the values in the A
and B counters. The eleven B Counter bits and
allowed values are shown in Table 12, and the seven
A Counter bits and allowed values are shown in
Table 13. Note that there are some limitations on
the ranges of the values for each counter.
Pulse Swallow Function
The VCO output frequency for the local oscillator is
computed using the following equation; the variables
are defined in Table 14:
f
VCO
= N x f
OSC
/R, where N = [(P x B) + A]
where:
N = [(P x B) + A]
f
VCO
is the desired output frequency
B is the divide ratio of the B counter (3 to 2047)
A is the divide ratio of the A counter (0<A<P, A<B)
f
OSC
is the frequency of the reference oscillator
R is the divide ratio of the R counter (3 to 32767)
P is the preset modulus of the prescalar (P=64).
Reference Divider Programming
The reference divider register for each synthesizer
consists of fifteen divider bits, five program mode
bits and the two register select bits, as shown in
Table 9. The fifteen divider bits allow a divide ratio
from 3 to 32767, inclusive, as shown in Table 10.
Notes:
(1) Case Temperature is 15 C higher than Ambient Temperature, when Ambient Temperature is
+25 C, using the PC Board Layout shown in Figures 24-26.
PRELIMINARY DATA SHEET - Rev 1.3
12/2003
13
ACD2203
Notes:
Divide ratios less than 3 are prohibited.
Table 10: Reference Divider R Counter Bits
E
D
I
V
I
D
R
O
I
T
A
R
R
5
1
R
4
1
R
3
1
R
2
1
R
1
1
R
0
1
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
3
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
7
6
7
2
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Table 12: Main Divider B Counter Bits
Notes:
B > A, Divide ratios less than 3 are prohibited.
B
F
O
E
U
L
A
V
R
E
T
N
U
O
C
B
1
1
B
0
1
B
9
B
8
B
7
B
6
B
5
B
4
B
3
B
2
B
1
3
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
1
0
0
-
-
-
-
-
-
-
-
-
-
-
-
7
4
0
2
1
1
1
1
1
1
1
1
1
1
1
Table 11: Main Divider Registers
LSB
MSB
D
R
O
W
A
T
A
D
T
S
R
I
F
D
R
O
W
A
T
A
D
D
N
O
C
E
S
D
R
O
W
A
T
A
D
D
R
I
H
T
4
2
3
2
2
2
1
2
0
2
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
1
9
8
7
6
5
4
3
2
1
/
y
m
m
u
D
r
e
c
a
p
S
m
a
r
g
o
r
P
e
d
o
M
r
e
t
n
u
o
C
B
r
e
t
n
u
o
C
A
t
c
e
l
e
S
X
2
X
1
C
2
C
1
B
1
1
B
0
1
B
9
B
8
B
7
B
6
B
5
B
4
B
3
B
2
B
1
A
7
A
6
A
5
A
4
A
3
A
2
A
1
S
2
S
1
Data Word
Register Bit
Function
Data
LSB
MSB
Table 9: Reference Divider Registers
D
R
O
W
A
T
A
D
T
S
R
I
F
D
R
O
W
A
T
A
D
D
N
O
C
E
S
D
R
O
W
A
T
A
D
D
R
I
H
T
4
2
3
2
2
2
1
2
0
2
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
1
9
8
7
6
5
4
3
2
1
/
y
m
m
u
D
r
e
c
a
p
S
e
d
o
M
m
a
r
g
o
r
P
R
,
o
i
t
a
R
e
d
i
v
i
D
r
e
d
i
v
i
D
e
c
n
e
r
e
f
e
R
t
c
e
l
e
S
X
2
X
1
D
5
D
4
D
3
D
2
D
1
R
5
1
R
4
1
R
3
1
R
2
1
R
1
1
R
0
1
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
S
2
S
1
Data Word
Register Bit
Function
Data
14
PRELIMINARY DATA SHEET - Rev 1.3
12/2003
ACD2203
Programmable Modes
Each register contains bits set aside for programming
different modes of operation in the synthesizers. Bit
D1 in each reference divider register controls the phase
detector polarity. Table 14 shows how this bit controls
the polarity, and the correct setting is determined by
using Table 15 and Figure 22.
Table 15: Phase Detector Polarity Selection
D
1
Y
T
I
R
A
L
O
P
O
C
V
S
C
I
T
S
I
R
E
T
C
A
R
A
H
C
0
e
v
it
a
g
e
N
)
2
(
e
v
r
u
c
1
e
v
it
i
s
o
P
)
1
(
e
v
r
u
c
Figure 22: VCO Characteristics
(1)
(2)
VCO INPUT VOLTAGE
VCO OUTPUT
FREQUENCY
Bit C1 in each main divider register sets the
prescalar mode. Table 16 indicates the appropriate
settings. (Currently, there is only one prescalar
mode available for use.)
Table 16: Prescalar Mode
C
1
E
D
O
M
R
A
L
A
C
S
E
R
P
0
5
6
/
4
6
1
)
e
s
u
e
r
u
t
u
f
r
o
f
d
e
v
r
e
s
e
r
(
Table 14: Phase Detector Polarity Bit
S
2
S
1
D
1
0
0
y
ti
r
a
l
o
P
r
o
t
c
e
t
e
D
e
s
a
h
P
2
L
L
P
1
0
y
ti
r
a
l
o
P
r
o
t
c
e
t
e
D
e
s
a
h
P
1
L
L
P
Table 13: Main Divider A Counter Bits
Notes:
B > A, A < P
A
F
O
E
U
L
A
V
R
E
T
N
U
O
C
A
7
A
6
A
5
A
4
A
3
A
2
A
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
-
-
-
-
-
-
-
-
7
2
1
1
1
1
1
1
1
1
Bit C2 in the main divider registers, bits D2 through
D5 in the reference divider registers, and bits X1
and X2 in all registers are reserved for future use,
and have no current function. They can be set either
high or low without affecting synthesizer
performance.
PRELIMINARY DATA SHEET - Rev 1.3
12/2003
15
ACD2203
Synthesizer Programming Example
The following example for programming the two synthesizers in the dual PLL details the calculations used
to determine the required value of each bit in all four registers:
Requirements
Desired CATV input channel: "HHH" - 499.25 MHz picture carrier (501 MHz digital channel center frequency)
(Second) IF picture carrier output frequency: 45.75 MHz (44 MHz digital channel center frequency)
First IF frequency: 1087.75 MHz (recommended)
Phase detector comparison frequency for down converter (also tuning increment): 62.5 KHz
Phase detector comparison frequency for up converter: 250 KHz
Crystal reference oscillator frequency: 4 MHz
Calculation of Reference Divider Values
The value for each reference divider is calculated by dividing the reference oscillator frequency by the desired
phase detector comparison frequency:
R = f
OSC
/ f
PD
For the down converter, the 4 MHz crystal oscillator frequency and the 62.5 KHz phase detector comparison
frequency are used to yield R
PLL2
= 4 MHz / 62.5 KHz = 64, and so the bit values for the down converter
R counter are R
PLL2
= 000000001000000.
For the up converter, the 4 MHz crystal oscillator frequency and the 250 KHz phase detector comparison
frequency are used to yield R
PLL1
= 4 MHz / 250 KHz = 16, and so the bit values for the up converter R counter
are R
PLL1
= 000000000010000.
Calculation of Main Divider Values
The values for the A and B counters are determined by the desired VCO output frequency for the local
oscillator and the phase detector comparison frequency:
N = f
VCO
/ f
PD
B = trunc(N / P)
A = N - (B x P)
The down converter local oscillator frequency will be 1087.75 MHz - 45.75 MHz = 1042 MHz in this example.
The main divider ratio for the down converter, then, is N
PLL2
= 1042 MHz / 62.5 KHz = 16672. Since P = 64 in the
ACD2203, B
PLL2
= trunc(16672 / 64) = 260, and A
PLL2
= 16672 - (260 x 64) = 32. These results give bit values
of B
PLL2
= 00100000100 and A
PLL2
= 0100000 for the B and A counters.
The up converter local oscillator frequency will be 499.25 MHz + 1087.75 MHz = 1587 MHz in this example.
Therefore, N
PLL1
= 1587 MHz / 250 KHz = 6348, B
PLL1
= trunc(6348 / 64) = 99, and A
PLL1
= 6348 - (99 x 64) = 12.
These results give bit values of B
PLL1
= 00001100011 and A
PLL1
= 0001100 for the B and A counters.
Phase Detector Polarity
If the VCO for the up converter has a negative slope, the phase detector polarity for PLL1 should be negative,
and D1
PLL1
= 1. If the VCO for the down converter has a positive slope, the phase detector polarity for PLL2
should be positive, and D1
PLL2
= 0.
In summary, for this example, the four register programming words are shown in Tables 17 and 18 on the
following page.
16
PRELIMINARY DATA SHEET - Rev 1.3
12/2003
ACD2203
LSB
MSB
Table 17: PLL1 and PLL2 Reference Divider Register Bits
for Synthesizer Programming Example
D
R
O
W
A
T
A
D
T
S
R
I
F
D
R
O
W
A
T
A
D
D
N
O
C
E
S
D
R
O
W
A
T
A
D
D
R
I
H
T
4
2
3
2
2
2
1
2
0
2
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
1
9
8
7
6
5
4
3
2
1
/
y
m
m
u
D
r
e
c
a
p
S
e
d
o
M
m
a
r
g
o
r
P
R
,
o
i
t
a
R
e
d
i
v
i
D
r
e
d
i
v
i
D
e
c
n
e
r
e
f
e
R
t
c
e
l
e
S
X
2
X
1
D
5
D
4
D
3
D
2
D
1
R
5
1
R
4
1
R
3
1
R
2
1
R
1
1
R
0
1
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
S
2
S
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
Data Word
Register Bit
Function
Data
PLL2
PLL1
LSB
MSB
Table 18: PLL1 and PLL2 Main Divider Register Bits
for Synthesizer Programming Example
D
R
O
W
A
T
A
D
T
S
R
I
F
D
R
O
W
A
T
A
D
D
N
O
C
E
S
D
R
O
W
A
T
A
D
D
R
I
H
T
4
2
3
2
2
2
1
2
0
2
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
1
9
8
7
6
5
4
3
2
1
/
y
m
m
u
D
r
e
c
a
p
S
m
a
r
g
o
r
P
e
d
o
M
r
e
t
n
u
o
C
B
r
e
t
n
u
o
C
A
t
c
e
l
e
S
X
2
X
1
C
2
C
1
B
1
1
B
0
1
B
9
B
8
B
7
B
6
B
5
B
4
B
3
B
2
B
1
A
7
A
6
A
5
A
4
A
3
A
2
A
1
S
2
S
1
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
1
1
Data Word
Register Bit
Function
Data
PLL2
PLL1
PRELIMINARY DATA SHEET - Rev 1.3
12/2003
17
ACD2203
APPLICATION INFORMATION
pins
17,18
V
SYN
V
SS
20 k
W
A
V
~ -1000
V
SYN
V
SS
pins
16,19
300 k
W
V
SYN
V
SS
pin 13
V
SYN
V
SS
pin 14
200
W
GND
pin 1
pin 2
pin 4
GND
5 k
W
5 k
W
10
W
pin 24
pin 5
OSC
GND
V
SUP
15
W
10 pF
GND
pin 28
pin 27
GND
5
W
5
W
5 pF
5 pF
Figure 23: Equivalent Circuits
18
PRELIMINARY DATA SHEET - Rev 1.3
12/2003
ACD2203
Figure 24: PC Board Layout Top View
Figure 26: PC Board Layout Bottom View
Figure 25: PC Board Layout Mid View
Figure 27: Evaluation Fixture
Table 19: J1 Header Pinout
Balun
J1
RF
IF
AFC
Out
LO
In
RF
1
4M
H
z
Xt
a
l
ACD2
2
0
3
Table 20: Fixture Pinout
N
I
P
N
O
I
T
C
N
U
F
1
k
c
o
l
C
2
a
t
a
D
3
d
n
u
o
r
G
4
S
A
5
C
D
V
5
+
6
C
D
V
0
3
+
N
I
P
N
O
I
T
C
N
U
F
F
R
t
u
p
n
I
F
R
r
e
t
r
e
v
n
o
c
n
w
o
D
F
R
t
u
p
n
I
F
R
r
e
t
r
e
v
n
o
c
n
w
o
D
F
I
)
d
e
d
n
E
e
l
g
n
i
S
(
t
u
p
t
u
O
F
I
t
u
O
C
F
A
ti
u
c
r
i
C
g
n
i
n
u
T
r
o
t
a
ll
i
c
s
O
r
e
t
r
e
v
n
o
c
p
U
o
T
n
I
O
L
F
R
r
e
z
i
s
e
h
t
n
y
S
U
t
u
p
n
I
O
L
PRELIMINARY DATA SHEET - Rev 1.3
12/2003
19
ACD2203
Figure 28: Evaluation Fixture Schematic
2
27
16
15
1
14
22
24
25
23
21
20
19
18
17
28
26
9
8
7
10
6
11
5
12
4
13
3
RF
IN+
OSC
GND
OSC
GND
T
CKT
I
SET
GND
RF
IN-
DA
T
A
CLK
REF
IN
REF
OUT
V
SYN
V
SS
GND
V
SS
GND
RF
D
CP
D
V
SUP
OSC
OUT
CP
U
V
IF
+I
F
OUT-
RF
U
V
IF
+I
F
OUT+
V
SS
V
SS
AS
GND
C20
R7
D1
ACD2203
R1
C2
C3
L1
C8
C21
C23
C22
L3
C24
C12
C1
1
C10
R8
L2
R9
C13
R10
C14
C15
R1
1
C17
C16
R13
RF
C1
R
F
C9
+5V
R6
X1
C7
LO
IN
DT1
IF
+5V
R12
AFC
OUT
Q1
C18
C19
+30V
R3
R4
C5
C6
1
6
5
4
3
2
J1
+30V
+5V
NC
X
AS
address
select
voltage
(see
T
able
7)
20
PRELIMINARY DATA SHEET - Rev 1.3
12/2003
ACD2203
Table 21: Evaluation Fixture Parts List
#
M
E
T
I
E
U
L
A
V
E
Z
I
S
N
O
I
T
P
I
R
C
S
E
D
#
T
R
A
P
Y
T
Q
R
O
D
N
E
V
,
2
C
,
1
C
0
2
C
F
p
0
0
1
3
0
6
0
r
o
ti
c
a
p
a
c
-
p
i
h
C
V
0
5
J
1
0
1
G
O
C
9
3
M
R
G
3
a
t
a
r
u
M
3
C
F
p
5
3
0
6
0
r
o
ti
c
a
p
a
c
-
p
i
h
C
V
0
5
C
0
5
0
G
O
C
9
3
M
R
G
1
a
t
a
r
u
M
8
C
,
7
C
F
p
0
3
3
0
6
0
r
o
ti
c
a
p
a
c
-
p
i
h
C
V
0
5
J
0
0
3
G
O
C
9
3
M
R
G
2
a
t
a
r
u
M
2
1
C
F
u
0
2
2
A
V
V
0
1
s
e
ir
e
S
r
o
ti
c
a
p
a
C
D
N
-
T
C
0
4
0
2
E
C
P
1
Y
E
K
-I
G
I
D
,
1
1
C
,
9
C
,
1
2
C
,
4
1
C
2
2
C
F
u
1
.
3
0
6
0
r
o
ti
c
a
p
a
c
-
p
i
h
C
V
6
1
Z
4
0
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tf
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c
li
o
C
PRELIMINARY DATA SHEET - Rev 1.3
12/2003
21
ACD2203
Table 21: Evaluation Fixture Parts List continued
#
M
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T
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22
PRELIMINARY DATA SHEET - Rev 1.3
12/2003
ACD2203
PACKAGE OUTLINE
Figure 29: S8 Package Outline - 28 Pin SSOP
PRELIMINARY DATA SHEET - Rev 1.3
12/2003
23
ACD2203
NOTES
24
IMPORTANT NOTICE
ANADIGICS, Inc. reserves the right to make changes to its products or to discontinue any product at any time without
notice. The product specifications contained in Advanced Product Information sheets and Preliminary Data Sheets are
subject to change prior to a product's formal introduction. Information in Data Sheets have been carefully checked and are
assumed to be reliable; however, ANADIGICS assumes no responsibilities for inaccuracies. ANADIGICS strongly urges
customers to verify that the information they are using is current before placing orders.
WARNING
ANADIGICS products are not intended for use in life support appliances, devices, or systems. Use of an ANADIGICS
product in any such application without written consent is prohibited.
ANADIGICS, Inc.
141 Mount Bethel Road
Warren, New Jersey 07059, U.S.A
Tel: +1 (908) 668-5000
Fax: +1 (908) 668-5132
URL: http://www.anadigics.com
E-mail: Mktg@anadigics.com
PRELIMINARY DATA SHEET - Rev 1.3
12/2003
ACD2203
ORDERING INFORMATION
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