08/2001
ARA2005
Reverse Amplifier with Step Attenuator
PRELIMINARY DATA SHEET - Rev 1.3
FEATURES
Low cost integrated monolithic GaAs amplifier
with step attenuator
Attenuation Range: 0-58 dB, adjustable in
4dB increments via a 4 wire parallel control
Meets DOCSIS distortion requirements at a
+60dBmV output signal level
Low distortion and low noise
Frequency range: 5-100MHz
5 Volt operation
-40 to +85
0
C temperature range
APPLICATIONS
MCNS/DOCSIS Compliant Cable Modems
CATV Interactive Set-Top Box
Telephony over Cable Systems
OpenCable Set-Top Box
Residential Gateway
The ARA2005 is a monolithic GaAs device designed
to provide the reverse path amplification and output
level control functions in a Cable TV Set Top Box or
Cable Modem. It incorporates a digitally controlled
precision step attenuator, which is preceded by an
ultra low noise amplifier stage and followed by an
ulta-linear output driver amplifier. The ARA2005 uses
a balanced circuit design that exceeds the MCNS/
DOCSIS requirement for harmonic performance at a
+60 dBmV output level while requiring only a single
+5V supply. Both the input and output of the device
are matched to 75 Ohms with an appropriate
transformer. The precision attenuator provides up to
58 dB of attenuation in 4 dB increments,
programmable via a four-bit digital control interface.
With external passive components, this device meets
IEC 1000-4-12 and ANSI/IEEE C62.41-1991 100KHz
ringwave tests, as well as IEC1000-4-5 1.2/50mS
surge tests. The ARA2005 is offered in a 28-pin SSOP
package.
PRODUCT DESCRIPTION
Figure 1: Cable Modem or Set Top Box Application Diagram
S8 Package
28 Pin SSOP
Diplexer
ARA2005
SAW
Filter
Double-
Conversion
Tuner
MAC
Upstream
QPSK/16QAM
Modulator
QAM Receiver
with FEC
Balun
Low Pass
Filter
Transmit Enable/Disable
Attenuation Control
Microcontroller
with Ethernet
MAC
RAM
ROM
10Base-T
Transceiver
RJ45
Connector
Clock
Clock
Data
Data
54-860 MHz
44 MHz
5-42 MHz
4
2
PRELIMINARY DATA SHEET - Rev 1.3
08/2001
ARA2005
Figure 2: Functional Block Diagram
Figure 3: Pin Out
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
GND
I
SET1
A1
OUT
(-)
Vg1
ATT
IN
(-)
A1
IN
(+)
A1
OUT
(+)
ATT
IN
(+)
32 dB
V
ATTN
16 dB
A1
IN
(-)
A2
OUT
(-)
I
SET2
A2
IN
(-)
Vg2
ATT
OUT
(-)
A2
OUT
(+)
A2
IN
(+)
ATT
OUT
(+)
4 dB
GND
8 dB
GND
GND
GND
GND
32 dB
16 dB
8 dB
4 dB
EFET
EFET
ATT
IN
(+)
A1
OUT
(+)
A1
IN
(+)
I
SET1
Vg1
A1
OUT
(-)
A1
IN
(-)
ATT
IN
(-)
ATT
OUT
(-)
A2
IN
(-)
A2
OUT
(-)
Vg2
I
SET2
A2
OUT
(+)
A2
IN
(+)
ATT
OUT
(+)
16 dB
4 dB
8 dB
32 dB
PRELIMINARY DATA SHEET - Rev 1.3
08/2001
3
ARA2005
Table 1: Pin Description
Notes:
(1) Pins should be AC-coupled. No external DC bias should be applied.
N
I
P
E
M
A
N
N
O
I
T
P
I
R
C
S
E
D
N
I
P
E
M
A
N
N
O
I
T
P
I
R
C
S
E
D
1
D
N
G
d
n
u
o
r
G
5
1
B
d
8
ti
B
l
o
rt
n
o
C
n
o
it
a
u
n
e
tt
A
B
d
8
2
V
N
T
T
A
r
o
t
a
u
n
e
tt
A
r
o
f
y
l
p
p
u
S
6
1
B
d
4
ti
B
l
o
rt
n
o
C
n
o
it
a
u
n
e
tt
A
B
d
4
3
T
T
A
N
I
)
+
(
)
+
(
t
u
p
n
I
r
o
t
a
u
n
e
tt
A
)
1
(
7
1
T
T
A
T
U
O
)-
(
t
u
p
t
u
O
)-
(
r
o
t
a
u
n
e
tt
A
)
1
(
4
1
A
T
U
O
)
+
(
t
u
p
t
u
O
)
+
(
1
A
r
e
if
il
p
m
A
8
1
2
A
N
I
)-
(
t
u
p
n
I
)-
(
2
A
r
e
if
il
p
m
A
)
1
(
5
D
N
G
d
n
u
o
r
G
9
1
D
N
G
d
n
u
o
r
G
6
1
A
N
I
)
+
(
t
u
p
n
I
)
+
(
1
A
r
e
if
il
p
m
A
)
1
(
0
2
2
A
T
U
O
)-
(
t
u
p
t
u
O
)-
(
2
A
r
e
if
il
p
m
A
7
1
g
V
l
o
rt
n
o
C
)-
/
+
(
1
A
r
e
if
il
p
m
A
1
2
I
2
T
E
S
t
n
e
rr
u
C
)-
/
+
(
2
A
r
e
if
il
p
m
A
t
s
u
j
d
A
8
I
1
T
E
S
t
n
e
rr
u
C
)-
/
+
(
1
A
r
e
if
il
p
m
A
t
s
u
j
d
A
2
2
2
g
V
l
o
rt
n
o
C
)-
/
+
(
2
A
r
e
if
il
p
m
A
9
1
A
N
I
)-
(
t
u
p
n
I
)-
(
1
A
r
e
if
il
p
m
A
)
1
(
3
2
2
A
T
U
O
)
+
(
t
u
p
t
u
O
)
+
(
2
A
r
e
if
il
p
m
A
0
1
D
N
G
d
n
u
o
r
G
4
2
D
N
G
d
n
u
o
r
G
1
1
1
A
T
U
O
)-
(
t
u
p
t
u
O
)-
(
1
A
r
e
if
il
p
m
A
5
2
2
A
N
I
)
+
(
t
u
p
n
I
)
+
(
2
A
r
e
if
il
p
m
A
)
1
(
2
1
T
T
A
N
I
)-
(
)-
(
t
u
p
n
I
r
o
t
a
u
n
e
tt
A
)
1
(
6
2
T
T
A
T
U
O
)
+
(
t
u
p
t
u
O
)
+
(
r
o
t
a
u
n
e
tt
A
)
1
(
3
1
B
d
2
3
ti
B
l
o
rt
n
o
C
n
o
it
a
u
n
e
tt
A
B
d
2
3
7
2
D
N
G
d
n
u
o
r
G
4
1
B
d
6
1
ti
B
l
o
rt
n
o
C
n
o
it
a
u
n
e
tt
A
B
d
6
1
8
2
D
N
G
d
n
u
o
r
G
4
PRELIMINARY DATA SHEET - Rev 1.3
08/2001
ARA2005
ELECTRICAL CHARACTERISTICS
R
E
T
E
M
A
R
A
P
N
I
M
X
A
M
T
I
N
U
)
3
2
,
0
2
,
1
1
,
4
,
2
s
n
i
p
(
y
l
p
p
u
S
g
o
l
a
n
A
0
9
C
D
V
)
2
2
,
7
s
n
i
p
(
2
g
V
,
1
g
V
s
l
o
rt
n
o
C
r
e
if
il
p
m
A
5
-
2
V
F
R
s
t
u
p
n
I
t
a
r
e
w
o
P
6
s
n
i
p
(
9
, )
-
0
6
+
V
m
B
d
)
6
1
,
5
1
,
4
1
,
3
1
s
n
i
p
(
s
l
o
rt
n
o
C
r
o
t
a
u
n
e
tt
A
0
6
V
e
r
u
t
a
r
e
p
m
e
T
e
g
a
r
o
t
S
5
5
-
0
0
2
+
0
C
e
r
u
t
a
r
e
p
m
e
T
g
n
ir
e
d
l
o
S
-
0
6
2
0
C
e
m
i
T
g
n
ir
e
d
l
o
S
-
5
c
e
S
Table 2: Absolute Minimum and Maximum Ratings
Table 3: Operating Ranges
R
E
T
E
M
A
R
A
P
N
I
M
P
Y
T
X
A
M
T
I
N
U
V
:
y
l
p
p
u
S
r
e
if
il
p
m
A
DD
)
3
2
,
0
2
,
1
1
,
4
s
n
i
p
(
5
.
4
5
7
C
D
V
V
:
y
l
p
p
u
S
r
o
t
a
u
n
e
tt
A
ATTN
)
2
n
i
p
(
V
DD
5
.
0
-
5
7
C
D
V
)
6
1
,
5
1
,
4
1
,
3
1
s
n
i
p
(
s
l
o
rt
n
o
C
r
o
t
a
u
n
e
tt
A
0
-
V
DD
5
.
0
+
V
)
2
2
,
7
s
n
i
p
(
2
g
V
,
1
g
V
s
l
o
rt
n
o
C
r
e
if
il
p
m
A
5
-
1
2
V
e
r
u
t
a
r
e
p
m
e
T
e
s
a
C
0
4
-
5
2
5
8
0
C
Stresses in excess of the absolute ratings may cause permanent damage.
Functional operation is not implied under these conditions. Exposure to
absolute ratings for extended periods of time may adversely affect
reliability.
The device may be operated safely over these conditions; however, parametric
performance is guaranteed only over the conditions defined in the electrical specifications.
Notes:
1. Pins 3, 6, 9, 12, 17, 18, 25 and 26 should be AC-coupled. No external DC
bias should be applied.
2. Pins 8 and 21 should be grounded or pulled to ground through a resistor. No
external DC bias should be applied.
PRELIMINARY DATA SHEET - Rev 1.3
08/2001
5
ARA2005
R
E
T
E
M
A
R
A
P
N
I
M
P
Y
T
X
A
M
T
I
N
U
S
T
N
E
M
M
O
C
)
1
1
,
4
s
n
i
p
(
t
n
e
rr
u
C
1
A
r
e
if
il
p
m
A
-
-
8
4
4
.
2
0
8
6
A
m
d
e
l
b
a
n
e
x
T
d
e
l
b
a
s
i
d
x
T
)
3
2
,
0
2
s
n
i
p
(
t
n
e
rr
u
C
2
A
r
e
if
il
p
m
A
-
-
0
7
7
.
3
0
1
1
9
A
m
d
e
l
b
a
n
e
x
T
d
e
l
b
a
s
i
d
x
T
)
2
n
i
p
(
t
n
e
rr
u
C
r
o
t
a
u
n
e
tt
A
-
2
5
A
m
n
o
it
p
m
u
s
n
o
C
r
e
w
o
P
l
a
t
o
T
-
-
0
0
6
0
4
0
0
9
0
0
1
W
m
d
e
l
b
a
n
e
x
T
d
e
l
b
a
s
i
d
x
T
Table 4: DC Electrical Specifications
T
A
=25
C; V
DD
, V
ATTN
= +5.0 VDC; Vg1, Vg2 = +1.0 V (Tx enabled); Vg1, Vg2 = 0 V (Tx disabled)
R
E
T
E
M
A
R
A
P
N
I
M
P
Y
T
X
A
M
T
I
N
U
S
T
N
E
M
M
O
C
)
z
H
M
0
1
(
n
i
a
G
5
.
7
2
3
.
9
2
5
.
0
3
B
d
g
n
it
t
e
s
n
o
it
a
u
n
e
tt
a
B
d
0
s
s
e
n
t
a
l
F
n
i
a
G
-
-
5
7
.
0
5
.
1
-
-
B
d
z
H
M
2
4
o
t
5
z
H
M
5
6
o
t
5
e
r
u
t
a
r
e
p
m
e
T
r
e
v
o
n
o
it
a
ir
a
V
n
i
a
G
-
6
0
0
.
0
-
-
C
/
B
d
s
p
e
t
S
n
o
it
a
u
n
e
tt
A
B
d
4
B
d
8
B
d
6
1
B
d
2
3
6
.
3
5
.
7
0
.
5
1
2
.
0
3
5
7
.
3
5
7
.
7
4
.
5
1
5
7
.
0
3
0
.
4
0
.
8
8
.
5
1
3
.
1
3
B
d
c
i
n
o
t
o
n
o
M
n
o
it
a
u
n
e
tt
A
m
u
m
i
x
a
M
3
.
6
5
8
.
7
5
1
.
9
5
B
d
2
d
n
l
e
v
e
L
n
o
it
r
o
t
s
i
D
c
i
n
o
m
r
a
H
)
z
H
M
0
1
(
-
5
7
-
3
5
-
c
B
d
s
m
h
O
5
7
o
t
n
i
V
m
B
d
0
6
+
3
d
r
l
e
v
e
L
n
o
it
r
o
t
s
i
D
c
i
n
o
m
r
a
H
)
z
H
M
0
1
(
-
0
6
-
3
5
-
c
B
d
s
m
h
O
5
7
o
t
n
i
V
m
B
d
0
6
+
t
p
e
c
r
e
t
n
I
t
u
p
t
u
O
r
e
d
r
O
d
r
3
8
7
-
-
V
m
B
d
n
o
i
s
s
e
r
p
m
o
C
n
i
a
G
B
d
1
-
5
.
8
6
-
V
m
B
d
e
r
u
g
i
F
e
s
i
o
N
-
0
.
3
0
.
4
B
d
s
s
o
l
n
u
l
a
b
t
u
p
n
i
s
e
d
u
l
c
n
I
Table 5: AC Electrical Specifications
T
A
=25
C; V
DD
, V
ATTN
= +5.0 VDC; Vg1, Vg2 = +1.0 V (Tx enabled); Vg1, Vg2 = 0 V (Tx disabled)
Note: As measured in ANADIGICS test fixture
6
PRELIMINARY DATA SHEET - Rev 1.3
08/2001
ARA2005
Note: As measured in ANADIGICS test fixture
continued: AC Electrical Specifications
T
A
=25
C; V
DD
, V
ATTN
= +5.0 VDC; Vg1, Vg2 = +1.0 V (Tx enabled); Vg1, Vg2 = 0 V (Tx disabled)
R
E
T
E
M
A
R
A
P
N
I
M
P
Y
T
X
A
M
T
I
N
U
S
T
N
E
M
M
O
C
r
e
w
o
P
e
s
i
o
N
t
u
p
t
u
O
.t
e
S
.
n
e
tt
A
.
n
i
M
/
l
a
n
g
i
S
o
N
/
e
v
it
c
A
.t
e
S
.
n
e
tt
A
.
x
a
M
/
l
a
n
g
i
S
o
N
/
e
v
it
c
A
-
-
-
-
5
.
8
3
-
8
.
3
5
-
V
m
B
d
h
t
d
i
w
d
n
a
b
z
H
k
0
6
1
y
n
A
z
H
M
2
4
o
t
5
m
o
rf
e
d
o
m
e
l
b
a
s
i
d
x
T
n
i
n
o
it
a
l
o
s
I
-
2
5
-
B
d
e
c
n
a
d
e
p
m
I
t
u
p
n
I
l
a
it
n
e
r
e
ff
i
D
-
0
0
3
-
s
m
h
O
9
d
n
a
6
s
n
i
p
n
e
e
w
t
e
b
)
d
e
l
b
a
n
e
x
T
(
e
c
n
a
d
e
p
m
I
t
u
p
n
I
-
5
7
-
s
m
h
O
r
e
m
r
o
f
s
n
a
rt
h
ti
w
)
d
e
l
b
a
n
e
x
T
(
s
s
o
L
n
r
u
t
e
R
t
u
p
n
I
)
e
c
n
a
d
e
p
m
i
c
it
s
ir
e
t
c
a
r
a
h
c
m
h
O
5
7
(
-
-
0
2
-
5
-
2
1
-
-
B
d
d
e
l
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7
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-
-
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1
-
5
1
-
2
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-
0
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-
B
d
d
e
l
b
a
n
e
x
T
d
e
l
b
a
s
i
d
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T
t
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r
T
e
g
a
tl
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t
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b
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x
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-
-
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7
p
-
p
V
m
g
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it
t
e
s
r
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t
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tt
a
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d
0
g
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r
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tt
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B
d
4
2
PRELIMINAR
Y
D
A
T
A
SHEET
-
Rev
1.3
08/2001
7
ARA2005
Figure
4:
T
est
Circuit
2
27
16
15
1
14
22
24
25
23
21
20
19
18
17
28
26
9
8
7
10
6
11
5
12
4
13
3
GND
I
SET1
Vg1
A1
IN
(+)
A1
OUT
(+)
ATT
IN
(+)
V
ATTN
GND
32 dB
16 dB
8 dB
A2
OUT
(-)
I
SET2
A2
IN
(-)
Vg2
ATT
OUT
(-)
A2
IN
(+)
A2
OUT
(+)
GND
4 dB
GND
A1
IN
(-)
A1
OUT
(-)
ATT
IN
(-)
ATT
OUT
(+)
GND
GND
GND
(75 Ohms)
470pF
470pF
1K Ohms
470pF
2K Ohms
Turns
Ratio
2:1
1500pF
RF Output
(75 Ohms)
0 / +3 V
Control A2
+5 V
1uF
0.1uF
3.9 Ohms
16 d
B
32 d
B
+5 V
1000pF
1000pF
1.2K Ohms
Turns
Ratio
1:2
RF Input
0 / +3 V
Control A1
+5 V
1.2K Ohms
1000pF
1000pF
1uF
0.1uF
1K Ohms
470pF
2K Ohms
ARA2005
10uH
1uF
0.1uF
Note:
Tx Enable: Control A1 and Control A2 = +3V
Tx Disable: Control A1 and Control A2 = 0V
Toko Balun
616PT-1030
2K Ohms
2K Ohms
4 d
B
8 d
B
10uH
8
PRELIMINARY DATA SHEET - Rev 1.3
08/2001
ARA2005
PERFORMANCE DATA
Figure 5: Gain & Noise Figure vs Frequency
Figure 6: Gain & Noise Figure vs V
DD
5
10
15
20
25
30
35
10
30
50
70
90
Frequency (MHz)
G
a
in
(d
B
)
2
3
4
5
6
7
8
NF
(
d
B)
Gain
Noise Figure
20
23
26
29
32
35
3
4
5
6
7
V
DD
( Volts )
GA
IN
(
d
B
)
1
2
3
4
5
6
NF (
d
B)
Gain
Noise Figure
Measured @ 30 MHz
Figure 7: Gain & Noise Figure vs Temperature
20
23
26
29
32
35
-40
-25
-10
5
20
35
50
65
80
Temperature (C
o
)
G
A
IN
(d
B
)
1
2
3
4
5
6
NF (
d
B)
Gain
Noise Figure
Measured @ 30 MHz
PRELIMINARY DATA SHEET - Rev 1.3
08/2001
9
ARA2005
Figure 8: Harmonic Distortion vs V
DD
P
OUT
= 58dBmV
Figure 9: Harmonic Distortion vs V
DD
P
OUT
= 58dBmV
-80
-70
-60
-50
-40
-30
-20
3
4
5
6
7
V
DD
( Volts )
H
a
rm
onic Level (dB
c
)
2nd Harmonic
3rd Harmonic
Measured @ 5 MHz
-80
-70
-60
-50
-40
-30
-20
3
4
5
6
7
V
DD
( Volts )
H
a
rm
oni
c Level
(
d
B
c
)
2nd Harmonic
3rd Harmonic
Measured @ 12 MHz
Figure 10: Harmonic Distortion vs Temperature
P
OUT
= 58dBmV
-80
-75
-70
-65
-60
-55
-50
-45
-40
-40
-25
-10
5
20
35
50
65
80
Temperature (C
o
)
H
a
rm
onic level (dB
c
)
2nd Harmonic
3rd Harmonic
Measured @ 5 MHz
10
PRELIMINARY DATA SHEET - Rev 1.3
08/2001
ARA2005
Figure 11: Harmonic Distortion vs Power Out
Figure 12: Transients vs Attenuation
P
OUT
= 55dBmV at 0dB attenuation
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
49
51
53
55
57
59
61
63
65
67
Pout (dBmV)
Ha
r
m
o
n
i
c
s
(
d
Bc
)
2nd
3rd
0
10
20
30
40
50
60
70
80
90
100
0
10
20
30
40
50
60
Power Attenuation (dB)
T
r
an
sien
t (m
V
)
DOCSIS 1.1 Spec.
ARA2001
ARA2005
Figure 13: Harmonic Performance over
Frequency
P
OUT
= +62dBmV
-72
-70
-68
-66
-64
-62
-60
-58
-56
-54
-52
-50
0
5
10
15
20
25
30
35
40
Frequency (MHz)
H
a
rm
oni
c Level
(
d
B
c
)
2nd Harmonic
3rd Harmonic
PRELIMINARY DATA SHEET - Rev 1.3
08/2001
11
ARA2005
Figure 14: IIP
2
& IIP
3
vs Frequency
Figure 15: IIP
2
& IIP
3
vs V
DD
20
24
28
32
36
40
5
15
25
35
45
55
65
75
85
95
Frequency (MHz)
IIP
2
(d
B
m
)
4
6
8
10
12
14
IIP
3
(d
B
m
)
IIP2
IIP3
Measured @ V
DD
= 5 Volts
Pin = -20 dBm per tone
20
24
28
32
36
40
3
4
5
6
7
V
DD
(Volts)
IIP
2
(d
B
m
)
-5
-1
3
7
11
15
IIP
3
(d
B
m
)
IIP2
IIP3
Measured @ 65 MHz
Two tones @ 29.5 MHz
12
PRELIMINARY DATA SHEET - Rev 1.3
08/2001
ARA2005
APPLICATION INFORMATION
Transmit Enable / Disable
The ARA2005 includes two amplification stages that
each can be shut down through external control pins
Vg1 and Vg2 (pins 7 and 22, respectively.) By
applying a slightly positive bias of typically +1.0 Volts,
the amplifier is enabled. In order to disable the
amplifier, the control pin needs to be pulled to
ground.
A practical way to implement the necessary control
is to use bias resistor networks similar to those
shown in the test circuit schematic (Figure 4.) Each
network includes a resistor shunted to ground that
serves as a pull-down to disable the amplifier when
no control voltage is applied. When a positive voltage
is applied, the network acts as a voltage divider that
presents the required +1.0 Volts to enable the
amplifier. By selecting different resistor values for
the voltage divider, the network can accommodate
different control voltage inputs.
The Vg1 and Vg2 pins may be connected together
directly, and controlled through a single resistor
network from a common control voltage.
Amplifier Bias Current
The I
SET
pins (8 and 21) set the bias current for the
amplification stages. Grounding these pins results
in the maximum possible current. By placing a
resistor from the pin to ground, the current can be
reduced. The recommended bias conditions use
the configuration shown in the test circuit schematic
in Figure 4.
Attenuator Control
Each of the four internal attenuation stages of the
ARA2005 is controlled by a TTL-compatible logic input
at one of the attenuator control pins (13 - 16). A logic
high will enable a given attenuator stage, and a logic
low will bypass it.
Output Transformer
Matching the output of the ARA2005 to a 75 Ohm
load is accomplished using a 2:1 turns ratio
transformer. In addition to providing an impedance
transformation, this transformer provides the bias to
the output amplifier stage via the center tap.
The transformer also cancels even mode distortion
products and common mode signals, such as the
voltage transients that occur while enabling and
disabling the amplifiers. As a result, care must be
taken when selecting the transformer to be used at
the output. It must be capable of handling the RF
and DC power requirements without saturating the
core, and it must have adequate isolation and good
phase and amplitude balance. It also must operate
over the desired frequency and temperature range
for the intended application.
ESD Sensitivity
Electrostatic discharges can cause permanent
damage to this device. Electrostatic charges
accumulate on test equipment and the human body,
and can discharge without detection. Although the
ARA2005 has some built-in ESD protection, proper
precautions and handling are strongly
recommended. Refer to the ANADIGICS application
note on ESD precautions.
PRELIMINARY DATA SHEET - Rev 1.3
08/2001
13
ARA2005
Figure 16: S8 Package Outline - 28 Pin SSOP
PACKAGE OUTLINE
14
PRELIMINARY DATA SHEET - Rev 1.3
08/2001
ARA2005
COMPONENT PACKAGING
Figure 18: Tape Dimensions
Volume quantities of the ARA2005 are supplied on
tape and reel. Each reel holds 3,500 pieces. Smaller
quantities are available in plastic tubes of 50 pieces.
Figure 17: Reel Dimensions
DIRECTION OF FEED
PRELIMINARY DATA SHEET - Rev 1.3
08/2001
15
ARA2005
NOTES
WARNING
ANADIGICS products are not intended for use in life support appliances, devices or systems. Use of an ANADIGICS
product in any such application without written consent is prohibited.
IMPORTANT NOTICE
ANADIGICS, Inc.
141 Mount Bethel Road
Warren, New Jersey 07059, U.S.A.
Tel: +1 (908) 668-5000
Fax: +1 (908) 668-5132
URL: http://www.anadigics.com
E-mail: Mktg@anadigics.com
ANADIGICS, Inc. reserves the right to make changes to its products or to discontinue any product at any time without
notice. The product specifications contained in Advanced Product Information sheets and Preliminary Data Sheets are
subject to change prior to a products formal introduction. Information in Data Sheets have been carefully checked and are
assumed to be reliable; however, ANADIGICS assumes no responsibilities for inaccuracies. ANADIGICS strongly urges
customers to verify that the information they are using is current before placing orders.
PRELIMINARY DATA SHEET - Rev 1.3
08/2001
16
ARA2005
ORDERING INFORMATION
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