March 2001
Copyright Alliance Semiconductor. All rights reserved.
AS29LV800
3V 1M 8/512K 16 CMOS Flash EEPROM
3/22/01; V.1.0
Alliance Semiconductor
P. 1 of 25
Features
Organization: 1M8/512K16
Sector architecture
- One 16K; two 8K; one 32K; and fifteen 64K byte sectors
- One 8K; two 4K; one 16K; and fifteen 32K word sectors
- Boot code sector architecture--T (top) or B (bottom)
- Erase any combination of sectors or full chip
Single 2.7-3.6V power supply for read/write operations
Sector protection
High speed 70/80/90/120 ns address access time
Automated on-chip programming algorithm
- Automatically programs/verifies data at specified address
Automated on-chip erase algorithm
- Automatically preprograms/erases chip or specified
sectors
Hardware RESET pin
- Resets internal state machine to read mode
Low power consumption
- 200 nA typical automatic sleep mode current
- 200 nA typical standby current
- 10 mA typical read current
JEDEC standard software, packages and pinouts
- 48-pin TSOP
- 44-pin SO; availability TBD
Detection of program/erase cycle completion
- DQ7 DATA polling
- DQ6 toggle bit
- DQ2 toggle bit
- RY/BY output
Erase suspend/resume
- Supports reading data from or programming data to a
sector not being erased
Low V
CC
write lock-out below 1.5V
10 year data retention at 150C
100,000 write/erase cycle endurance
Logic block diagram
X decoder
V
CC
V
SS
Cell matrix
Y decoder
Y gating
Data latch
Chip enable
A
d
dr
es
s
la
t
c
h
Input/output
buffers
Sector protect/
Command
register
Program/erase
control
V
CC
detector
Erase voltage
generator
Program voltage
generator
Timer
A0A18
CE
OE
STB
STB
Output enable
Logic
RY/BY
WE
RESET
DQ0DQ15
switches
erase voltage
BYTE
A-1
Pin arrangement
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A14
A15
A16
BYTE
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
A6
A5
A4
A3
A2
A1
A0
CE
V
SS
OE
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
44-pin SO
21
22
DQ3
DQ11
A10
A11
A12
A13
2
A18
3
A17
4
A7
1
RY/BY
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
43
42
41
44
WE
A8
A9
RESET
A8 A9
A1
0
A1
1
A1
2
A1
3
A1
4
A1
5
A1
6
BY
T
E
V
SS
DQ1
5
/
A
-1
DQ
7
DQ
14
NC
NC
WE
RES
E
T
NC
NC
RY
/
B
Y
A1
8
DQ
2
DQ
10
DQ
3
DQ
11
V
CC
DQ
4
DQ
12
DQ
5
DQ
6
DQ
13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
48
47
46
45
44
43
42
41
40
39
38
37
36
35
15
16
34
33
48-pin TSOP
A1
7
A7
A6
A5
A4
A3
A2
A1
A0 CE
V
SS
OE
DQ
0
DQ
8
DQ
1
DQ
9
17
18
19
20
21
22
32
31
30
29
28
27
23
24
26
25
AS29LV800
A
S
29
L
V
80
0
Selection guide
29LV800-70R
*
* Regulated voltage range of 3.0 to 3.6V
29LV800-80
29LV800-90
29LV800-120
Unit
Maximum access time
t
AA
70
80
90
120
ns
Maximum chip enable access time
t
CE
70
80
90
120
ns
Maximum output enable access time
t
OE
30
30
35
50
ns
AS29LV800
3/22/01; V.1.0
Alliance Semiconductor
P. 2 of 25
March 2001
Functional description
The AS29LV800 is an 8 megabit, 3.0 volt Flash memory organized as 1 Megabyte of 8 bits/512Kbytes of 16 bits each. For
flexible erase and program capability, the 8 megabits of data is divided into nineteen sectors: one 16K, two 8K, one 32K, and
fifteen 64k byte sectors; or one 8K, two 4K, one 16K, and fifteen 32K word sectors. The 8 data appears on DQ0DQ7; the
16 data appears on DQ0DQ15. The AS29LV800 is offered in JEDEC standard 48-pin TSOP and 44-pin SOP packages. This
device is designed to be programmed and erased in-system with a single 3.0V V
CC
supply. The device can also be
reprogrammed in standard EPROM programmers.
The AS29LV800 offers access times of 70/80/90/120 ns, allowing 0-wait state operation of high speed microprocessors. To
eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls. Word
mode (16 output) is selected by BYTE = high. Byte mode (8 output) is selected by BYTE = low.
The AS29LV800 is fully compatible with the JEDEC single power supply Flash standard. Write commands are sent to the
command register using standard microprocessor write timings. An internal state-machine uses register contents to control the
erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase
operations. Read data from the device occurs in the same manner as other Flash or EPROM devices. Use the program command
sequence to invoke the automated on-chip programming algorithm that automatically times the program pulse widths and
verifies proper cell margin. Use the erase command sequence to invoke the automated on-chip erase algorithm that
preprograms the sector (if it is not already programmed before executing the erase operation), times the erase pulse widths,
and verifies proper cell margin.
Boot sector architecture enables the system to boot from either the top (AS29LV800T) or the bottom (AS29LV800B) sector.
Sector erase architecture allows specified sectors of memory to be erased and reprogrammed without altering data in other
sectors. A sector typically erases and verifies within 1.0 seconds. Hardware sector protection disables both program and erase
operations in all, or any combination of, the nineteen sectors. The device provides true background erase with Erase Suspend,
which puts erase operations on hold to either read data from, or program data to, a sector that is not being erased. The chip
erase command will automatically erase all unprotected sectors.
A factory shipped AS29LV800 is fully erased (all bits = 1). The programming operation sets bits to 0. Data is programmed into
the array one byte at a time in any sequence and across sector boundaries. A sector must be erased to change bits from 0 to 1.
Erase returns all bytes in a sector to the erased state (all bits = 1). Each sector is erased individually with no effect on other
sectors.
The device features single 3.0V power supply operation for Read, Write, and Erase functions. Internally generated and
regulated voltages are provided for the Program and Erase operations. A low V
CC
detector automatically inhibits write
operations during power transtitions. The RY/BY pin, DATA polling of DQ7, or toggle bit (DQ6) may be used to detect end of
program or erase operations. The device automatically resets to the read mode after program/erase operations are completed.
DQ2 indicates which sectors are being erased.
The AS29LV800 resists accidental erasure or spurious programming signals resulting from power transitions. Control register
architecture permits alteration of memory contents only after successful completion of specific command sequences. During
power up, the device is set to read mode with all program/erase commands disabled when V
CC
is less than V
LKO
(lockout
voltage). The command registers are not affected by noise pulses of less than 5 ns on OE, CE, or WE. To initiate write
commands, CE and WE must be logical zero and OE a logical 1.
When the device's hardware RESET pin is driven low, any program/erase operation in progress is terminated and the internal
state machine is reset to read mode. If the RESET pin is tied to the system reset circuitry and a system reset occurs during an
automated on-chip program/erase algorithm, data in address locations being operated on may become corrupted and requires
rewriting. Resetting the device enables the system's microprocessor to read boot-up firmware from the Flash memory.
The AS29LV800 uses Fowler-Nordheim tunnelling to electrically erase all bits within a sector simultaneously. Bytes are
programmed one at a time using EPROM programming mechanism of hot electron injection.
AS29LV800
3/22/01; V.1.0
Alliance Semiconductor
P. 3 of 25
March 2001
Operating modes
L = Low (<V
IL
) = logic 0; H = High (>V
IH
) = logic 1; V
ID
= 10.0 1.0V; X = don't care.
In 16 mode, BYTE = V
IH
. In 8 mode, BYTE = V
IL
with DQ8-DQ14 in high Z and DQ15 = A-1.
Verification of sector protect/unprotect during A9 = V
ID.
Mode definitions
Mode
CE
OE
WE
A0
A1
A6
A9
RESET
DQ
ID read MFR code
L
L
H
L
L
L
V
ID
H
Code
ID read device code
L
L
H
H
L
L
V
ID
H
Code
Read
L
L
H
A0
A1
A6
A9
H
D
OUT
Standby
H
X
X
X
X
X
X
H
High Z
Output disable
L
H
H
X
X
X
X
H
High Z
Write
L
H
L
A0
A1
A6
A9
H
D
IN
Enable sector protect
L
V
ID
Pulse/L
L
H
L
V
ID
H
X
Sector unprotect
L
V
ID
Pulse/L
L
H
H
V
ID
H
X
Temporary sector
unprotect
X
X
X
X
X
X
X
V
ID
X
Verify sector protect
L
L
H
L
H
L
V
ID
H
Code
Verify sector unprotect
L
L
H
L
H
H
V
ID
H
Code
Hardware Reset
X
X
X
X
X
X
X
L
High Z
Item
Description
ID MFR code,
device code
Selected by A9 = V
ID
(9.5V10.5V), CE = OE = A1 = A6 = L, enabling outputs.
When A0 is low (V
IL
) the output data = 52h, a unique Mfr. code for Alliance Semiconductor Flash products.
When A0 is high (V
IH
), D
OUT
represents the device code for the AS29LV800.
Read mode
Selected with CE = OE = L, WE = H. Data is valid in t
ACC
time after addresses are stable, t
CE
after CE is low
and t
OE
after OE is low.
Standby
Selected with CE = H. Part is powered down, and I
CC
reduced to <1.0 A when CE = V
CC
0.3V = RESET. If
activated during an automated on-chip algorithm, the device completes the operation before entering
standby.
Output disable Part remains powered up; but outputs disabled with OE pulled high.
Write
Selected with CE = WE = L, OE = H. Accomplish all Flash erasure and programming through the command
register. Contents of command register serve as inputs to the internal state machine. Address latching occurs
on the falling edge of WE or CE, whichever occurs later. Data latching occurs on the rising edge WE or CE,
whichever occurs first. Filters on WE prevent spurious noise events from appearing as write commands.
Enable
sector protect
Hardware protection circuitry implemented with external programming equipment causes the device to
disable program and erase operations for specified sectors. For in-system sector protection, refer to Sector
protect algorithm on page 14.
Sector
unprotect
Disables sector protection for all sectors using external programming equipment. All sectors must be
protected prior to sector unprotection. For in-system sector unprotection, refer to Sector unprotect algorithm
on page 14.
Verify sector
protect/
unprotect
Verifies write protection for sector. Sectors are protected from program/erase operations on commercial
programming equipment. Determine if sector protection exists in a system by writing the ID read command
sequence and reading location XXX02h, where address bits A1218 select the defined sector addresses. A
logical 1 on DQ0 indicates a protected sector; a logical 0 indicates an unprotected sector.
AS29LV800
3/22/01; V.1.0
Alliance Semiconductor
P. 4 of 25
March 2001
Flexible sector architecture
In word mode, there are one 8K word, two 4K word, one 16K word, and fifteen 32K word sectors. Address range is A18A-1 if BYTE = V
IL
; address range is
A18A0 if BYTE = V
IH
.
Temporary
sector
unprotect
Temporarily disables sector protection for in-system data changes to protected sectors. Apply +10V to RESET
to activate temporary sector unprotect mode. During temporary sector unprotect mode, program protected
sectors by selecting the appropriate sector address. All protected sectors revert to protected state on removal
of +10V from RESET.
RESET
Resets the interal state machine to read mode. If device is programming or erasing when RESET = L, data
may be corrupted.
Deep
power down
Hold RESET low to enter deep power down mode (
<
1 A). Recovery time to start of first read cycle is 50ns.
Automatic
sleep mode
Enabled automatically when addresses remain stable for 300ns. Typical current draw is 1 A. Existing data is
available to the system during this mode. If an address is changed, automatic sleep mode is disabled and new
data is returned within standard access times.
Sector
Bottom boot sector architecture (AS29LV800B)
Top boot sector architecture (AS29LV800T)
8
16
Size
(Kbytes)
8
16
Size
(Kbytes)
0
00000h03FFFh
00000h01FFFh
16
00000h0FFFFh
00000h07FFFh
64
1
04000h05FFFh
02000h02FFFh
8
10000h1FFFFh
08000h0FFFFh
64
2
06000h07FFFh
03000h03FFFh
8
20000h2FFFFh
10000h17FFFh
64
3
08000h0FFFFh
04000h07FFFh
32
30000h3FFFFh
18000h1FFFFh
64
4
10000h1FFFFh
08000h0FFFFh
64
40000h4FFFFh
20000h27FFFh
64
5
20000h2FFFFh
10000h17FFFh
64
50000h5FFFFh
28000h2FFFFh
64
6
30000h3FFFFh
18000h1FFFFh
64
60000h6FFFFh
30000h37FFFh
64
7
40000h4FFFFh
20000h27FFFh
64
70000h7FFFFh
38000h3FFFFh
64
8
50000h5FFFFh
28000h2FFFFh
64
80000h8FFFFh
40000h47FFFh
64
9
60000h6FFFFh
30000h37FFFh
64
90000h9FFFFh
48000h4FFFFh
64
10
70000h7FFFFh
38000h3FFFFh
64
A0000hAFFFFh
50000h57FFFh
64
11
80000h8FFFFh
40000h47FFFh
64
B0000hBFFFFh
58000h5FFFFh
64
12
90000h9FFFFh
48000h4FFFFh
64
C0000hCFFFFh
60000h67FFFh
64
13
A0000hAFFFFh
50000h57FFFh
64
D0000hDFFFFh
68000h6FFFFh
64
14
B0000hBFFFFh
58000h5FFFFh
64
E0000hEFFFFh
70000h77FFFh
64
15
C0000hCFFFFh
60000h67FFFh
64
F0000hF7FFFh
78000h7BFFFh
32
16
D0000hDFFFFh
68000h6FFFFh
64
F8000hF9FFFh
7C000h7CFFFh
8
17
E0000hEFFFFh
70000h77FFFh
64
FA000hFBFFFh
7D000h7DFFFh
8
18
F0000hFFFFFh
78000h7FFFFh
64
FC000hFFFFFh
7E000h7FFFFh
16
Item
Description
AS29LV800
3/22/01; V.1.0
Alliance Semiconductor
P. 5 of 25
March 2001
ID Sector address table
READ codes
Key: L =Low (<V
IL
); H = High (>V
IH
); X =Don't care
Sector
Bottom boot sector address
(AS29LV800B)
Top boot sector address
(AS29LV800T)
A18
A17
A16
A15
A14
A13
A12
A18
A17
A16
A15
A14
A13
A12
0
0
0
0
0
0
0
X
0
0
0
0
X
X
X
1
0
0
0
0
0
1
0
0
0
0
1
X
X
X
2
0
0
0
0
0
1
1
0
0
1
0
X
X
X
3
0
0
0
0
1
X
X
0
0
1
1
X
X
X
4
0
0
0
1
X
X
X
0
1
0
0
X
X
X
5
0
0
1
0
X
X
X
0
1
0
1
X
X
X
6
0
0
1
1
X
X
X
0
1
1
0
X
X
X
7
0
1
0
0
X
X
X
0
1
1
1
X
X
X
8
0
1
0
1
X
X
X
1
0
0
0
X
X
X
9
0
1
1
0
X
X
X
1
0
0
1
X
X
X
10
0
1
1
1
X
X
X
1
0
1
0
X
X
X
11
1
0
0
0
X
X
X
1
0
1
1
X
X
X
12
1
0
0
1
X
X
X
1
1
0
0
X
X
X
13
1
0
1
0
X
X
X
1
1
0
1
X
X
X
14
1
0
1
1
X
X
X
1
1
1
0
X
X
X
15
1
1
0
0
X
X
X
1
1
1
1
0
X
X
16
1
1
0
1
X
X
X
1
1
1
1
1
0
0
17
1
1
1
0
X
X
X
1
1
1
1
1
0
1
18
1
1
1
1
X
X
X
1
1
1
1
1
1
X
Mode
A18A12
A6
A1
A0
Code
MFR code (Alliance Semiconductor)
X
L
L
L
52h
Device code
8 T boot
X
L
L
H
DAh
8 B boot
X
L
L
H
5Bh
16 T boot
X
L
L
H
22DAh
16 B boot
X
L
L
H
225Bh
Sector protection
Sector address
L
H
L
01h protected
00h unprotected
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