08/2001
1
S2
12 Pin 4 Sided SQFP
Package
FEATURES
Single +5 Volt Supply
Automatic Gain Control
-43 dBm Sensitivity
0 dBm Optical Overload
70 MHz Bandwidth
APPLICATIONS
OC-1 Receiver
FITL
Low Noise RF Amplifier
Figure 1: ATA00501 Equivalent Circuit
ATA00501
AGC Transimpedance Amplifier
SONET OC-1
PRELIMINARY DATA SHEET-Rev 1.5
VDD1
I
IN
GND
GND
GND GND
GND
GND
GND
GND
C
BY
C
BY
C
AGC
V
OUT
1992
19F
V
DD2
D1C
The ANADIGICS ATA00501 is a 5V low noise
transimpedance amplifier with AGC designed to be
used in OC-1 fiber optic links. The device is used in
conjunction with a photodetector (PIN diode or
avalanche photodiode) to convert an optical signal
into an output voltage. The ATA00501 has a bandwidth
of 70MHz and a dynamic range in excess of 40dB. It
is manufactured in a GaAs MESFET process and
available in bare die form or a 12 pin SQFP package.
PRODUCT DESCRIPTION
V
DD
V
OUT
C
AGC
GND
I
IN
C
BY
Photodetector cathode must be connected
To I
IN
for proper AGC operation
PATENT PENDING
GND
or
neg.supply
VGA
- 35
70K
+
4pF
+ 0.8
AGC
60K
20pF
PRELIMINARY DATA SHEET - Rev 1.5
08/2001
21.
ATA00501
Table 1: ATA00501D1C Pad Description (Die Only)
Figure 2: Bonding Pad Layout (Die Only)
ELECTRICAL CHARACTERISTICS
Table 3: Absolute Maximum Ratings
D
A
P
N
O
I
T
P
I
R
C
S
E
D
T
N
E
M
M
O
C
1
D
D
V
1
D
D
V
e
g
a
t
s
n
i
a
g
t
u
p
n
i
r
o
f
y
l
p
p
u
s
e
v
it
i
s
o
P
2
D
D
V
2
D
D
V
e
g
a
t
s
n
i
a
g
d
n
o
c
e
s
r
o
f
y
l
p
p
u
s
e
v
it
i
s
o
P
N
II
t
n
e
r
r
u
C
t
u
p
n
I
A
I
T
n
o
it
a
r
e
p
o
r
e
p
o
r
p
r
o
f
e
d
o
h
t
a
c
r
o
t
c
e
t
e
d
t
c
e
n
n
o
C
T
U
O
V
e
g
a
tl
o
V
t
u
p
t
u
O
A
I
T
k
c
o
l
b
C
D
l
a
n
r
e
t
x
e
s
e
ri
u
q
e
R
C
G
A
C
r
o
ti
c
a
p
a
C
C
G
A
l
a
n
r
e
t
x
E
t
n
a
t
s
n
o
c
e
m
it
C
G
A
=
C
G
A
C
*
K
0
7
Y
B
C
r
o
ti
c
a
p
a
c
s
s
a
p
y
b
e
g
a
t
s
n
i
a
g
t
u
p
n
I
F
p
6
5
>
925 um
VDD1
I
IN
GND
GND
GND GND
GND
GND
GND
GND
C
BY
C
BY
C
AGC
V
OUT
1992
19F
1250 um
V
DD2
V
1
D
D
V
0
.
7
V
2
D
D
V
0
.
7
I
N
I
A
m
5
T
A
0
4
-
.
p
m
e
T
g
n
it
a
r
e
p
O
o
5
2
1
o
t
C
o
C
T
S
5
6
-
.
p
m
e
T
e
g
a
r
o
t
S
o
0
5
1
o
t
C
o
C
Figure 3: Pin Layout
1
2
3
4
5
6
7
8
9
10
11
12
Table 2:ATA00501S2C Pin Description
Stresses in excess of the absolute ratings
may cause permanent damage. Functional
operation is not implied under these
conditions. Exposure to absolute ratings for
extended periods of time may adversely
affect reliability.
N
I
P
N
O
I
T
P
I
R
C
S
E
D
N
I
P
N
O
I
T
P
I
R
C
S
E
D
1
C
N
7
V
T
U
O
2
D
N
G
8
D
N
G
3
I
N
I
9
C
N
4
C
Y
B
0
1
V
D
D
5
D
N
G
1
1
D
N
G
6
C
C
G
A
2
1
C
N
PRELIMINARY DATA SHEET - Rev 1.5
08/2001
3
ATA00501
Table 4: Electrical Specifications
Notes:
(1) f=50MHz
(2) Measured with IIN below AGC Threshold. During AGC, input impedance will decrease propor-
tionally to I
IN
(3) Defined as the IIN where Transresistance has decreased by 50%.
(4) See note on Indirect Measurement of Optical Overload.
(5) See note on Measurement of Input Referred Noise Current.
(6) C
AGC
= 56 pF
(7) Parameter is guaranteed (not tested) by design and characterization data @ 51Mb/s, assuming
detector responsivity of 0.9
R
E
T
E
M
A
R
A
P
N
I
M
P
Y
T
X
A
M
T
I
N
U
)
A
n
0
0
5
<
c
d
I,
=
L
R
(
e
c
n
a
t
s
i
s
e
r
s
n
a
r
T
5
5
K
R
(
e
c
n
a
t
s
i
s
e
r
s
n
a
r
T
L
)
0
5
=
)
1
(
5
1
8
2
K
B
d
3
-
h
ti
w
d
n
a
B
0
5
0
7
z
H
M
e
c
n
a
t
s
i
s
e
R
t
u
p
n
I
)
2
(
0
0
5
1
e
c
n
a
t
s
i
s
e
R
t
u
p
t
u
O
0
3
0
5
0
6
e
g
a
tl
o
V
t
e
s
ff
O
t
u
p
n
I
5
.
1
6
.
1
9
.
1
s
tl
o
V
e
g
a
tl
o
V
t
e
s
ff
O
t
u
p
t
u
O
8
.
1
s
tl
o
V
tf
ir
D
e
g
a
tl
o
V
t
e
s
ff
O
1
/
V
m
o
C
I
(
d
l
o
h
s
e
r
h
T
C
G
A
N
I
)
)
3
(
5
0
1
A
d
a
o
lr
e
v
O
l
a
c
it
p
O
)
4
(
3
-
0
m
B
d
t
n
a
t
s
n
o
C
e
m
i
T
C
G
A
)
6
(
6
1
c
e
s
E
I
D
-
y
ti
v
it
i
s
n
e
S
l
a
c
it
p
O
)
7
(
3
4
-
m
B
d
P
F
Q
S
-
y
ti
v
it
i
s
n
e
S
l
a
c
it
p
O
)
7
(
1
4
-
m
B
d
t
n
e
r
r
u
C
y
l
p
p
u
S
0
3
5
4
A
m
e
g
n
a
R
e
g
a
tl
o
V
g
n
it
a
r
e
p
O
5
.
4
+
0
.
5
+
0
.
6
+
s
tl
o
V
e
g
n
a
R
e
r
u
t
a
r
e
p
m
e
T
g
n
it
a
r
e
p
O
0
4
-
5
8
o
C
m
m
W
W
W
W
PRELIMINARY DATA SHEET - Rev 1.5
08/2001
41.
ATA00501
Figure 4: ATA 00501D1C Typical Bonding
APPLICATION INFORMATION
Power Supplies and General Layout
Considerations
The ATA00501S2C may be operated from a positive
supply as low as + 4.5 V and as high as + 6.0 V.
Below + 4.5 V, bandwidth, overload and sensitivity
will degrade, while at + 6.0 V, bandwidth, overload
and sensitivity improve (see Bandwidth vs.
Temperature curves). Use of surface mount, low
inductance power supply bypass capacitors
(>=56pF) are essential for good high frequency and
low noise performance. The power supply bypass
capacitors should be mounted on or connected to a
good low inductance ground plane.
General Layout Considerations
Since the gain stages of the transimpedance
amplifier have an open loop bandwidth in excess
of 1.0 GHz, it is essential to maintain good high
frequency layout practices. To prevent oscillations,
a low inductance RF ground plane should be made
available for power supply bypassing. Traces that
can be made short should be made short, and the
utmost care should be taken to maintain very low
capacitance at the photodiode-TIA interface (I
IN
),
excess capacitance at this node will cause a
degradation in bandwidth and sensitivity (see
Bandwidth vs. CT curves).
PIN
56pF
56pF
V
DD
OUT
56pF
56pF
GND
VDD2
GND
GND
1992
V
OUT
GND
GND
C
BY
C
AGC
C
BY
GND
GND
GND
GND
I
IN
60C
V
DD
Figure 6: Bandwidth vs. Temperature
0.04
0.05
0.06
0.07
0.08
0.09
-40
10
60
85
V
DD
=
4.5 V
V
DD
=
5.0 V
V
DD
=
5.5 V
C
T
= 0.5 pF
Temperature (C)
Bandwidth
(GHz)
Figure 5: ATA 00501S2C External Circuit
1
2
3
4
5
6
7
8
9
10
11
12
I
IN
NC
GND
or
Neg.Supply
0.1F
Vout
NC
0.1F
V
DD
NC
56 pF
56 pF
PRELIMINARY DATA SHEET - Rev 1.5
08/2001
5
ATA00501
Note: All performance curves are typical @ TA =25 oC
unless otherwise noted.
IIN Connection
(Refer to the equivalent circuit diagram.) Bonding
the detector cathode to IIN (and thus drawing current
from the ATA00501) improves the dynamic range.
Although the detector may be used in the reverse
direction for input currents not exceeding 25
m
A, the
specifications for optical overload will not be met.
VOUT Connection
The output pad should be connected via a coupling
capacitor to the next stage of the receiver channel
(filter or decision circuits), as the output buffers are
not designed to drive a DC coupled 50 ohm load
(this would require an output bias current of
approximately 36 mA to maintain a quiescent 1.8
Volts across the output load). If VOUT is connected
to a high input impedance decision circuit (>500
ohms), then a coupling capacitor may not be
required, although caution should be exercised
since DC offsets of the photo detector/TIA
combination may cause clipping of subsequent gain
or decision circuits.
Figure 7: Bandwidth vs. CT
V
DD
= 4.5 V
V
DD
= 5.0 V
V
DD
= 5.5 V
90
80
70
60
50
40
30
0 0.2 0.4 0.6 0.8 1 1.2
B(3dB) A/ 2
Rf (C
in
+C
t
)
C
T
(pF)
Bandwidth
(MHz)
Figure 8: Transimpedance vs. I
IN
V
DD
= 5.5 V
V
DD
= 4.5 V
I
IN
(mA DC)
-2.1 -1.6 -1.1 -0.6 -0.1
25
22
19
16
13
10
7
4
1
I
IN
50
Transimpedance
(K
Ohm)
Figure 9: Bandwidth vs. I
IN
Figure 10: V
OUT
vs. I
IN
V
DD
= 4.5 V
V
DD
= 5.5 V
50
I
IN
- 2.1 - 1.6 - 1.1 - 0.6 - 0.1
1.44
1.24
1.04
.84
.64
.44
.24
.04
R
f
Bandwidth
(GHz)
I
IN
(mA DC)
V
DD
= 4.5 V
V
DD
= 5.5 V
Output Collapse
I
IN
v
OUT
Heavy AGC
Linear Region
(
o
3.4
3.2
3.0
2.9
2.7
2.5
2.4
2.2
2.0
1.9
1.7
1.5
1.4
1.2
1.0
0.8
0.7
0.5
0.3
0.2
0.0
R
f
-4 - 3 - 2 - 1
I
IN
(mA DC)
V
O
U
T
(
V
olt
s
)
PRELIMINARY DATA SHEET - Rev 1.5
08/2001
61.
ATA00501
V
DD
= 5.5 V
V
DD
=
5.0V
V
DD
=
4.5V
1.9
1.85
1.8
1.75
1.7
1.65
1.6
1.55
1.5
- 40 10 60
Temperature
o
C
Input
Of
fset
V
o
l
t
age
CBY Connection
The CBY pad must be connected via a low
inductance path to a surface mount capacitor of at
least 56pF (additional capacitance can be added in
parallel with the 56 pF or 220 pF capacitors to
improve low frequency response and noise
performance). Referring to the equivalent circuit
diagram and the typical bonding diagram, it is critical
that the connection from CBY to the bypass capacitor
use two bond wires for low inductance, since any
high frequency impedance at this node will be fed
back to the open loop amplifier with a resulting loss
of transimpedance bandwidth. Two pads are
provided for this purpose.
Sensitivity and Bandwidth
In order to guarantee sensitivity and bandwidth
performance, the TIA is subjected to a
comprehensive series of tests at the die sort level
(100% testing at 25 oC) to verify the DC parametric
performance and the high frequency performance
(i.e. adequate |S21|) of the amplifier. Acceptably high
|S21| of the internal gain stages will ensure low
amplifier input capacitance and hence low input
referred noise current. Transimpedance sensitivity
and bandwidth are then guaranteed by design and
correlation with RF and DC die sort test results.
Indirect Measurement of Optical Overload
Optical overload can be defined as the maximum
optical power above which the BER (bit error rate)
increases beyond 1 error in 1010 bits. The
ATA00501D1C is 100% tested at die sort by a DC
measurement which has excellent correlation with
an PRBS optical overload measurement. The
measurement consists of sinking a negative current
(see VOUT vs IIN figure) from the TIA and determining
the point of output voltage collapse. Also the input
node virtual ground during heavy AGC is checked to
verify that the linearity (i.e. pulse width distortion) of
the amplifier has not been compromised.
Measurement of Input Referred Noise Current
The Input Noise Current is directly related to
sensitivity . It can be defined as the output noise
voltage (Vout), with no input signal, (including a 30
MHz lowpass filter at the output of the TIA) divided by
the AC transresistance.
C
T
=1.0pF
CT
50
CT =0.5pF
7
6
5
4
3
2
1
- 0.1 1
10 100
1000
Frequency (MHz)
R
f
pA/
Hz
Figure 11: Input Offset Voltage vs. Temperature
Figure 12: Input Referred Noise Spectral Density
FIgure 13: Input Referred Noise vs Temperature
(dBm) = 10 LOG
6500
i
n
R
10
9
8
7
6
5
-40 0 40 80
0.5pF
25dB
Input Referred Noise Test Circuit
Temperature (
0
C)
TIA
V
DD =
4.5 V
V
DD
=5.5V
30
MHz
LPF
Input
Referred
Noise
in
(nA
RMS)
PRELIMINARY DATA SHEET - Rev 1.5
08/2001
7
ATA00501
AGC Capacitor
It is important to select an external AGC capacitor of
high quality and appropriate size. The ATA00501D1C
has an on-chip 70 KW resistor with a shunt 4 pF
capacitor to ground. Without external capacitance
the chip will provide an AGC time constant of 280
nS. For the best performance in a typical 51MB/s
SONET receiver, a minimum AGC capacitor of 56pF
is recommended. This will provide the minimum
amount of protection against pattern sensitivity and
pulse width distortion on repetitive data sequences
during high average optical power conditions.
Conservative design practices should be followed
when selecting an AGC capacitor, since unit to unit
variability of the internal time constant and various
data conditions can lead to data errors if the chosen
value is too small.
Phase Response
At frequencies below the 3dB bandwidth of the
device, the transimpedance phase response is
characteristic of a single pole transfer function (as
shown in the Phase vs Frequency curve). The output
impedance is essentially resistive up to 1000 MHz.
Figure 14: Phase (I
IN
to V
OUT
)
50 100 150
Frequency (MHz)
I
IN
0.5pF
V
OUT
180
200
220
240
R
f
Degrees
WARNING
ANADIGICS products are not intended for use in life support appliances, devices or systems. Use of an ANADIGICS
product in any such application without written consent is prohibited.
IMPORTANT NOTICE
ANADIGICS, Inc.
141 Mount Bethel Road
Warren, New Jersey 07059, U.S.A.
Tel: +1 (908) 668-5000
Fax: +1 (908) 668-5132
URL: http://www.anadigics.com
E-mail: Mktg@anadigics.com
ANADIGICS, Inc. reserves the right to make changes to its products or to discontinue any product at any time without
notice. The product specifications contained in Advanced Product Information sheets and Preliminary Data Sheets are
subject to change prior to a products formal introduction. Information in Data Sheets have been carefully checked and are
assumed to be reliable; however, ANADIGICS assumes no responsibilities for inaccuracies. ANADIGICS strongly urges
customers to verify that the information they are using is current before placing orders.
PRELIMINARY DATA SHEET - REV 1.5
08/2001
8
ATA00501
ORDERING INFORMATION
PACKAGE OUTLINE
0.024 (.61)
0.018 (.46)
0.018 (.460)
0.012 (.300)
0.165 (4.19)
0.152 (3.86)
0.245 (6.22)
0.230 (5.84)
0.011 (.28)
0.007 (.18)
0.035 (.89)
0.020 (.51)
0.015 (.38)
0.000 (0.00)
0.032 BSC
(0.81)
4X 0.023X45
0.021X45
4 Sides
7
0
o
1
2
3
4
5
6
7
8
9
10
11
12
0.047 (1.19)
0.032 (0.81)
0.065 (1.65)
0.055 (1.40)
0.000 (0.00)
0.020 (.51)
Figure 15: ATA00501S2C Package Pin-Out (S2C)
Dimensions in Inches (Millimeters)
R
E
B
M
U
N
T
R
A
P
N
O
I
T
P
O
E
G
A
K
C
A
P
N
O
I
T
P
I
R
C
S
E
D
E
G
A
K
C
A
P
C
1
D
1
0
5
0
0
A
T
A
C
1
D
e
i
D
C
2
S
1
0
5
0
0
A
T
A
C
2
S
e
g
a
k
c
a
P
P
F
Q
S
d
e
d
i
S
4
n
i
P
2
1
PDF 
ZIP