1
PS8320D 10/14/04
SDRAM12
SDRAM2
SDRAM1
SDRAM0
BUF_IN
SDATA
SCLK
SDRAM3
I2C
I/O
V
SS
V
DD
S
DRAM
1
S
DRAM
3
V
SS
S
DRAM
2
S
DRAM
4
S
DRAM
5
S
DRAM
12
V
DD
S
DATA
V
DD
S
DRAM
10
V
SS
S
DRAM
9
S
DRAM
8
V
SS
V
DD
S
DRAM
7
S
DRAM
6
V
SS
V
SS
S
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
DD
S
DRAM
0
BUF_IN
V
DD
S
DRAM
11
Pin Configuration
Block Diagram
Description
The PI6C184 is a high-speed low-noise 1-13 non-inverting
buffer designed for SDRAM clock buffer applications.
This buffer is intended to be used with the PI6C104 clock generator
for Intel Architecture for both desktop and mobile systems.
At power-up, all SDRAM outputs are enabled and active. The I
2
C
Serial control may be used to individually activate/deactivate any
of the 13 output drivers.
Note:
Purchase of I
2
C components from Pericom conveys a license to
use them in an I
2
C system as defined by Philips.
Features
High-speed, low-noise, non-inverting, 1-13 buffer
Supports up to four SDRAM DIMMs
Low skew (< 250ps) between any two output clocks
I
2
C Serial Configuration interface
Multiple V
DD
, V
SS
pins for noise reduction
3.3V power supply voltage
Separate Hi-Z pin for testing
Packaging (Pb-free & Green available):
- 28-pin SSOP (H)
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Precision 1-13 Clock Buffer
PI6C184
PI6C184
Precision 1-13 Clock Buffer
2
PS8320D 10/14/04
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Pin Description
I
2
C Address Assignment
Serial Configuration Map
Byte0: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Note:
Inactive means outputs are held LOW and are
disabled from switching
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PI6C184
Precision 1-13 Clock Buffer
3
PS8320D 10/14/04
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Byte1: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Byte2: Optional Register for Possible Future
Requirements (1 = enable, 0 = disable)
2-Wire I
2
C Control
The I
2
C interface permits individual enable/disable of each clock
output and test mode enable.
The PI6C184 is a slave receiver device. It can not be read back. Sub
addressing is not supported. All preceding bytes must be sent in
order to change one of the control bytes.
Every bite put on the SDATA line must be 8-bits long (MSB first),
followed by an acknowledge bit generated by the receiving device.
During normal data transfers SDATA changes only when SCLK is
LOW. Exceptions: A HIGH-to-LOW transition on SDATA while
SCLK is HIGH indicates a "start" condition. A LOW-to-HIGH
transition on SDATA while SCLK is HIGH is a "stop" condition
and indicates the end of a data transfer cycle.
Each data transfer is initiated with a start condition and ended with
a stop condition. The first byte after a start condition is always a
7-bit address byte followed by a read/write bit. (HIGH = read from
addressed device, LOW= write to addressed device). If the device's
own address is detected, PI6C184 generates an acknowledge by
pulling SDATA line LOW during ninth clock pulse, then accepts
the following data bytes until another start or stop condition is
detected.
Following acknowledgement of the address byte (D2), two more
bytes must be sent:
1. "Command Code" byte, and
2. "Byte Count" byte.
Although the data bits on these two bytes are "don't care," they
must be sent and acknowledged.
Storage Temperature ............................................... 65C to +150C
Ambient Temperature with Power Applied ................. 0C to +70C
3.3V Supply Voltage to Ground Potential .................. 0.5V to +4.6V
DC Input Voltage ....................................................... 0.5V to +4.6V
Note:
Stresses greater than those listed under MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
Supply Current
(V
DD
= +3.465V, C
LOAD
= Max.)
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3
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
PI6C184
Precision 1-13 Clock Buffer
4
PS8320D 10/14/04
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SDRAM Clock Buffer Operating Specification
DC Operating Specifications
(V
DD
= +3.3V 5%, T
A
= 0C - 70C)
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4
AC Timing
Symbol
Parameter
66 MHz
100 MHz
Units
Min.
Max.
Min.
Max.
T
DSKP
SDRAM CLK period
15.0
15.5
10.0
10.5
ns
T
SDKH
SDRAM CLK high time
5.6
3.3
ns
T
SDKL
SDRAM CLK low time
5.3
3.1
ns
T
SDRISE
SDRAM CLK rise time
1.5
4.0
1.5
4.0
V/ns
T
SDFALL
SDRAM CLK fall time
1.5
4.0
1.5
4.0
V/ns
t
PLH
SDRAM Buffer LH prop delay
1.0
5.5
1.0
5.0
ns
t
PHL
SDRAM Buffer HL prop delay
1.0
5.5
1.0
5.0
ns
DutyCycle Measured at 1.5V
45
55
45
55
%
tSDSKW
SDRAM Output to Output Skew
250
250
ps
PI6C184
Precision 1-13 Clock Buffer
5
PS8320D 10/14/04
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Figure 1. Clock Waveforms
Notes:
1. Maximum rise/fall times are guaranteed at maximum specified load.
2. Minimum rise/fall times are guaranteed at minimum specified load.
3. Rise/fall times are specified with pure capacitive load as shown.
Testing is done with an additional 500
resistor in parallel.
Minimum and Maximum Expected Capacitive Loads
Design Guidelines to Reduce EMI
1. Place series resistors and CI capacitors as close as possible to the respective clock pins. Typical value
for CI is 10pF. Series resistor value can be increased to reduce EMI provided that the rise and fall time
are still within the specified values.
2. Minimize the number of "vias" of the clock traces.
3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing
clock traces from plane to plane (refer to rule #2).
4. Position clock signals away from signals that go to any cables or any external connectors.
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1.5V
1.5V
t
phl
t
plh
1.5V
1.5V
Input
Waveform
Output
Waveform
Output
Buffer
Test
Point
2.4
1.5
0.4
tSDKH
tSDKP
3.3V
Clocking
Interface
(TTL)
tSDKL
t
SDFALL
t
SDRISE
Test Load
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