4-Bit Micro-controller With LCD Driver

Features

Low power dissipation
Powerful instruction set (148 instructions)

Binary addition, subtraction, BCD
adjustment, logical operation in direct
addressing mode and index
addressing mode
Single-bit manipulation (set, reset, decision
for branch)
Various conditional branches
16 working registers and manipulation
LCD driver data transfer
Look-up table
Programmable option
System clock selection

Memory capacity

Instruction ROM capacity 2048 x 16 bits
Index ROM capacity 256 x 8 bits
Internal RAM capacity 256 x 4 bits
(low-address 128 nibbles can be accessed
by direct addressing, full-range 256 nibbles
can be accessed by index addressing)

Input/output ports

Port IOA 4 pins (with internal pull-low,
chattering clock, MUX with CX, RR, RT, RH/
SEG 37~40 by mask option)
Port IOB 4 pins (MUX with ELC, ELP, BZB,
BZ/SEG41, 42 by mask option)
Port IOC 4 pins (with internal pull-low,
low-level hold, chattering clock, MUX option
with AN1~4 by mask option)
Port IOD 4 pins (MUX with PWM1,
2/SEG33~36 by mask option)

8-level subroutine nesting
Interrupt function

External factor 2 (INT pin & port IOA, IOC
input)
Internal factor 4 (predivider, 2 timers & RFC)

Built-in EL-light driver, alarm, frequency or

melody generator (MUX with IOB/ SEG41, 42)

Built-in R to F converter circuit (MUX with

IOA/SEG37~40)

Built-in comparator, 6/8-bit PWM output, 4-bit

D/A converter, low-battery detector; this
structure can be used as a 4/6/8-bit full range
ADC

Port PWM 2 pins (MUX with SEG35, 36)
Port ADC 4 pins (MUX with IOC)

2 6-bit programmable timers with programmable

clock source

Watchdog timer
LCD/LED driver output

42 LCD/LED driver outputs (up to 168 LCD
segments are drivable)
Mask option is used to select static, 1/2 bias
1/2 duty, 1/2 bias 1/3 duty, 1/2 bias 1/4 duty,
1/3 bias 1/3 duty and 1/3 bias 1/4 duty drive
modes of the LCD panel
Mask option is used to select DC output,
and static, 1/2 duty, 1/3 duty and 1/4 duty
drive modes of the LED panel
Mask option is used to select SEG28~32 as
P open-drain DC outputs
Single instruction stops all segments that
are either in LCD or LED

Built-in voltage doubler, halver, tripler charge

pump circuit

Dual clock operation
HALT function
Stop function

General Description

APU428 is an embedded high-performance 4-bit

microcomputer with an LCD/LED driver. It contains
all the necessary functions in a single chip: 4-bit
parallel processing ALU, ROM, RAM, I/O ports, timer,
clock generator, dual clock, ADC, RFC, alarm,
EL-light, LCD driver, look-up table and watchdog
timer. The instruction set consists of 148 instructions
which include nibble operation, manipulation,
various conditional branch instructions and LCD

data transfer instructions which are powerful and
easy to follow.

The HALT function stops any internal operations other
than the oscillator, divider and LCD driver in order to
minimize the power dissipation.

The stop function stops all clocks in the chip.

Preliminary

1 Ver. 0.0

APU428

Block Diagram

LC D D river

C O M 1 4

S E G 1 S E G 42

V D D 1 3

S egm entP LA

4-B itD ata B us

D ata R A M
(Index (L))

128 x 4 B its

A LU

6-B itP reset

T im er

Instruction

D ecoder

C ontrol

C ircuit

P R O M

2048 x 16-B it

8-Levels S tack

SET

C U P 1

C U P 2

11-B itP rogram

C ounter

Index

M ask R O M

128 x 8 B its

F requency

G enerator

P re-D ivider

W atchdog

T im er

O scillator

I
N

Index S R A M

(H )

128 x 4 B its

S E G 33 36

D -P ort

P W M

D 1 D 4

C -P ort

A D C

C 1 C 4

S E G 37 40

A -P ort

R F C

A 1 A 4

S E G 41 42

B -P ort

LightA larm

B 1 B 4

Preliminary

2 Ver. 0.0

APU428

Pad Assignment

Pad Coordinates

Pad No.

Pad Name

Pad No.

Pad Name

SEG1

560

SEG34

1480

2265

SEG2

675

SEG35

1365

2265

SEG3

790

SEG36

1250

2265

SEG4

905

SEG37

1135

2265

SEG5

1020

SEG38

1020

2265

SEG6

1135

SEG39

905

2265

SEG7

1250

SEG40

790

2265

SEG8

1365

SEG41

675

2265

SEG9

1480

SEG42

560

2265

SEG10

1595

IOB3

445

2265

SEG11

1710

IOB4

330

2265

SEG12

1840

GND

200

2265

SEG13

1970

160

VDD

2175

SEG14

1970

290

CFIN

2045

SEG15

1970

420

CFOUT

1915

SEG16

1970

535

XTIN

1800

SEG17

1970

650

XTOUT

1685

SEG18

1970

765

TESTA

1570

SEG19

1970

880

RESET

1455

Preliminary

3 Ver. 0.0

APU428

APU428

Pad No.

Pad Name

Pad No.

Pad Name

SEG20

1970

995

INT

1340

SEG21

1970

1110

IOM1

1225

SEG22

1970

1225

IOM2

1110

SEG23

1970

1340

IOM3

995

SEG24

1970

1455

IOM4

880

SEG25

1970

1570

VDD1

765

SEG26

1970

1685

VDD2

650

SEG27

1970

1800

VDD3

535

SEG28

1970

1915

CUP1

420

SEG29

1970

2045

CUP2

290

SEG30

1970

2175

COM1

160

SEG31

1840

2265

COM2

200

SEG32

1710

2265

COM3

330

SEG33

1595

2265

COM4

445

Chip size: 84.65 x 96.45 mil

Pad Descriptions

Pad Name

I/O

Description

BAK

Positive back-up voltage.
In Li mode, connects a 0.1u capacitance to GND.

VDD1
VDD2
VDD3

LCD drives the voltage and positive supply voltage.
While in Ag mode, connects +1.5V to V

DD1

While in Li/ExtV mode, connects +3.0V to

VDD2

RESET

Input pin from LSI reset request signal.
Internal pull-down resistor.

INT

Input pin for external INT request signal.
Falling or rising edge triggered by mask option.
Internal pull-down or pull-up resistor or none is selected by mask option.

TESTA

Test signal input pin.

CUP1
CUP2

Switching pins for supplying the LCD driving voltage to the VDD1, 2, 3 pins.
Connects the CUP1 and CUP2 pins with nonpolarized electrolytic capacitor if
1/2 or 1/3 bias mode has been selected.
In the static mode, these pins should be open.

XIN
XOUT

Time-based counter frequency (clock-specified, LCD alternating frequency,
alarm signal frequency) or system clock oscillation. 32kHz crystal oscillator.
Oscillation stops at the execution of STOP instruction.

CFIN
CFOUT

System clock oscillation.
Connected with ceramic resonator.
Connected with RC oscillation circuit.
Oscillation stops at the execution of STOP or SLOW instruction.

COM1~4

Output pins for supplying voltage to drive the common pins of the LCD or LED
panel.

SEG1~42

Output pins for LCD or LED panel segment.

IOA1~4

I/O

Input/Output port A can use software to define the internal pull-low resistor and
chattering clock in order to reduce input bounce and generate interrupt.
This port shares pins with SEG37~40 and is set by mask option.
This port also shares pins with CC, RR, RT and RH, and is set by mask option.

Preliminary

4 Ver. 0.0

APU428

Pad Name

I/O

Description

IOB1~4

I/O

I/O Input/Output port B.
IOB1, 2 shares pins with SEG41, 42, or ELC, ELP and is set by mask option.
IOB3, 4 shares pins with BZ, BZB and is set by mask option.

IOC1~4

I/O

I/O Input/Output port C can use software to define the internal pull-low/
low-level hold resistor and chattering clock in order to reduce input bounce and
generate interrupt. This port shares pins with AN1-4 and is set by mask option.

IOD1~4

I/O

Input / Output port D.
This port shares pins with SEG33~36 and is set by mask option.
IOD3,4 shares pins with PWM1,2 and is set by mask option.

RFC CC
RR
RT
RH

O
O
O

1 input pin and 3 output pins for RFC application.
This port shares pins with SEG37~40 and is set by mask option.
This port shares pins with IOA1~4 and is set by mask option.

EL ELC
ELP

O
O

Output port for the EL-light.
These ports share pins with SEG41, 42 and are set by mask option.
These ports share pins with IOB1, 2 and are set by mask option.

ALM BZB
Z

O
O

Output port for alarm, frequency or melody generator.
This port shares pins with IOB3,4 and is set by mask option.

GND

Negative supply voltage.

Preliminary

5 Ver. 0.0

APU428

Absolute Maximum Rating

Ta = 0 to 70 GND=0V

Name

Symbol

Rating

Unit

DD1

-0.3 ~ +5.5

DD2

-0.3 ~ +5.5

Maximum Supply Voltage

DD3

-0.3 ~ +8.5

Maximum Input Voltage

-0.3 to V

DD1/2

+0.3

OUT1

-0.3 to V

DD1/2

+0.3

Maximum Output Voltage

OUT2

-0.3 to V

DD3

+0.3

Maximum Operating Temperature

OPG

0 to +70

Maximum Storage Temperature

STG

-25 to +125

Allowable operating conditions

Ta = 0 to 70 GND=0V

Name

Symbol

Condition

Min.

Max.

Unit

DD1

1.2

5.25

DD2

2.4

5.25

Supply Voltage

DD3

2.4

8.0

Oscillator Start-up Voltage

DDB

Crystal Mode

1.3

Oscillator Sustain Voltage

DDB

Crystal Mode

1.2

Supply Voltage

DD1

Ag Mode

1.2

1.65

Supply Voltage

DD2

EXT-V, Li Mode

2.4

5.25

Input H Voltage

IH1

DD1-0.7

DD1+0.7

Input L Voltage

IL1

Ag Battery Mode

-0.7

0.7

Input H Voltage

IH2

DD2-0.7

DD2+0.7

Input L Voltage

IL2

Li Battery Mode

-0.7

0.7

Input H Voltage

IH3

0.8V

DD1

Input L Voltage

IL3

OSCIN at Ag Battery Mode

0.2V

DD1

Input H Voltage

IH4

0.8V

DD2

Input L Voltage

IL4

OSCIN at Li Battery Mode

0.2V

DD2

Input H Voltage

IH5

0.8V

DD2

Input L Voltage

IL5

CFIN at Li Battery or EXT-V Mode

0.2V

DD2

Input H Voltage

IH6

0.8V

DDO

Input L Voltage

IL6

RC Mode

0.2V

DDO

OPG1

Crystal Mode

3580

kHz

OPG2

External RC Mode

1000

kHz

Operating Freq.

OPG3

CF Mode

1000

3580

kHz

Preliminary

6 Ver. 0.0

APU428

Electrical Characteristics

Ta=0 to 70

Input resistance

Name

Symbol

Condition

Min.

Typ.

Max.

Unit

IIH1

=0.2V

DD1

, #1

100

IIH2

=0.2V

DD2

, #2

100

L -Level Hold t

(IOC)

IIH3

=0.2V

DD2

, #3

MSD1

DD1

, #1

200

500

1000

MSD2

DD2

, #2

200

500

1000

IOC/IOA Pull-Down t

MSD3

DD3

, #3

100

250

500

INTU1

DD1

, #1

200

500

1000

INTU2

DD2

, #2

200

500

1000

INT Pull-Up t

INTU3

DD3

, #3

100

250

500

INTD1

=GND, #1

200

500

1000

INTD2

=GND, #2

200

500

1000

INT Pull-Down t

INTD3

=GND, #3

100

250

500

RES1

=GND or V

DD1

, #1

RES2

=GND or V

DD2

, #2

RES Pull-Down t

RES3

=GND or V

DD2

, #3

Note: #1: V

DD1

= 1.2V ( Ag ), #2: V

DD2

= 2.4V ( Li ), #3: V

DD2

= 4V (Ext-V).

DC output characteristics

Name

Symbol

Condition

For

Min.

Typ.

Max.

Unit

OH1a

=-10 A, #1

0.8

0.9

1.0

OH2 a

=-50 A, #2

1.5

1.8

2.1

Output H Voltage

OH3 a

=-200 A, #3

2.5

3.5

OL1 a

=20 A, #1

0.2

0.3

0.4

OL2 a

=100 A, #2

0.3

0.6

0.9

Output L Voltage

OL3 a

=400 A, #3

SEG1~
SEG32

0.5

1.0

1.5

OH1c

=-200 A, #1

0.8

0.9

1.0

OH2c

=-1mA, #2

1.5

1.8

2.1

Output H Voltage

OH3c

=-3mA, #3

2.5

3.5

OL1c

=400 A, #1

0.2

0.3

0.4

OL2c

=2mA, #2

0.3

0.6

0.9

Output L Voltage

OL3c

=6mA, #3

SEG33~

SEG42,

IOB3~4,

IOC-n

0.5

1.0

1.5

Note: #1: V

DD1

= 1.2V ( Ag ), #2: V

DD2

= 2.4V ( Li ), #3: V

DD2

= 4V (Ext-V).

Preliminary

7 Ver. 0.0

APU428

Segment driver output characteristics

Name

Symbol

Condition

For

Min.

Typ.

Max.

Unit

Static display mode

OH1d

=-1 A, #1

1.0

OH2d

=-1 A, #2

2.2

Output H Voltage

OH3d

=-1 A, #3

3.8

OL1d

=1 A, #1

0.2

OL2d

=1 A, #2

0.2

Output L Voltage

OL3d

=1 A, #3

SEG-n

0.2

OH1e

=-10 A, #1

1.0

OH2e

=-10 A, #2

2.2

Output H Voltage

OH3e

=-10 A, #3

3.8

OL1e

=10 A, #1

0.2

OL2e

=10 A, #2

0.2

Output L Voltage

OL3e

=10 A, #3

COM-n

0.2

1/2 bias display mode

OH12f

=-1 A, #1, #2

2.2

Output H Voltage

OH3f

=-1 A, #3

3.8

OL12f

=1 A, #1, #2

0.2

Output L Voltage

OL3f

=1 A, #3

SEG-n

0.2

OH12g

=-10 A, #1, #2

2.2

Output H Voltage

OH3g

=-10 A, #3

3.8

OM12g

OI/H

= 10 A, #1, #2

1.0

1.4

Output M Voltage

OM3g

OI/H

= 10 A, #3

1.8

2.2

OL12g

=10 A, #1, #2

0.2

Output L Voltage

OL3g

=10 A, #3

COM-n

0.2

1/3 bias display mode

OH12i

=-1 A, #1, #2

3.4

Output H Voltage

OH3i

=-1 A, #3

5.8

OM12i

OI/H

= 10 A, #1, #2

1.0

1.4

Output M1 Voltage

OM13i

OI/H

= 10 A, #3

1.8

2.2

OM22i

OI/H

= 10 A, #1, #2

2.2

2.6

Output M2 Voltage

OM23i

OI/H

= 10 A, #3

3.8

4.2

OL12i

=1 A, #1, #2

0.2

Output L Voltage

OL3i

=1 A, #3

SEG-n

0.2

OH12j

=-10 A, #1, #2

3.4

Output H Voltage

OH3j

=-10 A, #3

5.8

OM12j

OI/H

= 10 A, #1, #2

1.0

1.4

Output M1 Voltage

OM13j

OI/H

= 10 A, #3

1.8

2.2

OM22j

OI/H

= 10 A, #1, #2

2.2

2.6

Output M2 Voltage

OM23j

OI/H

= 10 A, #3

3.8

4.2

OL12j

=10 A, #1, #2

0.2

Output L Voltage

OL3j

=10 A, #3

COM-n

0.2

Note: #1: V

DD1

= 1.2V ( Ag ), #2: V

DD2

= 2.4V ( Li ), #3: V

DD2

= 4V (Ext-V).

Preliminary

8 Ver. 0.0

APU428

Functional Description

Index SRAM
The 256 X 4 bits index SRAM is used for applications that need more SRAM or need to load addresses by
operation, and data SRAM is included at a lower-half address in the index SRAM.

Index ROM
The 256 X 8 bits index ROM can be used in the 4-bit or 8-bit mode.

I/O ports
The IOA port can be selected by software separately as input or output. It can also be selected with/without
internal pull-low and different chattering clocks for a HALT release / interrupt trigger in order to reduce the
input bounce for the key scan:

PH6: 512Hz, PH8: 128Hz, PH10: 32Hz.

The pull-low of IOA will be masked off for those pins defined as output pins:

The IOA port can be used as a pseudo serial output port.

The IOB port can be selected by software separately as input or output.

Th e IOC port can be selected by software separately as input or output, and with/without internal pull-low and
different chattering clocks for a HALT release /interrupt trigger in order to reduce the bounce of the key scan.

The pull-low of the IOC will be masked off for those pins defined as output pins.

The IOD port can be selected by software separately as input or output.

The IOD port can be used as a pseudo serial output port.

The initial state of all I/O ports is the standard input state, and IOA and C have pull-low.

Before setting the I/O ports from input to output, execute the output function first to ensure the output state.

Resistor to frequency converter

We use an RC oscillation circuit and a 16-bit counter to calculate the relative resistance of temperature and
humidity sensor. The diagram is shown below:

ELP

RHM

Rref

ENX

EHM

FIN

ERR

ENX

FIN

Freq.

16-Bit Counter

4-Bit Data Bus

Freq.

TMS

PH9

MRF

Timer & R/F

Controller

RTP

There are 2 methods for measuring the input frequency. First, set FIN (i.e. CX) as the clock input and use
timer 2 or the software directly as interval control. Second, if the FIN (CX) frequency is too low (either because
of a poor resolution for a fixed interval or a longer interval for better resolution but a longer read-out rate,
ex.10 seconds per read-out), you can switch the measure mode to set FIN (CX) as the interval control. It will

Preliminary

9 Ver. 0.0

APU428

enable the counter from the first FIN rising edge to the next rising edge, then will generate an interrupt. It may
also use FREQ (internal frequency generator output) as clock input, hence counting the CX interval. For
measuring the resistor value of the temperature and humidity sensor, we must first measure the frequency of
Rref, then the frequency of Sensor:

Fref= K / Rref CX and
Fsensor= K / Rsensor CX, hence
Rsensor = Rref * Freq / Fsensor.
The CX input can be used as a clock counter.

Analog-to-Digital converter

The diagram is shown below:

LHCP

ENCP

ADF1

ADF2

ADF3

ADF4

AN1

AN2

AN3

Analog Switch

LBR

Low Battery

Reference

4-Bit Ladder

DAC

ENLBR

ENDAC
MDA

DAC

AN4

0 1 2 3

MPW1

MPW2

6 / 8-Bit

PWM DAC

0 1 2 3 4 5 6 7

6 / 8-Bit

PWM DAC

0 1 2 3 4 5 6 7

MPW1

MPW2

The use of these blocks is illustrated below:

Comparator: Sets negative input as AN4, compare with AN1, 2, 3.
4-bit ADC: Sets negative input as internal 4-bit DAC, positive input as AN4, software control for AN1, 2, 3,
4 analog value archive.
Low battery detector: Sets negative input as internal 4-bit DAC, positive input as LBR (low battery
reference). If the DAC level is lower than LBR, it means there is a low-battery condition.
PWM DAC output: With an external RC network, 6-bit or 8-bit PWM DAC can be used.
6-bit/ 8-bit ADC: Sets negative input as AN4, connects from PWM with an external RC network. You can
get analog value from AN1, 2, 3.
Supply voltage measurement: Sets negative input as AN4, connects from PWM with an external RC
network, positive input is LBR. If comparative data is N, the supply voltage is LBR (about 1.26V) * 255 / N.

Note: The internal 4-bit DAC level is 1/32 V

for 0, 3/32 for 1, 29/32 for E and 31/32 for F. The level of 6-bit

PWM is 0/63, 1/63, 62/63 and 63/63, and the level of 8-bit PWM is 0/255, 1/255, 254/255 and 255/255.

Preliminary

10 Ver. 0.0

APU428

An example of ADC timing is shown below:

TCK4

SW (LBR/AN4)

SW (AN4/DAC)

En LBR

En DAC

LHCP

ENCP

SAD 1Bh

LBR

DAC

SAD 28h

LBR

DAC

SAD 11h

SAD 20h

AN4

DAC

AN4

DAC

T1h

Note: Power Supply = 1.2V T1h needs 5ms

Power Supply = 2.4V T1h needs 10 s

EL-light
Sets ELC and ELP clock and duty cycle using ELC X instruction, then turn on and off ELC and ELP output by
SF X and RF X instruction. With external transistor, diode, inductor and resistor, we can pump the EL panel to
AC 100~250V.

LIT

ELP

ELC

ELP

EL-plane

When the EL-light is turned on, the ELC will turn on before ELP, but when the EL-light is off, the ELP and ELC
will turn off after the next falling edge of ELC in order to make sure no voltage is left on the EL plane.

Timer
The 6-bit programmable timer can select PH3/PH9/PH15/FREQ (Timer 2 can also select PH5/PH7/PH11/
PH13 by TM2X instruction) as the clock source. When it underflows, HALT release signals are generated.

Preliminary

11 Ver. 0.0

APU428

Predivider
The predivider is a 15-sage counter that uses PH0 as clock source. The output of T-FF is changed when the
input signal is changed from H to L. PH11~15 are reset to L when PLC 100H instruction is executed,
power-on reset or external reset is used. When PH14 is changed from H to L, the HALT release signal is
generated.

Alarm/frequency/melody
There is an 8-bit programmable counter and an 8-bit envelope control for alarm, frequency or melody output
from BZ/BZB.

The frequency counter can use software to select 1/2 duty, 1/3 duty,1/4 duty drive modes.

Frequency

1/2 Duty Frequency

1/3 Duty Frequency

1/4 Duty Frequency

INT function
The INT pin can be selected by mask option as pull-high/pull-low or none, and as a rising edge/falling edge
trigger.

Watchdog Timer
The watchdog timer automatically generates a device reset when it overflows. The interval of overflow is
8/64/512 x PH10 (set by mask option). You can use software to enable and disable this function. The
watchdog enable flag will be disabled by power on reset or reset pin reset condition, but cannot be disabled
by watchdog reset itself.

HALT function
The HALT instruction disables all clocks except the predivider, timer, frequency counter, PWM, EL-light
generator and chattering clock in order to minimize the operating current.

STOP function
The STOP instruction disables all clocks to minimize the standby current, so only two external factors (INT,
IOA/IOC) can release the stop condition.

Instruction Table

Instruction

Machine Code

Function

Flag/Remark

NOP

0000 0000 0000 0000

No Operation

LCT Lz, Ry

0000 001Z ZZZZ YYYY

{ 7SEG

Ry}

LCB Lz, Ry

0000 010Z ZZZZ YYYY

{ 7SEG

Ry}

LCP Lz, Ry

0000 011Z ZZZZ YYYY

Ry , AC

LCD Lz, @HL

0000 100Z ZZZZ 0000

T@HL

OPA Rx

0000 1010 0XXX XXXX

Port(A)

OPAS Rx, D

0000 1011 DXXX XXXX

A1, 2, 3, 4

Rx0, Rx1, D, Pulse

OPB Rx

0000 1100 0XXX XXXX

Port(B)

Preliminary

12 Ver. 0.0

APU428

Instruction

Machine Code

Function

Flag/Remark

OPC Rx

0000 1101 0XXX XXXX

Port(C)

OPD Rx

0000 1110 0XXX XXXX

Port(D)

OPDS Rx

0000 1111 DXXX XXXX

D1, 2, 3, 4

Rx0, Rx1, D, Pulse

FRQ Rx, D

0001 00DD 0XXX XXXX

FREQ

Rx, AC

DD=00: 1/4 Duty
DD=01: 1/3 Duty
DD=10: 1/2 Duty

FRQ D,@HL

0001 01DD 0000 0000

FREQ

T@HL

FRQX D,X

0001 10DD XXXX XXXX FREQ

MVL Rx

0001 1100 0XXX XXXX

MVH Rx

0001 1101 0XXX XXXX

MPW1 Rx

0001 1110 0XXX XXXX

PWM1

Rx , AC

MPW2 Rx

0001 1111 0XXX XXXX

PWM2

Rx , AC

ADC Rx

0010 0000 0XXX XXXX

Rx+AC+CF

ADC @HL

0010 0000 1000 0000

@HL+AC+CF

ADC* Rx

0010 0001 0XXX XXXX

AC, Rx

Rx+AC+CF

ADC* @HL

0010 0001 1000 0000

AC, @HL

@HL+AC+CF

SBC Rx

0010 0010 0XXX XXXX

Rx+ACB+CF

SBC @HL

0010 0010 1000 0000

@HL+ACB+CF

SBC* Rx

0010 0011 0XXX XXXX

AC, Rx

Rx+ACB+CF

SBC* @HL

0010 0011 1000 0000

AC, @HL

@HL+ACB+CF

ADD Rx

0010 0100 0XXX XXXX

Rx+AC

ADD @HL

0010 0100 1000 0000

@HL+AC

ADD* Rx

0010 0101 0XXX XXXX

AC,Rx

Rx+AC

ADD* @HL

0010 0101 1000 0000

AC, @HL

@HL+AC

SUB Rx

0010 0110 0XXX XXXX

Rx+ACB+1

SUB @HL

0010 0110 1000 0000

@HL+ACB+1

SUB* Rx

0010 0111 0XXX XXXX

AC, Rx

Rx+ACB+1

SUB* @HL

0010 0111 1000 0000

AC,@HL

@HL+ACB+1

ADN Rx

0010 1000 0XXX XXXX

Rx+AC

ADN @HL

0010 1000 1000 0000

@HL+AC

ADN* Rx

0010 1001 0XXX XXXX

AC, Rx

Rx+AC

ADN* @HL

0010 1001 1000 0000

AC,@HL

@HL+AC

AND Rx

0010 1010 0XXX XXXX

Rx AND AC

AND @HL

0010 1010 1000 0000

@HL AND AC

AND* Rx

0010 1011 0XXX XXXX

AC, Rx

Rx AND AC

AND* @HL

0010 1011 1000 0000

AC,@HL

@HL AND AC

EOR Rx

0010 1100 0XXX XXXX

Rx EXOR AC

EOR @HL

0010 1100 1000 0000

@HL EXOR AC

EOR* Rx

0010 1101 0XXX XXXX

AC, Rx

Rx EXOR AC

EOR* @HL

0010 1101 1000 0000

AC,@HL

@HL EXOR AC

Preliminary

13 Ver. 0.0

APU428

Instruction

Machine Code

Function

Flag/Remark

OR Rx

0010 1110 0XXX XXXX

Rx OR AC

OR @HL

0010 1110 1000 0000

@HL OR AC

OR* Rx

0010 1111 0XXX XXXX

AC, Rx

Rx OR AC

OR* @HL

0010 1111 1000 0000

AC,@HL

@HL OR AC

ADCI Ry,D

0011 0000 DDDD YYYY AC

Ry+D+CF CF

ADCI* Ry,D

0011 0001 DDDD YYYY AC, Ry

Ry+D+CF

SBCI Ry,D

0011 0010 DDDD YYYY AC

Ry+DB+CF

SBCI* Ry,D

0011 0011 DDDD YYYY AC, Ry

Ry+DB+CF

ADDI Ry,D

0011 0100 DDDD YYYY AC

Ry+D

ADDI* Ry,D

0011 0101 DDDD YYYY AC, Ry

Ry+D

SUBI Ry,D

0011 0110 DDDD YYYY AC

Ry+DB+1

SUBI* Ry,D

0011 0111 DDDD YYYY AC, Ry

Ry+DB+1

ADNI Ry,D

0011 1000 DDDD YYYY AC

Ry+D

ADNI* Ry,D

0011 1001 DDDD YYYY AC, Ry

Ry+D

ANDI Ry,D

0011 1010 DDDD YYYY AC

Ry AND D

ANDI* Ry,D

0011 1011 DDDD YYYY AC, Ry

Ry AND D

EORI Ry,D

0011 1100 DDDD YYYY AC

Ry EXOR D

EORI* Ry,D

0011 1101 DDDD YYYY AC, Ry

Ry EXOR D

ORI Ry,D

0011 1110 DDDD YYYY AC

Ry OR D

ORI* Ry,D

0011 1111 DDDD YYYY AC, Ry

Ry OR D

INC* Rx

0100 0000 0XXX XXXX

AC, Rx

Rx+1

INC* @HL

0100 0000 1000 0000

AC, @HL

@HL+1

DEC* Rx

0100 0001 0XXX XXXX

AC, Rx

Rx-1

DEC* @HL

0100 0001 1000 0000

AC, @HL

@HL-1

IPA Rx

0100 0010 0XXX XXXX

AC, Rx

Port(A)

IPB Rx

0100 0100 0XXX XXXX

AC, Rx

Port(B)

IPC Rx

0100 0111 0XXX XXXX

AC, Rx

Port(C)

IPD Rx

0100 1000 0XXX XXXX

AC, Rx

Port(D)

MAF Rx

0100 1010 0XXX XXXX

AC,Rx

STS1

B3: CF
B2: AC=0
B1: (No use)
B0: (No use)

MSB Rx

0100 1011 0XXX XXXX

AC,Rx

STS2

B3: (No use)
B2: SCF2(HRx)
B1: SCF1(CPT)
B0: BCF

MSC Rx

0100 1100 0XXX XXXX

AC,Rx

STS3

B3: SCF7(PDV)
B2: PH15
B1: SCF5(TMR1)
B0: SCF4(INT)

MCX Rx

0100 1101 0XXX XXXX

AC,Rx

STS3X

B3: SCF9(RFC)
B2: SCF0(APT)
B1: SCF6(TMR2)
B0: (No use)

Preliminary

14 Ver. 0.0

APU428

Instruction

Machine Code

Function

Flag/Remark

MSD Rx

0100 1110 0XXX XXXX

AC,Rx

STS4

B3: (No use)
B2: RFOVF
B1: WDF
B0: CSF

MDX Rx

0100 1111 0XXX XXXX

AC,Rx

STS4X

B3: ADF4
B2: ADF3
B1: ADF2
B0: ADF1

SR0 Rx

0101 0000 0XXX XXXX

ACn, Rxn

Rx(n+1)

AC3, Rx3

SR1 Rx

0101 0001 0XXX XXXX

ACn, Rxn

Rx(n+1)

AC3, Rx3

SL0 Rx

0101 0010 0XXX XXXX

ACn, Rxn

Rx(n-1)

AC0, Rx0

SL1 Rx

0101 0011 0XXX XXXX

Can, Rxn

Rx(n-1)

AC0, Rx0

DAA

0101 0100 0000 0000

BCD(AC)

DAA* Rx

0101 0101 0XXX XXXX

AC, Rx

BCD(AC)

DAA* @HL

0101 0101 1000 0000

AC, @HL

BCD(AC)

DAS

0101 0110 0000 0000

BCD(AC)

DAS* Rx

0101 0111 0XXX XXXX

AC, Rx

BCD(AC)

DAS* @HL

0101 0111 1000 0000

AC, @HL

BCD(AC)

LDS Rx,D

0101 1DDD DXXX XXXX AC, Rx

LDH Rx,@HL

0110 0000 0XXX XXXX

AC, Rx

H(T@HL)

LDH* Rx,@HL

0110 0001 0XXX XXXX

AC, Rx

H(T@HL)

HL + 1

LDL Rx,@HL

0110 0010 0XXX XXXX

AC, Rx

L(T@HL)

LDL* Rx,@HL

0110 0011 0XXX XXXX

AC, Rx

L(T@HL)

@HL + 1

MRF1 Rx

0110 0100 0XXX XXXX

AC,Rx

RFC3-0

MRF2 Rx

0110 0101 0XXX XXXX

AC,Rx

RFC7-4

MRF3 Rx

0110 0110 0XXX XXXX

AC,Rx

RFC11-8

MRF4 Rx

0110 0111 0XXX XXXX

AC,Rx

RFC15-12

STA Rx

0110 1000 0XXX XXXX

STA @HL

0110 1000 1000 0000

@HL

LDA Rx

0110 1100 0XXX XXXX

LDA @HL

0100 1100 1000 0000

@HL

MRA Rx

0110 1101 0XXX XXXX

Rx3

MRW @HL,Rx

0110 1110 0XXX XXXX

AC,@HL

MWR Rx,@HL

0110 1111 0XXX XXXX

AC,Rx

@HL

MRW Ry,Rx

0111 0YYY YXXX XXXX AC,Ry

MWR Rx,Ry

0111 1YYY YXXX XXXX AC,Rx Ry

JB0 X

1000 0XXX XXXX XXXX PC

if AC0 = 1

Preliminary

15 Ver. 0.0

APU428

Instruction

Machine Code

Function

Flag/Remark

JB1 X

1000 1XXX XXXX XXXX PC

if AC1 = 1

JB2 X

1001 0XXX XXXX XXXX PC

if AC2 = 1

JB3 X

1001 1XXX XXXX XXXX PC

if AC3 = 1

JNZ X

1010 0XXX XXXX XXXX PC

if AC 0

JNC X

1010 1XXX XXXX XXXX PC

if CF = 0

JZ X

1011 0XXX XXXX XXXX PC

if AC = 0

JC X

1011 1XXX XXXX XXXX PC

if CF = 1

CALL X

1100 0XXX XXXX XXXX

STACK

PC+1

JMP X

1101 0XXX XXXX XXXX PC

RTS

1101 1000 0000 0000

STACK

CALL Return

SCC X

1101 1001 0X0X 0XXX

X6 = 1: Cfq = BCLK
X6 = 0: Cfq = PH0
X5 = 1: Cpw = BCLK
X5 = 0: Cpw = PH0
X,4 = 1: Set P(A)
X,4 = 0: Set P(C)
X2,1,0=001: Cch = PH10
X2,1,0=010: Cch = PH8
X2,1,0=100: Cch = PH6

SCA X

1101 1010 00XX 0000

X5: A1-4 Enable (SEF5)
X4: C1-4 Enable (SEF4)

SAD X

1101 1011 00XX XXXX

X5: Enable Cmp. output
X4: Latch Data to Cmp.
X3=1: CP4(+) = LBR
X3=0: CP4(+) = AN4
X2=1: CP1~4(-) = AN4
X2=0: CP1~4(-) = DAC
X1: Enable LBR
X0: Enable DAC

SPA X

1101 1100 000X XXXX

X4: Set A4~1 Pull-Low
X3~0: Set A4~1 I/O

SPB X

1101 1101 0000 XXXX

X3~0: Set B4~1 I/O

SPC X

1101 1110 000X XXXX

X4: Set C4-1 Pull-Low
/Low-Level-Hold
X3~0: Set C4-1 I/O

SPD X

1101 1111 0000 XXXX

X3-0: Set D4~1 I/O

TMS Rx

1110 0000 0XXX XXXX

Timer1

Rx, AC

TMS @HL

1110 0001 0000 0000

Timer1

T@HL

TMSX

X 1110 0010 XXXX XXXX

X7,6=11: Ctm=FREQ
X7,6=10: Ctm=PH15
X7,6=01: Ctm=PH3
X7,6=00: Ctm=PH9
X5~0: Set Timer1 Value

MDA Rx

1110 0011 0XXX XXXX

DAC Rx

TM2 Rx

1110 0100 0XXX XXXX

Timer2 Rx, AC

TM2 @HL

1110 0101 0000 0000

Timer2 T@HL

Preliminary

16 Ver. 0.0

APU428

Instruction

Machine Code

Function

Flag/Remark

TM2X X

1110 011X XXXX XXXX

X8,7,6=111 : Ctm=PH13
X8,7,6=110 : Ctm=PH11
X8,7,6=101 : Ctm=PH7
X8,7,6=000 : Ctm=PH5
X8,7,6=011 : Ctm=FREQ
X8,7,6=010 : Ctm=PH15
X8,7,6=001 : Ctm=PH3
X8,7,6=000 : Ctm=PH9
X5~0: Set Timer2 Value

SHE X

1110 1000 0XXX XXX0

X6: Enable HEF6(RFC)
X4: Enable HEF4(TMR2)
X3: Enable HEF3(PDV)
X2: Enable HEF2(INT)
X1: Enable HEF1(TMR1)

SIE* X

1110 1001 0XXX XXXX

X6: Enable IEF6(RFC)
X4: Enable IEF4(TMR2)
X3: Enable IEF3(PDV)
X2: Enable IEF2(INT)
X1: Enable IEF1(TMR1)
X0: Enable IEF0(A,CPT)

PLC X

1110 101X 0XXX XXXX

X8: Reset PH15~11
X6, 4~0: Reset HRF6, 4~0

SRF X

1110 1100 00XX XXXX

X5: Enable Cx Control
X4: Enable Timer2 Control
X3: Enable Counter
X2: Enable RH Output
X1: Enable RT Output
X0: Enable RR Output

ENX
EHM
ETP
ERR

SRE X

1110 1101 X0XX 0000

X6~4: Enable SRF6~4

SRF6 (A Port)
SRF5 (HRF2)
SRF4 (M Port)

FAST

1110 1110 0000 0000

SCLK: High Speed Clock

SLOW

1110 1111 0000 0000

SCLK: Low Speed Clock

SF X

1111 0000 X00X XXXX

X7: Reload Set
X4: WDT Enable
X3: HALT after EL LIGHT
X2: EL LIGHT On
X1: BCF Set
X0: CF Set

RL1
WDF

BCF
CF

RF X

1111 0100 X00X 0XXX

X7: Reload Reset
X4: WDT Reset
X2: EL LIGHT Off
X1: BCF Reset
X0: CF Reset

RL1
WDF

BCF
CF

SF2 X

1111 1000 0000 0XXX

X0: Reload Set
X1: Dis-ENX Set
X2: Close all segments

RL2
DED
RSOFF

RF2 X

1111 1001 0000 0XXX

X0: Reload Reset
X1: Dis-ENX Reset
X2: Release all Segments

RL2
DED
RSOFF

Preliminary

17 Ver. 0.0

APU428

Instruction

Machine Code

Function

Flag/Remark

ALM X

1111 101X XXXX XXXX

X8,7,6=111: FREQ
X8,7,6=100: DC1
X8,7,6=011: PH3
X8,7,6=010: PH4
X8,7,6=001: PH5
X8,7,6=000: DC0
X5~0 PH15~10

ELC X

1111 110X XXXX XXXX

X8=1 BCLKX
X8=0 PH0
X7,6=11 BCLK/8
X7,6=10 BCLK/4
X7,6=01 BCLK/2
X7,6=00 BCLK
X5,4=11 1/1
X5,4=10 1/2
X5,4=01 1/3
X5,4=00 1/4
X3,2=11 PH5
X3,2=10 PH6
X3,2=01 PH7
X3,2=00 PH8
X1,0=11 1/1
X1,0=10 1/2
X1,0=01 1/3
X1,0=00 1/4

ELP � CLK

BCLKX

ELP � DUTY

ELC � CLK

ELC � DUTY

HALT

1111 1110 0000 0000

HALT operation

STOP

1111 1111 0000 0000

STOP operation

Symbol description

AC:

Accumulator

Immediate data

ACn:

Accumulator bit-n

PC:

Program counter

Address

CF:

Carry flag

Rx:

Memory of address X

Rxn:

Memory bit-n of address X

WDF:

Watchdog timer enable flag

Ry:

Memory of working register Y

HL:

Index register

BCF:

Back-up flag

BCLK:

System clock address

@HL:

Memory of index RAM

IEFn:

Interrupt enable flag

HRFn:

HALT release flag

SRFn:

Stop release enable flag

HEFn:

HALT release enable flag

SCFn:

Start condition flag

Cfq:

Clock source of frequency generator

Cch:

Clock source of chartering detector

Ctm:

Clock source of timer

TMR:

Timer overflow release flag

PDV:

Predivider

SEFn:

Switch enable flag

Lz:

LCD latch

FREQ:

Frequency generator setting value

T@HL:

Memory of index ROM

ADF:

ADC flag

CSF:

Clock source flag

DAC:

Digital-to-analog converter output signal

LBR:

Low-battery voltage reference

Low address of index

High address of index

RFOVF: RFC overflow flag

HT@HL: High nibble of index ROM

LT@HL: Low nibble of index ROM

Preliminary

18 Ver. 0.0

APU428

Электронный компонент: APU428