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Электронный компонент: ASM34012C

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6F-3 NO.7, LANE 75, TA-AN ROAD, SEC.1, TAIPEI, TAIWAN, R.O.C.
HTTP://WWW.APLUSINC.COM.TW
7576F-3 TEL:886-2-27818277 FAX:886-2-27815779
ASM34012C
DATA SHEET
Rev 1.2
1
ASM34012C
VERY LOW-COST VOICE SYNTHESIZER WITH 4-BIT MICROPROCESSOR
1.0 General Description
The ASM34012C is very low cost voice synthesizer with 4-bit microprocessor. It has various features
including 4-bit ALU, ROM, RAM, I/O ports, timers, clock generator, watchdog timer(WDT), voice
synthesizer, etc. It consists of 22 instructions in the device. With CMOS technology and halt function
can minimize power dissipation. Its architecture is similar to RISC, with two stages of instruction
pipeline. It allows all instructions to be executed in a single cycle, except for program branches and
data table read instructions (which need two instruction cycles).
1.1 Feature
Single power supply can operate from 2.4V through 5V
Internal Program ROM: 4K x 10-bit
1 sets of 20-bit DPR can access up to 1024K x 10 bits data memory space
Data Registers:
96 x 4-bit data RAM (00-1Fh plus 40h-7Fh)
Unbanked special function registers (SFR) range: 20h-3Fh
I/O Ports:
PRA: 4-bit I/O Port A (2Bh)
PRB: 4-bit Output Port B (2Dh)
PRC: 4-bit Input Port C (2Fh)
On-chip clock generator: Resistive Clock Drive(RM)
Timer: 1
Timer0: a 9-bit auto-reload timer/counter
Stack: 2-level subroutine nesting
HALT and Release from HALT function to reduce power consumption
Watch Dog Timer (WDT)
Instruction: 1-cycle instruction except for table read and program branches which are 2-cycles
Number of instruction: 22
ASM34012C
Rev 1.2
2
FIGURE 1.1 : Block Diagram of ASM34012C
COUT
OSC
VDD/GND
ROM
1
PC[11:0]
ROM Latch
Instruction
Latch
Instruction
Decoder
0
PCH(8)
PCL(4)
PCLATCH(8)
DPR3,2,1
Program
DLATCH(10)
Clock Generator
Power on Reset
Test select
P1,P2,P3,P4
enter test mode
Timer0(9)
Reset Chip
Stack(12)
Data Bus[3:0]
Instruction Bus [9:0]
ROM_ADDR[19:0]
ROM_Data[9:0]
Data Bus[3:0]
Control Signal
ADDR[19:0]
=00000000b
(ADDR[19:12])
PRASL(4)
weak or strong
pull-low for PRA,
(Data)
In
str
u
cti
o
n
Bu
s
[
9
:
0
]
Instruction Bus [9:0]
( Voice synthesizer )
One-Channel
SRAM
(96 x 4)
40h-7Fh
(2-Level)
ALU(4)
Register(4)
Accumlator(4)
Immediate(4)
DPR[19:0]
RESET pin
Reset Chip
PR
A
0
00h-1Fh
PRA(4)
PRB(4)
PRC(4)
PRB, PRC
COUT
ASM34012C
Rev 1.2
3
FIGURE 1.2 : External ROM Map of ASM34012C
Data RO
M
12bit x 2 STACK
Reset Vector
FFFFFh(1024Kx10-bits)
00FFFh(4K)
00000h-00FFFh
Pro
g
r
a
m

and data ROM
20-bit Data Pointer
PC[11:0]
00000h-FFFFFh
Reserved for Testing
00080h-003FFh
00400h
00000h
00080h
ASM34012C
Rev 1.2
4
1.2 Pin-Out
ASM34012C Pin-Out
VDD3
I
-
Third Power supply during operation
PRC1
I
STI
Std./O.D.
Input port with programmable strong pull-low or weak pull-low or fix-input-
floating capability
PRC0/RESET
I
STI
Std./O.D.
Input port with programmable strong pull-low or weak pull-low or fix-input-
floating capability
Mask option selected as an external RESET pin with weak pull-low capability
PRA3-1
I/O
STI
Std./O.D.
I/O port with programmable strong pull-low or weak pull-low or fix-input-
floating capability
Output type with standard or Open-Drain output
PRA0/RESET
I/O
STI
Std./O.D.
I/O port with programmable strong pull-low or weak pull-low or fix-input-
floating capability
Output type with standard or Open-Drain output
Mask option selected as an external RESET pin with weak pull-low capability
OSC
I
-
RM mode Oscillator input
VDD1
I
-
First Power supply during operation
COUT
O
-
Current Output of Audio
GND1
I
-
First Circuit Ground Potential
GND2
I
-
Second Circuit Ground Potential
TEST
O
-
Enter Test Mode. ( TEST = High )
VDD2
I
-
Second Power supply during operation
PRB0-3
O
Std./O.D. Output type with standard or Open-Drain output
PRC2-3
I
STI
Std./O.D.
Input port with programmable strong pull-low or weak pull-low or fix-input-
floating capability
GND3
I
-
Third Circuit Ground Potential
1.3 Application circuit
ASM34012C