ii
Copyright ARM Limited 2000. All rights reserved.
ARM DDI 0135A
ARM1020TTM
(Rev 0)
Technical Reference Manual
Copyright ARM Limited 2000. All rights reserved.
Release information
Proprietary notice
ARM, the ARM Powered logo, Thumb and StrongARM are registered trademarks of ARM Limited.
The ARM logo, AMBA, Angel, ARMulator, EmbeddedICE, ModelGen, Multi-ICE, PrimeCell,
ARM7TDMI, ARM7TDMI-S, ARM9TDMI, ARM9E-S, ETM7, ETM9, TDMI, and STRONG are
trademarks of ARM Limited.
Document confidentiality status
Figure 7-1 on page 7-2 reprinted with permission IEEE Std 1149.1-1990, IEEE Standard Test Access Port
and Boundary-Scan Architecture Copyright1999, by IEEE. The IEEE disclaims any responsibility or liability
resulting from the placement and use in the described manner.
Product status
The information in this document is Preliminary (information on a product under development).
ARM web address
http://www.arm.com
Change history
Date
Issue
Change
9 February 2000
A
First release
All other products or services mentioned herein may be trademarks of their respective owners.
Neither the whole nor any part of the information contained in, or the product described in, this document may
be adapted or reproduced in any material form except with the prior written permission of the copyright
holder.
The product described in this document is subject to continuous developments and improvements. All
particulars of the product and its use contained in this document are given by ARM Limited in good faith.
However, all warranties implied or expressed, including but not limited to implied warranties or
merchantability, or fitness for purpose, are excluded.
This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable
for any loss or damage arising from the use of any information in this document, or any error or omission in
such information, or any incorrect use of the product.
ARM DDI 0135A
Copyright ARM Limited 2000. All rights reserved.
iii
Contents
ARM1020TTM (Rev 0) Technical Reference
Manual
Preface
About this document ....................................................................................................xiv
Further reading............................................................................................................ xvii
Feedback ................................................................................................................... xviii
Chapter 1
Introduction
1.1
About the ARM1020T ................................................................................... 1-2
1.2
Processor functional block diagram .............................................................. 1-3
1.3
Pipeline ......................................................................................................... 1-6
1.4
Clocking ...................................................................................................... 1-10
Chapter 2
System Coprocessor Programmer's Model
2.1
About the programmer's model..................................................................... 2-2
2.2
Summary of ARM1020T system control coprocessor (CP15) registers........ 2-3
2.3
Register descriptions .................................................................................... 2-6
Chapter 3
Memory Management Unit
3.1
About the MMU ............................................................................................. 3-2
3.2
MMU software-accessible registers .............................................................. 3-3
3.3
Address translation ....................................................................................... 3-5
3.4
MMU descriptors ........................................................................................... 3-8
3.5
MMU memory access control...................................................................... 3-18
3.6
MMU cachable and bufferable information ................................................. 3-20
iv
Copyright ARM Limited 2000. All rights reserved.
ARM DDI 0135A
3.7
MMU aborts ................................................................................................ 3-21
3.8
MMU fault checking sequence ................................................................... 3-22
3.9
MMU and write buffer ................................................................................. 3-26
3.10
MMU faults and CPU aborts....................................................................... 3-27
3.11
Fault status ................................................................................................. 3-28
3.12
External aborts ........................................................................................... 3-29
3.13
Interaction of the MMU, caches, and write buffer ....................................... 3-30
Chapter 4
Caches and Write Buffer
4.1
About the caches and write buffer ................................................................ 4-2
4.2
Instruction cache .......................................................................................... 4-3
4.3
Data cache and write buffer.......................................................................... 4-6
4.4
Cache coherence ....................................................................................... 4-13
4.5
Portability issues......................................................................................... 4-15
Chapter 5
Branch Prediction and Prefetch Unit
5.1
About the Prefetch Unit ................................................................................ 5-2
5.2
Branch prediction.......................................................................................... 5-3
5.3
Treatment of BL and BLX instructions.......................................................... 5-4
5.4
Instruction memory barrier instruction (IMB) ................................................ 5-5
5.5
ARM1020T IMB implementation................................................................... 5-6
Chapter 6
Bus Interface
6.1
Bus features ................................................................................................. 6-2
6.2
ARM1020T AMBA AHB signals.................................................................... 6-3
6.3
Arbiter signals............................................................................................... 6-5
6.4
Test signals .................................................................................................. 6-6
6.5
AHB control signals in ARM1020T ............................................................... 6-8
6.6
Timing......................................................................................................... 6-11
6.7
The ARM1020T instruction bus interface unit (I-BIU) overview.................. 6-12
6.8
The ARM1020 data bus interface unit (D-BIU) overview............................ 6-13
6.9
AMBA interface........................................................................................... 6-14
6.10
The Write Buffer (WB) ................................................................................ 6-15
6.11
Handling external aborts............................................................................. 6-16
6.12
Coprocessor interface ................................................................................ 6-17
Chapter 7
JTAG Interface
7.1
JTAG interface and halt mode...................................................................... 7-2
7.2
The JTAG port and test data registers ......................................................... 7-4
7.3
EXTEST........................................................................................................ 7-6
7.4
SCAN_N ....................................................................................................... 7-7
7.5
RESTART..................................................................................................... 7-8
7.6
INTEST......................................................................................................... 7-9
7.7
IDCODE...................................................................................................... 7-10
7.8
BYPASS ..................................................................................................... 7-11
7.9
HALT .......................................................................................................... 7-12
7.10
INTEST....................................................................................................... 7-13
ARM DDI 0135A
Copyright ARM Limited 2000. All rights reserved.
v
7.11
Using EXTEST and INTEST with ARM1020T............................................. 7-14
7.12
Scan chain descriptions .............................................................................. 7-15
Chapter 8
Debug
8.1
About the ARM1020T debug unit.................................................................. 8-2
8.2
Debug registers............................................................................................. 8-4
8.3
Values in the link register after aborts......................................................... 8-13
8.4
Halt mode.................................................................................................... 8-15
8.5
Monitor mode .............................................................................................. 8-22
8.6
Comms channel .......................................................................................... 8-23
Chapter 9
AMBA Test Interface
9.1
About the AMBA test interface ...................................................................... 9-2
9.2
Memory mapping .......................................................................................... 9-4
9.3
TIC test modes.............................................................................................. 9-5
9.4
JTAG test mode ............................................................................................ 9-9
9.5
Cache testing .............................................................................................. 9-10
9.6
MMU testing ................................................................................................ 9-15
Chapter 10
Instruction Cycle Summary and Interlocks
10.1
Introduction ................................................................................................. 10-2
10.2
Instruction cycle times................................................................................. 10-8
10.3
Interlocks................................................................................................... 10-10
Chapter 11
AC Characteristics
11.1
ARM1020T timing diagrams........................................................................ 11-2
11.2
ARM1020T timing parameters .................................................................... 11-3
Appendix A
Signal Descriptions
A.1
Global control signals....................................................................................A-2
A.2
AHB signals in normal mode.........................................................................A-3
A.3
AHB signals in test mode ..............................................................................A-6
A.4 PLL
signals ...................................................................................................A-7
A.5
JTAG and TAP controller signals ..................................................................A-8
A.6 Debug
signals .............................................................................................A-10
A.7 Coprocessor
signals ...................................................................................A-11
PDF 
ZIP