Copyright 2003 ARM Limited. All rights reserved.
ARM DDI 0289B
ARM11 Memory Built-In Self Test
Controller
Technical Reference Manual
ii
Copyright 2003 ARM Limited. All rights reserved.
ARM DDI 0289B
ARM11 Memory Built-In Self Test Controller
Technical Reference Manual
Copyright 2003 ARM Limited. All rights reserved.
Release Information
The table below shows the release state and change history of this document.
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Web Address
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Change history
Date
Issue
Change
14 April 2003
A
First release
28 April 2003
B
Addition of ARM11 to product name
ARM DDI 0289B
Copyright 2003 ARM Limited. All rights reserved.
iii
Contents
ARM11 Memory Built-In Self Test Controller
Technical Reference Manual
Preface
About this book .............................................................................................. x
Feedback ..................................................................................................... xiii
Chapter 1
Introduction
1.1
Overview ..................................................................................................... 1-2
1.2
MBIST ports ................................................................................................ 1-3
Chapter 2
Functional Description
2.1
Timing ......................................................................................................... 2-2
2.2
Bitmap mode ............................................................................................... 2-6
Chapter 3
ARM11 MBIST Controller Instruction Register
3.1
Instruction Register ..................................................................................... 3-2
3.2
Field descriptions ........................................................................................ 3-3
Appendix A
Signal Descriptions
A.1
Signal descriptions ...................................................................................... A-2
Contents
iv
Copyright 2003 ARM Limited. All rights reserved.
ARM DDI 0289B
Appendix B
Integration with the ARM1136 Processor
2.1
Instruction Register enables field ............................................................... B-2
B.2
Choosing the RAM size .............................................................................. B-3
B.3
Connection ............................................................................................... B-12
Appendix C
Integration with the ETB11
3.1
Instruction Register enables field ............................................................... C-2
C.2
Trace RAM ................................................................................................. C-3
C.3
Connection ................................................................................................. C-5
ARM DDI 0289B
Copyright 2003 ARM Limited. All rights reserved.
v
List of Tables
ARM11 Memory Built-In Self Test Controller
Technical Reference Manual
Change history .............................................................................................................. ii
Table 1-1
ARM11 MBIST Controller interface signals ............................................................... 1-4
Table 2-1
Format of the data log ............................................................................................... 2-5
Table 3-1
Register settings and resulting address sizes ........................................................... 3-5
Table 3-2
Register settings and resulting address sizes ........................................................... 3-5
Table 3-3
Behavior of the engine control field ........................................................................... 3-6
Table 3-4
Supported patterns .................................................................................................... 3-7
Table 3-5
Go/No-Go algorithm .................................................................................................. 3-9
Table A-1
Signal descriptions .................................................................................................... A-2
Table B-1
Enable bit RAM selection .......................................................................................... B-2
Table B-2
Example values for x- and y-Locations, TLB RAM .................................................... B-3
Table B-3
Choosing values for x- and y-Locations, BTAC RAM ................................................ B-4
Table B-4
ITCM size and location .............................................................................................. B-4
Table B-5
Cache valid size and locations .................................................................................. B-5
Table B-6
TCM size and locations ............................................................................................. B-6
Table B-7
Instruction cache size and tag RAM locations .......................................................... B-7
Table B-8
Instruction cache size and data RAM locations ........................................................ B-7
Table B-9
Greater of data cache or data TCM size and dirty RAM locations ............................ B-8
Table B-10
DTCM size and DTCM RAM locations ...................................................................... B-9
Table B-11
Data cache size and data cache tag RAM locations ............................................... B-10
Table B-12
Data cache size and data cache tag RAM locations ............................................... B-10
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