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Copyright 2001, 2002. ARM Limited. All rights reserved.
ARM DDI 0222B
ARM9EJ-S
Technical Reference Manual
Copyright 2001, 2002. ARM Limited. All rights reserved.
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Change history
Date
Issue
Change
August 1, 2001
A
First release
September 30, 2002
B
Second release
ARM DDI 0222B
Copyright 2001, 2002. ARM Limited. All rights reserved.
iii
Contents
ARM9EJ-S Technical Reference Manual
Preface
About this document .................................................................................... xvi
Feedback ...................................................................................................... xx
Chapter 1
Introduction
1.1
About the ARM9EJ-S with Jazelle technology ............................................ 1-2
1.2
ARM9EJ-S architecture with Jazelle technology ......................................... 1-6
1.3
ARM9EJ-S block, core, and interface diagrams ......................................... 1-8
1.4
ARM9EJ-S instruction set summary ......................................................... 1-12
Chapter 2
Programmer's Model
2.1
About the programmer's model ................................................................... 2-2
2.2
Processor operating states ......................................................................... 2-3
2.3
Memory formats .......................................................................................... 2-4
2.4
Instruction length ......................................................................................... 2-6
2.5
Data types ................................................................................................... 2-7
2.6
Operating modes ........................................................................................ 2-8
2.7
Registers ..................................................................................................... 2-9
2.8
The program status registers .................................................................... 2-15
2.9
Exceptions ................................................................................................ 2-20
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Copyright 2001, 2002. ARM Limited. All rights reserved.
ARM DDI 0222B
Chapter 3
Memory Interface
3.1
About the memory interface ....................................................................... 3-2
3.2
Instruction interface .................................................................................... 3-3
3.3
Instruction interface addressing signals ..................................................... 3-4
3.4
Instruction interface data timed signals ...................................................... 3-6
3.5
Endian effects for instruction Fetches ........................................................ 3-7
3.6
Instruction interface cycle types ................................................................. 3-8
3.7
Data interface ........................................................................................... 3-16
3.8
Data interface addressing signals ............................................................ 3-18
3.9
Data interface data timed signals ............................................................. 3-21
3.10
Data interface cycle types ........................................................................ 3-26
3.11
Endian effects for data transfers ............................................................... 3-35
3.12
Use of CLKEN to control bus cycles ......................................................... 3-36
Chapter 4
Interrupts
4.1
About interrupts .......................................................................................... 4-2
4.2
Hardware interface ..................................................................................... 4-3
4.3
Maximum interrupt latency ......................................................................... 4-6
4.4
Minimum interrupt latency .......................................................................... 4-7
Chapter 5
Coprocessor Interface
5.1
About the coprocessor interface ................................................................. 5-2
5.2
LDC or STC ................................................................................................ 5-4
5.3
MCR or MRC .............................................................................................. 5-8
5.4
MCRR or MRRC ......................................................................................... 5-9
5.5
Interlocked MCR ....................................................................................... 5-10
5.6
Interlocked MCRR .................................................................................... 5-11
5.7
CDP .......................................................................................................... 5-12
5.8
Privileged instructions ............................................................................... 5-14
5.9
Busy-waiting and interrupts ...................................................................... 5-15
5.10
Coprocessor 15 MCRs ............................................................................. 5-16
5.11
Connecting coprocessors ......................................................................... 5-17
Chapter 6
Debug Interface and EmbeddedICE-RT
6.1
About the debug interface .......................................................................... 6-2
6.2
Debug systems ........................................................................................... 6-3
6.3
About EmbeddedICE-RT ............................................................................ 6-6
6.4
Disabling EmbeddedICE-RT ...................................................................... 6-8
6.5
Debug interface signals .............................................................................. 6-9
6.6
ARM9EJ-S core clock domains ................................................................ 6-15
6.7
Determining the core and system state .................................................... 6-16
6.8
The debug communications channel ........................................................ 6-17
6.9
Monitor mode debug ................................................................................. 6-22
6.10
Using Watchpoints and breakpoints in Jazelle state ................................ 6-24
ARM DDI 0222B
Copyright 2001, 2002. ARM Limited. All rights reserved.
v
Chapter 7
Device Reset
7.1
About device reset ...................................................................................... 7-2
7.2
Reset modes ............................................................................................... 7-3
7.3
ARM9EJ-S core behavior on exit from reset ............................................... 7-5
Chapter 8
Instruction Cycle Times
8.1
Instruction cycle count summary ................................................................. 8-3
8.2
Introduction to detailed instruction cycle timings ......................................... 8-7
8.3
Branch and ARM branch with link ............................................................... 8-9
8.4
Thumb branch with link ............................................................................. 8-10
8.5
Branch and exchange ............................................................................... 8-11
8.6
Thumb Branch, Link, and Exchange <immediate> ................................... 8-12
8.7
Data operations ......................................................................................... 8-13
8.8
MRS .......................................................................................................... 8-15
8.9
MSR operations ........................................................................................ 8-16
8.10
Multiply and multiply accumulate .............................................................. 8-17
8.11
QADD, QDADD, QSUB, and QDSUB ....................................................... 8-21
8.12
Load register ............................................................................................. 8-22
8.13
Store register ............................................................................................ 8-27
8.14
Load multiple registers .............................................................................. 8-28
8.15
Store multiple registers ............................................................................. 8-31
8.16
Load double register ................................................................................. 8-32
8.17
Store double register ................................................................................. 8-33
8.18
Data swap ................................................................................................. 8-34
8.19
PLD ........................................................................................................... 8-36
8.20
Software interrupt, Undefined instruction, and exception entry ................. 8-37
8.21
Coprocessor data processing operation ................................................... 8-38
8.22
Load coprocessor register (from memory) ................................................ 8-39
8.23
Store coprocessor register (to memory) .................................................... 8-41
8.24
Coprocessor register transfer (to ARM) .................................................... 8-43
8.25
Coprocessor register transfer (from ARM) ................................................ 8-44
8.26
Double coprocessor register transfer (to ARM) ......................................... 8-45
8.27
Double coprocessor register transfer (from ARM) .................................... 8-46
8.28
Coprocessor absent .................................................................................. 8-47
8.29
Unexecuted instructions ............................................................................ 8-49
Chapter 9
AC Parameters
9.1
Timing diagrams ......................................................................................... 9-2
9.2
AC timing parameter definitions .................................................................. 9-9
Appendix A
Signal Descriptions
A.1
Clock interface signals ................................................................................ A-2
A.2
Instruction memory interface signals ........................................................... A-3
A.3
Data memory interface signals .................................................................... A-5
A.4
Miscellaneous signals ................................................................................. A-7
A.5
Coprocessor interface signals ..................................................................... A-8
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