High Performance
Flat Panel / CRT
VGA Controllers
65540 / 545
Data Sheet
Revision 1.2
October 1995
Copyright Notice
Copyright 1995, Chips and Technologies, Inc. ALL RIGHTS RESERVED.
This manual is copyrighted by Chips and Technologies, Inc. You may not reproduce,
transmit, transcribe, store in a retrieval system, or translate into any language or
computer language, in any form or by any means, electronic, mechanical, magnetic,
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written permission of Chips and Technologies, Inc.
Restricted Rights Legend
Use, duplication, or disclosure by the Government is subject to restrictions set forth in
subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at
252.277-7013.
Trademark Acknowledgement
CHIPS Logotype, CHIPSlink, CHIPSPort, ELEAT, LeAPSet, NEAT, NEATsx, PEAK,
PRINTGINE, SCAT, SuperMathDX, SuperState, and WINGINE are registered trademarks
of Chips and Technologies, Incorporated.
CHIPSet, Super Math, WinPC, and XRAM Video Cache are trademarks of Chips and
Technologies, Incorporated.
IBM AT, XT, PS/2, Micro Channel, Personal System/2, Enhanced Graphics Adapter,
Color Graphics Adapter, Video Graphics Adapter, IBM Color Display, and IBM
Monochrome Display are trademarks of International Business Machines Corporation.
Hercules is a trademark of Hercules Computer Technology.
MS-DOS and Windows are trademarks of Microsoft Corporation.
MultiSync is a trademark of Nippon Electric Company (NEC).
Brooktree and RAMDAC are trademarks of Brooktree Corporation.
Inmos is a trademark of Inmos Corporation.
TRI-STATE is a registered trademark of National Semiconductor Corporation.
VESA is a registered trademark of Video Electronics Standards Association.
VL-Bus is a trademark of Video Electronics Standards Association.
All other trademarks are the property of their respective holders.
Disclaimer
This document is provided for the general information of the customer. Chips and
Technologies, Inc., reserves the right to modify the information contained herein as
necessary and the customer should ensure that it has the most recent revision of the data
sheet. CHIPS makes no warranty for the use of its products and bears no responsibility
for any errors which may appear in this document. The customer should be on notice that
the field of personal computers is the subject of many patents held by different parties.
Customers should ensure that they take appropriate action so that their use of the products
does not infringe upon any patents. It is the policy of Chips and Technologies, Inc. to
respect the valid patent rights of third parties and not to infringe upon or assist others to
infringe upon such rights.
Revision 1.2
65540 / 545
n
Highly integrated design (flat panel / CRT VGA
controller, RAMDAC, clock synthesizer)
n
Multiple Bus Architecture Integrated Interface
Local Bus (32-bit CPU Direct and VL)
EISA/ISA (PC/AT) 16-bit Bus
PCI Bus (65545)
n
Flexible display memory configurations
One 256Kx16 DRAM
(512KB)
Four 256Kx4 DRAMs
(512KB)
Two 256Kx16 DRAMs
(1MB)
n
Advanced frame buffer architecture uses
available display memory, maximizing
integration and minimizing chip count
n
Integrated programmable linear address feature
accelerates GUI performance
n
Hardware windows acceleration (65545)
32-bit graphics engine
- System-to-screen and screen-to-screen
BitBLT
- 3 operand ROP's
- Color expansion
- Optimized for WindowsTM BitBLT format
Hardware line drawing
64x64x2 hardware cursor
n
Hardware pop-up icon (65545)
64x64 pixels by 4 colors
128x128 pixels by 2 colors
n
High performance resulting from zero wait-state
writes (write buffer) and minimum wait-state
reads (internal asynchronous FIFO design)
n
Mixed 3.3V 0.3V / 5.0V 10% Operation
n
Interface to CHIPS' PC Video to display "live"
video on flat panel displays
n
Supports panel resolutions up to 1280 x 1024
resolution including 800x600 and 1024x768
n
Supports non-interlaced CRT monitors with
resolutions up to 1024 x 768 / 256 colors
n
True-color and Hi-color display capability with
flat panels and CRT monitors up to 640x480
resolution
n
Direct interface to Color and Monochrome Dual
Drive (DD) and Single Drive (SS) panels
(supports 8, 9, 12, 15, 16, 18 and 24-bit data
interfaces)
n
Advanced power management features minimize
power consumption during:
Normal operation
Standby (Sleep) modes
Panel-Off Power-Saving Mode
n
Flexible on-board Activity Timer facilitates
ordered shut-down of the display system
n
Power Sequencing control outputs regulate
application of Bias voltage, +5V to the panel and
+12 V to the inverter for backlight operation
n
SMARTMAPTM intelligent color to gray scale
conversion enhances text legibility
n
Text enhancement feature improves white text
contrast on flat panel displays
n
Fully Compatible with IBMTM VGA
n
EIAJ-standard 208-pin plastic flat pack
System Diagram
65540
or
65545
To CRT
Display
To Flat
Panel
Display
RGB
H/V Sync
Panel Control
Panel Data
Address
Data
Control
14.31818 MHz
32-bit 386/486
CPU Direct or VL
Local Bus, PCI
Bus, or 16-bit ISA
System Bus
BIOS
ROM
65540 / 545
High Performance
Flat Panel / CRT VGA Controller
16/24
32
24
32
512KByte or
1MByte Video
Memory
28
Optional
PCVideo
Multi-Media
Interface
Revision Date
By Comment
1.1
9/94
DH
Added note: Refer to Electrical Specs for maximum clock frequencies in
'Supported Video Modes' table
Added note: Not all above resolutions can be supported at 3.3V and/or 5V
Changed Mode 50 in Supported Video Modes-Extended Resolution Table
from 16 to 16M
Reset column in Reset/Setup/Test/Standby/Panel-Off Mode table was
incorrect. Now reads: "RESET#/Low///High/High"
Changed note for Pin List-Bus Interface: from "Drive=5V low drive and
3V high drive" to "IOL and IOH drive listed above indicates 5V low
drive and 3.3V high drive (see also XR6C)"
Changed pin description: pin 25 LDEV# pin type "Out/OC" to "Out"
Changed Config Reg XR01 bits 2-1 VL-Bus description for pin
23=CRESET should read pin 23=RDYRTN#
Changed Ext Reg XR2D and XR2E to (CMPR Enabled) and (CMPR
Disabled) and added note: "For DD panels without frame acceleration,
the programmed value should be doubled"
Updated tables for "No FRC" and "2-Frame FRC"
Updated Flat Panel Timing "CD: 010" should read "CD: 001"
Updated Programming: FLM delay programmed in XR2C should be equal
to: CRT blank time FLM front porch FLM width
XR2D LP Delay (CMPR enabled) & XR2E LP Delay (CMPR disabled)
Added note: "Can use external 14.31818 MHz oscillator into XTALI (203)
with XTALO (204) as no connect"
Updated Elec Specs: changed "Max" under "Normal Operating Conditions"
from 90 to 100; "memory clock is assumed to be 68 MHz not 65 MHz;"
and "VL-Bus timing is compatible with VL-Bus Specification 2.0"
Added timing for VL-Bus LDEV#, 14.31818 MHz, DRAM R/M/W and
PC-Video and modified timing for PCI Bus Frame
Clarified function of ACTI output.
1.2
7/95
BB/MP
Updated Supported Video Modes table
Updated I/O Map section
Added 64310 to CHIPS VGA Product Family in Register Summary
Updated Extension Registers table
Updated XR33, XR6C, XR6F in the Extension Registers section
Added Rset formula to CRT Panel Interface Circuit
Updated Interface-Optrex DMF-50351NC-FW (640x480 Color STN-DD)
LCD Panel Interface example
Updated 65540/545 DC Characteristics in timing section
Updated Local Bus Input Setup & Hold, Local Bus Output Valid, Local
Bus Output Float Delay, VL-Bus LDEV#, CRT Output, Panel Output
Timing diagrams
Added 65545B2 specifications
Revision History
Revision 1.2
2
65540 / 545
Revision History
Table of Contents
Revision 1.2
3
65540 / 545
Table of Contents
Section
Page
Introduction / Overview ..................................
7
Minimum Chip Count / Board Space ..........
8
Display Memory Interface...........................
8
CPU Bus Interface ....................................... 10
High Performance Features ......................... 10
65545 Acceleration...................................... 10
65545 Hardware Cursor............................... 10
PC Video / Overlay Support........................ 10
Display Interface.......................................... 11
Flat Panel Displays.................................. 11
Panel Power Sequencing ............................. 11
CRT Displays .......................................... 11
Simultaneous Flat Panel / CRT Display.. 14
Display Enhancement Features ................... 14
"True-Gray" Gray Scale Algorithm ........ 14
RGB Color to Gray Scale Reduction ...... 14
SmartMapTM ............................................ 14
Text Enhancement................................... 15
Vertical and Horizontal Compensation ... 15
Advanced Power Management.................... 16
Normal Operating Mode ......................... 16
Mixed 3.3V and 5V Operation................ 16
Panel Off Mode ....................................... 16
Standby Mode ......................................... 16
CRT Power Management (DPMS) ......... 16
CPU Activity Indicator / Timer ................... 17
Full Compatibility ....................................... 17
Write Protection ...................................... 17
Extension Registers ................................. 17
Panel Interface Registers......................... 17
Alternate Panel Timing Registers ........... 17
Context Switching ................................... 17
Reset, Setup, and Test Modes...................... 18
Reset Mode.............................................. 18
Setup Mode ............................................. 18
Tri-State Mode ........................................ 18
ICT (In-Circuit-Test) Mode .................... 18
Chip Architecture ........................................ 19
Sequencer ................................................ 19
CRT Controller........................................ 19
Graphics Controller ................................. 19
Attribute Controller ................................. 19
VGA / Color Palette DAC....................... 19
Clock Synthesizers .................................. 20
Configuration Inputs.................................... 21
Virtual Switch Register ............................... 21
Light Pen Registers...................................... 21
BIOS ROM Interface................................... 21
Package........................................................ 21
Application Schematics ............................... 22
Section
Page
Pinouts (65540) ............................................... 23
Pinouts (65545) ............................................... 24
Pin Diagram (65540) ................................... 23
Pin Diagram (65545) ................................... 24
Pin Lists ....................................................... 25
Pin Descriptions - ISA/VL-Bus Interface.... 31
Pin Descriptions - PCI Bus Interface
(65545 only) ............................................ 34
Pin Descriptions - Display Memory ............ 37
Pin Descriptions - Flat Panel Interface ........ 39
Pin Descriptions - CRT and Clock Interface 40
Pin Descriptions - Power / Gnd / Standby... 42
Register and Port Address Summaries ............ 43
I/O Map........................................................ 43
CGA, MDA, and Hercules Registers........... 44
EGA Registers ............................................. 44
VGA Registers............................................. 44
VGA Indexed Registers............................... 45
Extension Registers ..................................... 46
32-Bit Registers (65545) ............................. 49
PCI Configuration Registers (65545) .......... 50
Register Descriptions ...................................... 51
Global Control (Setup) Registers ................ 53
PCI Configuration Registers........................ 55
General Control & Status Registers............. 59
CGA / Hercules Registers............................ 61
Sequencer Registers..................................... 63
CRT Controller Registers ............................ 67
Graphics Controller Registers ..................... 81
Attribute Controller and
VGA Color Palette Registers .................. 89
Extension Registers ..................................... 95
32-Bit Registers (65545 only) ..................... 155
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