Document Outline

• Exit
• Cover Page
• 65550 Product Features
• System Diagrams
• Figure 1: System Diagram - External Interfaces
• Figure 2: Internal Data Flow
• 6555x Software Support Features
• Revision History
• Table of Contents
  • List of Tables
  • Table of Figures
• Chapter 1 Introduction/Overview
  • 1. INTRODUCTION / OVERVIEW
  • 1.1 High Performance
  • 1.2 Hardware Multimedia Support
  • 1.3 Versatile Panel Support
  • 1.4 Low Power Consumption
  • 1.5 Software Compatibility / Flexibility
  • 1.6 Display Memory Size Requirements
  • Figure 1-1: Display Memory Configurations
  • Figure 1-2: Display Memory Configurations with an STN-DD Buffer
• Chapter 2 Pin Descriptions
  • 2.0 Pin Information
  • 2.1 Pin Diagram
  • Figure 2-1: Pin Diagram
  • 2.2 Ball Grid Array: Top View
  • Figure 2-2: Top View � BGA Ball Assignments
  • 2.2 Ball Grid Array: Bottom View
  • Figure 2-3: Bottom View: BGA Ball Assignments
  • 2.3 Summary of Pin Function Changes (From 65548 to 65550)
  • 2.4 CPU Direct / VL-Bus Interface
  • Table 2- 1: Bus Output Signal Status During Standby Mode
  • 2.5 PCI Bus Interface
  • 2.6 Display Memory Interface
  • 2.7 Flat Panel Display Interface
  • 2.8 CRT & Clock Interface
  • 2.9 CRT / PANEL Signal Status During Standby Mode
  • 2.10 Display Memory Output Signal Status During Standby Mode
  • 2.11 Power / Ground and Standby Control
• Chapter 3 I/O and Memory Address Maps
  • 3.0 INTRODUCTION
  • 3.1 I/O Map
  • 3.2 Sub-Addressing Indexes and Data Ports
  • 3.3 Memory Map
  • 3.4 PCI Configuration Registers
• Chapter 4 Register Summaries
  • 4.0 Register Summaries
  • 4.1 Setup and Enable Registers
  • 4.2 Sequencer Registers
  • 4.3 Graphics Controller Registers
  • 4.4 Attribute Controller Registers
  • 4.5 VGA Color Palette Registers
  • 4.6 CRT Controller Registers
  • 4.7 PCI Configuration Registers
  • 4.8 BitBLT Registers
  • 4.9 Extension Registers
  • 4.10 Multimedia Registers
  • 4.11 Flat Panel Registers
• Chapter 5 Set Up and General Control Register Descriptions
  • 5.0 Introduction
  • 5.1 Setup and Enable Registers
    • POS102 Global Enable Register
    • VSE Video Subsystem Enable Register
  • 5.2 General Control and Status Registers
    • ST00 Input Status Register 0
    • ST01 Input Status Register 1
    • FCR Feature Control Register
    • MSR Miscellaneous Output Register
• Chapter 6 Sequencer Registers
  • 6.0 SEQUENCER REGISTERS
  • SRX Sequencer Index Register
  • SR00 Reset Register
  • SR01 Clocking Mode Register
  • SR02 Plane Mask Register
  • SR03 Character Map Select Register
  • SR04 Memory Mode Register
  • SR07 Horizontal Character Counter Reset
• Chapter 7 Graphics Controller Registers
  • 7.0 GRAPHICS CONTROLLER REGISTERS
  • GRX Graphics Controller Index Register
  • GR00 Set/Reset Register
  • GR01 Enable Set/Reset Register
  • GR02 Color Compare Register
  • GR03 Data Rotate Register
  • GR04 Read Plane Select Register
  • GR05 Graphics Mode Register
  • GR06 Miscellaneous Register
  • GR07 Color Don�t Care Register
  • GR08 Bit Mask Register
• Chapter 8 Attribute Controller Registers
  • 8.0 ATTRIBUTE CONTROLLER REGISTERS
  • ARX Attribute Controller Index Register
  • AR00-AR0F Palette Registers 0-F
  • AR10 Mode Control Register
  • AR11 Overscan Color Register
  • AR12 Memory Plane Enable Register
  • AR13 Horizontal Pixel Panning Register
  • AR14 Color Select Register
• Chapter 9 Palette DAC Registers
  • 9.0 PALETTE DAC REGISTERS
  • DACMASK Pixel Data Mask Register
  • DACSTATE DAC State Register
  • DACRX Palette Read Index Register
  • DACWX Palette Write Index Register
  • DACDATA Palette Data Register
• Chapter 10 CRT Controller Registers
  • 10 CRT CONTROLLER REGISTERS
  • CRX CRT Controller Index Register
  • CR00 Horizontal Total Register
  • CR01 Horizontal Display Enable End Register
  • CR02 Horizontal Blanking Start Register
  • CR03 Horizontal Blanking End Register
  • CR04 Horizontal Sync Start Register
  • CR05 Horizontal Sync End Register
  • CR06 Vertical Total Register
  • CR07 Overflow Register
  • CR08 Preset Row Scan Register
  • CR09 Maximum Scan Line Register
  • CR0A Text Cursor Start Register
  • CR0B Text Cursor End Register
  • CR0C Start Address High Register
  • CR0D Start Address Low Register
  • CR0E Text Cursor Location High Register
  • CR0F Text Cursor Location Low Register
  • CR10 Vertical Sync Start Register
  • CR11 Vertical Sync End Register
  • CR12 Vertical Display Enable End Register
  • CR13 Offset Register
  • CR14 Underline Location Register
  • CR15 Vertical Blanking Start Register
  • CR16 Vertical Blanking End Register
  • CR17 CRT Mode Control
  • CR18 Line Compare Register
  • CR22 Memory Read Latch Data Register
  • CR30 Extended Vertical Total Register
  • CR31 Extended Vertical Display End Register
  • CR32 Extended Vertical Sync Start Register
  • CR33 Extended Vertical Blanking Start Register
  • CR40 Extended Start Address Register
  • CR41 Extended Offset Register
  • CR70 Interlace Control Register
  • CR71 NTSC/PAL Video Output Control Register
  • CR72 Horizontal Serration 1 Start Register
  • CR73 Horizontal Serration 2 Start Register
  • CR74 NTSC/PAL Horizontal Pulse Width Register
• Chapter 11 PCI Configuration Registers
  • 11.0 PCI Configuration Registers
  • VENDID Vendor ID
  • DEVID Device ID
  • DEVCTL Device Control
  • DEVSTAT Device Status
  • REV Revision
  • PRG Register-Level Programming Interface
  • SUB Sub-Class Code
  • BASE Base Class Code
  • HDR Header Type
  • MBASE Memory Base Address
  • RBASE ROM Base Address
• Chapter 12 BitBLT Registers
  • 12.0 BITBLT REGISTERS
  • BR00 Source and Destination Offset Register
  • BR01 Pattern/Source Expansion Background Color Reg.
  • BR02 Pattern/Source Expansion Foreground Color Reg.
  • BR03 Monochrome Source Control Register
  • BR04 BitBLT Control Register
  • BR05 Pattern Address Register
  • BR06 Source Address Register
  • BR07 Destination Address Register
  • BR08 Destination Width & Height Register
  • BR09 Source Expansion Background Color Register
  • BR0A Source Expansion Foreground Color Register
• Chapter 13 Extension Registers
  • 13.0 EXTENSION REGISTERS
  • 13.1 BASIC SYSTEM CONFIGURATION
    • XR00 Vendor ID Low
    • XR01 Vendor ID High
    • XR02 Device ID Low
    • XR03 Device ID High
    • XR04 Revision ID
    • XR05 Linear Base Address Low
    • XR06 Linear Base Address High
    • XR08 Configuration
    • XR09 I/O Control
    • XR0A Address Mapping
    • XR0B Burst Write mode
    • XR0E Page Selector
  • 13.2 BitBLT ENGINE CONTROL REGISTER
    • XR20 BitBLT Engine Configuration
  • 13.3 MEMORY CONFIGURATION
    • XR40 DRAM Access Control
    • XR41 DRAM Type Register
    • XR42 DRAM Configuration Register
    • XR43 DRAM Interface Register
    • XR44 DRAM Timing Register
  • 13.4 PIN CONTROL REGISTERS
    • XR60 Video Pin Control
    • XR61 DDC Sync Select
    • XR62 GPIO Control
    • XR63 GPIO Data
    • XR67 Pin Tri-State Control
    • XR70 Configuration Pin 0
    • XR71Configuration Pin 1
  • 13.5 PIXEL PIEPLINE CONTROL
    • XR80 Pixel Pipeline Configuration 0
    • XR81 Pixel Pipeline Configuration 1
    • XR82 Pixel Pipeline Configuration 2
  • 13.6 HARDWARE CURSOR 1 & 2
    • XRA0 Cursor 1 Control Register
    • XRA1 Cursor 1 Vertical Extension Register
    • XRA2 Cursor 1 Base Address Low Register
    • XRA3 Cursor 1 Base Address High Register
    • XRA4 Cursor 1 X-Position Low Register
    • XRA5 Cursor 1 X-Position High Register
    • XRA6 Cursor 1 Y-Position Low Register
    • XRA7 Cursor 1 Y-Position High Register
    • XRA8 Cursor 2 Control Register
    • XRA9 Cursor 2 Vertical Extension Register
    • XRAA Cursor 2 Base Address Low Register
    • XRAB Cursor 2 Base Address High Register
    • XRAC Cursor 2 X-Position Low Register
    • XRAD Cursor 2 X-Position High Register
    • XRAE Cursor 2 Y-Position Low Register
    • XRAF Cursor 2 Y-Position High Register
  • 13.7 CLOCK CONTROL
    • XRC0 Video Clock 0 VCO M-Divisor
    • XRC1 Video Clock 0 VCO N-Divisor
    • XRC2 Video Clock 0 VCO M/N-Divisor MSBs
    • XRC3 Video Clock 0 Divisor Select
    • XRC4 Video Clock 1 VCO M-Divisor
    • XRC5 Video Clock 1 VCO N-Divisor
    • XRC6 Video Clock 1 VCO M/N-Divisor MSBs
    • XRC7 Video Clock 1 Divisor Select
    • XRC8 Video Clock 2 VCO M-Divisor
    • XRC9 Video Clock 2 VCO N-Divisor
    • XRCA Video Clock 2 VCO M/N-Divisor MSBs
    • XRCB Video Clock 2 Divisor Select
    • XRCC Memory Clock VCO M-Divisor
    • XRCD Memory Clock VCO N-Divisor
    • XRCE Memory Clock Divisor Select
    • XRCF Clock Configuration
  • 13.8 POWER MANAGEMENT
    • XRD0 Module PowerDown 0
    • XRD2 Down Counter
    • XRE0- XRE7 Software Flags x
    • XRF8-XRFC Test Registers
• Chapter 14 Multimedia Registers
  • 14.0 MULTIMEDIA REGISTERS
    • MR00 Module Capability
    • MR01 Secondary Capability
  • 14.1 ACQUISITION CONTROL
    • MR02 Acquisition Control 1
    • MR03 Acquisition Control 2
    • MR04 Acquisition Control 3
    • MR05 Acquisition Control 4
    • MR06 Acquisition Memory Address PTR1
    • MR07 Acquisition Memory Address PTR1
    • MR08 Acquisition Memory Address PTR1
    • MR09 Acquisition Memory Address PTR2
    • MR0A Acquisition Memory Address PTR2
    • MR0B Acquisition Memory Address PTR2
    • MR0C Acquisition Memory Width (Span)
    • MR0E Acquisition Window XLEFT
    • MR0F Acquisition Window XLEFT
    • MR10 Acquisition Window XRIGHT
    • MR11 Acquisition Window XRIGHT
    • MR12 Acquisition Window Y-TOP
    • MR13 Acquisition Window Y-TOP
    • MR14 Acquisition AQ Window Y-BOTTOM
    • MR15 Acquisition Window Y-BOTTOM
    • MR16 H-SCALE
    • MR17 V-SCALE
    • MR18 Capture Frame Count
  • 14.2 PLAYBACK CONTROL
    • MR1E Display Control 1
    • MR1F Display Control 2
    • MR20 Display Control 3
    • MR21 Double Buffer Status
    • MR22 Playback Memory Address PTR1
    • MR23 Playback Window Address PTR1
    • MR24 Playback Memory Address PTR1
    • MR25 Playback Memory Address PTR2
    • MR26 Playback Memory Address PTR2
    • MR27 Playback Memory Address PTR2
    • MR28 Playback Memory Width (Span)
    • MR2A Playback Window XLEFT
    • MR2B Playback Window XLEFT
    • MR2C Playback Window
    • MR2D Playback Window XRIGHT
    • MR2E Playback Window Y-TOP
    • MR2F Playback Window Y-TOP
    • MR30 Playback Window Y-BOTTOM
    • MR31 Playback Window Y-BOTTOM
    • MR32 H-ZOOM
    • MR33 V-ZOOM
    • MR3C Color Key Control 1
    • MR3D-3F Color Keys
    • MR40-42 Color Key Masks
    • MR43 Line Count
    • MR44 Line Count
• Chapter 15 Flat Panel Registers
  • 15.0 FLAT PANEL REGISTERS
  • FR00 Feature Register
  • FR01 CRT / FP Control
  • FR02 FP Mode Control
  • FR03 FP Dot Clock Source
  • FR04 Panel Power Sequencing Delay
  • FR05 Power Down Control 1
  • FR06 FP Power Down Control
  • FR08 FP Pin Polarity
  • FR0A Programmable Output Drive
  • FR0B FP Pin Control 1
  • FR0C Pin Control 2
  • FR0F Activity Timer Control
  • FR10 FP Format 0
  • FR11 FP Format 1
  • FR12 FP Format 2
  • FR13 FP Format 3
  • FR16 FRC Option Select
  • FR17 Polynomial FRC Control
  • FR18 FP Text Mode Control
  • FR19 Blink Rate Control
  • FR1A Frame Buffer Control
  • FR1E M (ACDCLK) Control
  • FR1F Diagnostic
  • FR20 FP Horizontal Panel Display Size LSB
  • FR21 FP Horizontal Sync Start LSB
  • FR22 FP Horizontal Sync End
  • FR23 FP Horizontal Total LSB
  • FR24 FP HSync (LP) Delay LSB
  • FR25 FP Horizontal Overflow 1
  • FR26 FP Horizontal Overflow 2
  • FR27 FP HSync (LP) Width and Disable
  • FR30 FP Vertical Panel Size LSB
  • FR31 FP Vertical Sync Start LSB (FR31)
  • FR32 FP Vertical Sync End
  • FR33 FP Vertical Total LSB
  • FR34 FP VSync (FLM) Delay LSB
  • FR35 FP Vertical Overflow 1
  • FR36 FP Vertical Overflow 2
  • FR37 FP VSync (FLM) Disable
  • FR40 Horizontal Compensation Register
  • FR41 Horizontal Stretching Register
  • FR48 Vertical Compensation Register
  • FR49�4C Text Mode Vertical Stretching 0 MSB
  • FR4D Vertical Line Replication Register
  • FR4E Selective Vertical Stretching Disable Register
• Chapter 16 Application Schematics
  • 16.0 APPLICATION SCHEMATIC EXAMPLES
  • Figure 16-1: Circuit Example PCI Bus Interface
  • Figure 16-2: Circuit Example VL BUS Interface
  • Figure 16-3: Circuit Example - VL-Bus BIOS Interface
  • Figure 16-4: Circuit Example
  • Figure 16-5: Circuit Example
  • Figure 16-6: Circuit Example 256Kx16 Display Memory Interface
  • Figure 16-7: Circuit Example 256Kx32 Display Memory Interface
  • Figure 16-8: Circuit Example 512Kx32 Display Memory Interface
  • Figure 16-9: Circuit Example CRT / Panel Display Interface
  • Figure 16-10: Circuit Example RGB-to-NTSC Encoder
• Chapter 17 Electrical Specifications
  • 17 ELECTRICAL SPECIFICATIONS
  • Table 17-1: 65550 Absolute Maximum Conditions
  • Table 17-2: 65550 Normal Operating Conditions
  • Table 17-3: 65550 DAC Characteristics
  • Table 17- 4: 65550 DC Characteristics
  • Table 17- 5: 65550 DC Drive Characteristics
  • Table 17- 6: 65550 AC Test Conditions
  • Figure 17-1: AC Test Timing
  • Table 17- 7: 65550 AC Timing Characteristics - Reference Clock
  • Figure 17-2: Reference Clock Timing
  • Table 17- 8: 65550 AC Timing Characteristics - Clock Generator
  • Figure 17-3: Clock Timing
  • Table 17- 9: 65550 AC Timing Characteristics - Reset
  • Figure 17-4: Reset Timing
  • Table 17- 10: 65550 AC Timing Characteristics - PCI Bus Frame (33 MHz)
  • Figure 17-5: PCI Bus Frame Timing
  • Table 17- 11: 65550 AC Timing Characteristics - PCI Bus Stop (33 MHz)
  • Figure 17-6: PCI Bus Stop Timing
  • Table 17- 12: 65550 AC Timing Characteristics PC BIOS ROM
  • Figure 17-7: PCI BIOS ROM Timing
  • Table 17- 13: 65550 AC Timing Characteristics - DRAM Read / Write
  • Figure 17-8: DRAM Page Mode Read Cycle Timing
  • Figure 17-9: DRAM Page Mode Write Cycle Timing
  • Table 17-14: 65550 AC Timing Characteristics - CBR Refresh
  • Figure 17-10: CAS-Before-RAS (CBR) DRAM Refresh Cycle Timing
  • Table 17-15: 65550 AC Timing Characteristics - Self Refresh
  • Figure 17-11: �Self Refresh DRAM� Refresh Cycle Timing
  • Table 17-16: 65550 AC Timing Characteristics - Video Data Port
  • Figure 17-12: Video Data Port Timing
  • Figure 17-13: CRT Output Timing
  • Table 17- 17: 65550 AC Timing Characteristics - Panel Output Timing
  • Figure 17-2: Panel Output Timing
• Chapter 18 Mechanical Specifications
  • 18.0 MECHANICAL SPECIFICATIONS
  • 18.1 Thin Quad Flat Pack (TQFP)
    • Figure 18-1: Thin Quad Flat Pack (TQFP)
  • 18.2 Plastic Quad Flat Pack
    • Figure 18-2: Plastic Quad Flat Pack
    • 18.3 256+16-Contact Ball Grid Array
    • Figure 18-3: 256+16-Contact Ball Grid Array
• Appendix A Clock Generation
  • A CLOCK GENERATION
  • A.1 Clock Synthesizer
  • A.2 Dot Clock (DCLK)
  • A.3 Memory Clock (MCLK)
  • A.4 PLL Parameters
  • Figure A-1: PLL Elements
  • A.5 Programming the Clock
  • A.6 DCLK Programming
  • A.7 MCLK Programming
  • A.8 Programming Constraints
  • A.9 Programming Example
  • A.10 PCB Layout Considerations
  • A.11 Display Memory Bandwidth
  • A.12 STN-DD Panel Buffering
  • A.13 Horizontal and Vertical Clocking
• Appendix B VGA Standard Modes
  • B.1 VGA Standard Modes
• Appendix C Panel Power Sequencing
  • C.1 PANEL POWER SEQUENCING
• Appendix D Hardware Cursor and Pop Up Window
  • D HARDWARE CURSOR AND POP UP WINDOW
  • D.1 Cursor Configuration
    • D.1.1 Basic Cursor Configuration
    • D.1.2 Base Address for Cursor Data
    • D.1.3 Cursor Vertical Extension
    • D.1.4 Cursor Colors
  • D.2 Cursor Modes
    • D.2.1 32x32x2bpp and 64x64x2bpp AND/XOR Pixel Plane Modes
      • Table D-1: Memory Organization
      • Table D-2: Memory Organization
      • Table D-3: Pixel Data 32x32x2bpp
    • D.2.2 64x64x2bpp 4-Color Mode
      • Table D-4: Memory Organization
      • Table D-5: Pixel Data
    • D.2.3 64x64x2bpp 3-Color
      • Table D-6: Memory Organization
      • Table D-7: Pixel Data
    • D.2.4 128x128x1bpp 2-Color Mode
      • Table D-8: Memory Organization
      • Table D-9: Pixel Data
    • D.2.5 The 128x128x1bpp 1-Color
      • Table D-10: Memory Organization
      • Table D-11: Pixel Bit Definitions
  • D.3 Cursor Positioning
• Appendix E BitBLT Engine
  • E. HiQVideo� � Series BitBLT Engine
    • E.1 Introduction
      • Figure E-1: Block Diagram and Data Paths of the BitBLT Engine
    • E.2 Basic BitBLT Functional Considerations
      • E.2.1 Color Depth Configuration and Color Expansion
      • E.2.2 Graphics Data Size Limitations
      • E.2.3 Bit-Wise Operations
        • Table E-1: Bit-Wise Operations and 8-bit Codes (00 - 3F)
        • Table E-2: Bit-Wise Operations and 8-bit Codes (40 - 7F)
        • Table E-3: Bit-Wise Operations and 8-bit Codes (80 - BF)
        • Table E-4: Bit-Wise Operations and 8-bit Codes (C0 - FF)
      • E.2.4 Per-Pixel Write-Masking Operations
        • Figure E-2: Block Diagram and Data Paths of the BitBLT Engine
      • E.2.5 When the Source and Destination Locations Overlap
        • Figure E-2-1: Source Corruption in BitBLT with Overlapping Source and Destination Locations
        • Figure E-2-2: Correctly Performed BitBLT with Overlapping Source and Destination Locations
        • Figure E-2-3: Suggested Starting Points for Possible Source and Destination Overlap Situations
    • E.3 Basic Graphics Data Considerations
      • E.3.1 Contiguous vs. Discontiguous Graphics Data
        • Figure E-3-1: Representation of On-Screen Single 6-Pixel Line in the Frame Buffer
        • Figure E-3-2: Representation of On-Screen 6x4 Array of Pixels in the Frame Buffer
      • E.3.2 Source Data
      • E.3.3 Monochrome Source Data
      • E.3.4 Pattern Data
        • Figure E-3-3: Pattern Data -- Always an 8x8 Array of Pixels
        • Figure E-3-4: Monochrome Pattern Data -- Occupies a Single Quadword
        • Figure E-3-5: 8bpp Pattern Data -- Occupies 64 Bytes (8 Quadwords)
        • Figure E-3-6: 16bpp Pattern Data -- Occupies 128 Bytes (16 Quadwords)
        • Figure E-3-7: 24bpp Pattern Data -- Occupies 256 Bytes (32 Quadwords)
      • E.3.5 Destination Data
    • E.4. BitBLT Programming Examples
      • E.4.1 Pattern Fill -- A Very Simple BitBLT
        • Figure E-4-1: On-Screen Destination for Example Pattern Fill BitBLT
        • Figure E-4-2: Pattern Data for Example Pattern Fill BitBLT
        • Figure E-4-3: Results of Example Pattern Fill BitBLT
      • E.4.2 Drawing Characters Using a Font Stored in System Memory
        • Figure E-4-4: On-Screen Destination for Example Character Drawing BitBLT
        • Figure E-4-5: Source Data in System Memory for Example Character Drawing BitBLT
        • Figure E-4-6: Results of Example Character Drawing BitBLT
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