ASIX ELECTRONICS CORPORATION
Frist Released Date : Sep/11/2000
2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: 886-3-579-9500
FAX: 886-3-579-9558
http://www.asix.com.tw
AX88170 L
USB to Fast Ethernet/HomePNA Controller
USB to Fast Ethernet/HomePNA Controller
Document No.: AX170-12 / V1.2 / Apr. 11 '01
Features
Single chip USB to 10/100Mbps Fast Ethernet and
1/10Mbps HomePNA Network Controller
Compliant with USB specification 1.0 and 1.1
Full Speed USB Device with bus power capability
USB Communication Class Spec 1.0 Compliant
Support 4 endpoints on USB
IEEE 802.3u 100BASE-T, TX, and T4 Compatible
Embedded 5K*16 bit SRAM
Support both full-duplex or half-duplex operation on
Fast Ethernet
Provides a MII port for both Ethernet and
HomePNA PHY interface
Supports suspended mode and remote wakeup
(link_up or magic packet)
Optional PHY power down mode for power saving
Provides optional MII/RMII interface with PHY
mode for multiple ports USB-to-USB bridge
application.
Support 256/512 bytes serial EEPROM (used for
saving USB Descriptors)
Support automatic loading of Ethernet ID, USB
Descriptors and Adapter Configuration from
EEPROM on power-on initialization
External PHY loop-back diagnostic capability
Small form factor 64-pin LQFP package
48MHz and 25MHz Operation, pure 3.3V operation
with I/O 5V tolerance
*IEEE is a registered trademark of the Institute of Electrical and
Electronic Engineers, Inc.
*All other trademarks and registered trademark are the property of
their respective holders.
Product description
The AX88170 USB to Fast Ethernet/HomePNA Controller is a high performance and highly integrated Controller with
embedded 5K*16 bit SRAM. The AX88170 contains a USB interface to host CPU and compliant with USB Standard V1.0 and
V1.1. The interface between AX88170 and PC Host is compliant with USB Communication Class Specification 1.0. The
AX88170 could be used for both 10M/100Mbps Fast Ethernet function based on IEEE802.3 / IEEE802.3u LAN standard and
1M/10M HomePNA standard. The AX88170 supports media-independent interface (MII) or RMII (Reduce MII) interface to
simplify the design on implementing Fast Ethernet and HomePNA functions. The chip also provides an optional MII/RMII
interface with PHY mode, combine with Ethernet repeater or switch IC can build a multiple ports USB-to-USB bridge
application.
System Block Diagram
Always contact ASIX for possible updates before starting a design.
This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without
notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
AX88170
10/100 Mbps Ethernet
PHY/TxRx
MAGNETIC
RJ45
USB I/F
EEPROM
1/10 Mbps
Home LAN PHY
MAGNETIC
RJ11
ASIX ELECTRONICS CORPORATION
2
CONFIDENTIAL
AX88170 PRELIMINARY
CONTENTS
1.0 INTRODUCTION...........................................................................................................................................................................4
1.1 G
ENERAL
D
ESCRIPTION
:............................................................................................................................................................ 4
1.2 AX88170 B
LOCK
D
IAGRAM
:...................................................................................................................................................... 4
1.3 AX88170 P
IN
C
ONNECTION
D
IAGRAM WITH
MII I
NTERFACE
........................................................................................... 5
1.4 AX88170
P
IN
C
ONNECTION
D
IAGRAM WITH
RMII I
NTERFACE
......................................................................................... 6
2.0 SIGNAL DESCRIPTION...............................................................................................................................................................7
2.1 USB B
US
I
NTERFACE
S
IGNALS
G
ROUP
.................................................................................................................................... 7
2.2 EEPROM S
IGNALS
G
ROUP
......................................................................................................................................................... 7
2.3
A
MII
INTERFACE SIGNALS GROUP
(MAC
MODE
) .................................................................................................................. 7
2.3
B
MII
INTERFACE SIGNALS GROUP
(PHY
MODE
)..................................................................................................................... 8
2.4 RMII
INTERFACE SIGNAL PINS
(PHY
MODE
) .......................................................................................................................... 9
2.5 M
ISCELLANEOUS PINS GROUP
................................................................................................................................................... 9
3.0 EEPROM MEMORY MAPPING...............................................................................................................................................11
4.0 USB COMMANDS .......................................................................................................................................................................12
4.1 USB
STANDARD COMMANDS
................................................................................................................................................... 12
4.2 USB C
OMMUNICATION
C
LASS
C
OMMANDS
......................................................................................................................... 13
4.3 USB V
ENDOR
C
OMMANDS
....................................................................................................................................................... 14
5.0 USB CONFIGURATION STRUCTURE...................................................................................................................................16
5.1 USB C
ONFIGURATION
. ............................................................................................................................................................. 16
5.2 USB I
NTERFACE
C
LASS
. ........................................................................................................................................................... 16
5.3 USB E
NDPOINTS
........................................................................................................................................................................ 16
6.0 ELECTRICAL SPECIFICATION AND TIMINGS .................................................................................................................17
6.1 A
BSOLUTE
M
AXIMUM
R
ATINGS
............................................................................................................................................ 17
6.2 G
ENERAL
O
PERATION
C
ONDITIONS
...................................................................................................................................... 17
6.3 DC
C
HARACTERISTICS
.............................................................................................................................................................. 17
6.4 A.C. T
IMING
C
HARACTERISTICS
............................................................................................................................................. 18
6.4.1 25M_XIN............................................................................................................................................................................18
6.4.2 48M_XIN............................................................................................................................................................................18
6.4.3 Reset Timing......................................................................................................................................................................18
6.4.4 MII Timing of MAC mode................................................................................................................................................20
6.4.5 MII Timing of PHY mode .................................................................................................................................................21
6.4.6 RMII Interface Timing of PHY Mode.............................................................................................................................22
6.4.7 STATION MANAGEMENT TIMING..............................................................................................................................23
6.4.8 SERIAL EEPROM TIMING.............................................................................................................................................24
7.0 PACKAGE INFORMATION.......................................................................................................................................................25
APPENDIX A: SYSTEM APPLICATIONS ....................................................................................................................................26
A.1 USB
TO
F
AST
E
THERNET
C
ONVERTER
................................................................................................................................ 26
A.2 USB
TO
F
AST
E
THERNET AND
/
OR
H
OME
LAN C
OMBO SOLUTION
................................................................................ 27
A.3 USB-
TO
-USB
OR
USB-
TO
-E
THERNET
B
RIDGE THROUGH
E
THERNET
R
EPEATER
C
ONTROLLER
............................ 28
A.4 USB-
TO
-USB
OR
USB-
TO
-E
THERNET
B
RIDGE THROUGH
E
THERNET
S
WITCH
C
ONTROLLER
................................. 28
DEMONSTRATION CIRCUIT A: AX88170 + ETHERNET PHY.............................................................................................29
DEMONSTRATION CIRCUIT B: AX88170 + HOMEPNA 1M8 PHY ....................................................................................31
DEMONSTRATION CIRCUIT C: 4 USB PORTS + 1 ETHERNET PORT BRIDGE AP.....................................................33
ASIX ELECTRONICS CORPORATION
3
CONFIDENTIAL
AX88170 PRELIMINARY
FIGURES
F
IG
- 1 AX88170 B
LOCK
D
IAGRAM
..................................................................................................................................................... 4
F
IG
- 2 AX88170 P
IN
C
ONNECTION
D
IAGRAM WITH
MII I
NTERFACE
......................................................................................... 5
F
IG
-
3 AX88170 P
IN
C
ONNECTION
D
IAGRAM
RMII I
NTERFACE
.................................................................................................. 6
TABLES
T
AB
- 1 USB
BUS INTERFACE SIGNALS GROUP
.................................................................................................................................. 7
T
AB
- 2 EEPROM
BUS INTERFACE SIGNALS GROUP
......................................................................................................................... 7
T
AB
- 3 MII
INTERFACE SIGNALS GROUP
(MAC
MODE
) ................................................................................................................. 8
T
AB
- 4 MII
INTERFACE SIGNALS GROUP
(PHY
MODE
) ................................................................................................................... 8
T
AB
- 5 RMII
INTERFACE SIGNAL PINS
(PHY
MODE
)....................................................................................................................... 9
T
AB
- 6 M
ISCELLANEOUS PINS GROUP
............................................................................................................................................. 10
T
AB
- 7 EEPROM M
EMORY
M
APPING
............................................................................................................................................. 11
ASIX ELECTRONICS CORPORATION
4
CONFIDENTIAL
AX88170 PRELIMINARY
1.0 Introduction
1.1 General Description:
The AX88170 USB to Fast Ethernet Controller is a high performance and highly integrated USB bus Ethernet Controller with
embedded 5K*16 bit SRAM. The AX88170 contains a full speed USB interface to host CPU and compliant with USB
Communication Class Spec. 1.0. The AX88170 implements both 10Mbps and 100Mbps Ethernet function based on
IEEE802.3 / IEEE802.3u LAN standard. The AX88170 supports media-independent interface (MII) or RMII (Reduce MII)
interface to simplify the design on implementing Fast Ethernet and HomePNA functions. The chip also provides an optional
MII/RMII interface with PHY mode, combines with Ethernet repeater or switch IC can build a multiple ports USB-to-USB
bridge application.
AX88170 uses 64-pin LQFP low profile package, 48MHz operation for USB and 25MHz operation for Ethernet, CMOS
process with pure 3.3V operation and 5 Volt I/O tolerance.
1.2 AX88170 Block Diagram:
Fig 1 AX88170 Block Diagram
MAC
Core
Memory Arbiter
USB to
Ethernet
Bridge
USB Core and Interface
STA
SEEPROM
Loader I/F
D-/D+
MII I/F
Or
RMII I/F
SMDC
SMDIO
EECS
EECK
EEDI
EEDO
5K* 16
SRAM
ASIX ELECTRONICS CORPORATION
5
CONFIDENTIAL
AX88170 PRELIMINARY
1.3 AX88170 Pin Connection Diagram with MII Interface
The AX88170 is housed in the 64-pin plastic light quad flat pack. See
Fig 2 AX88170 Pin Connection
Diagram
.
Fig 2 AX88170 Pin Connection Diagram with MII Interface
1
5 6
4
7
2 3
8 9 10 11 12 13 14 15 16
30
29
28
24
23
25
27
26
ASIX
22
18
17
19
31
21
20
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
64
63
61
62
60
59
58
57
56
55
54
50
49
COL
TEST0
VSS
VDD
/RST
VSS
VDD
VSS
VDD
VDD
VSS
RXD0
RXD1
RXD2
RXD3
RX_ER
RX_DV
TXD0
TXD1
TXD2
TXD3
CRS TX_CLK
25M_XIN
VSS
VDD
52
53
51
VSS
VSS
D+
/S_RMII
/S_MAC
/S_FDPX
SPD_UP
EECS
AX88170
RX_CLK
TX_EN
TEST1
TEST2
D-
MDC
MDIO
/PHY_RST
25M_CLKO
25M_XOUT
48M_XIN
48M_XOUT
EECK
EEDI
EEDO
VSS
VDD
VDD
VDD
VSS
TEST3
LD_RDY
TEST_OUT
VDD
S_EXT
ACT/LINK
TEST4
(MII Interface)
GPIO0
GPIO1
/HomeLink
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