AX88780
High-Performance Non-PCI Single-Chip
32-bit 10/100M Fast Ethernet Controller
Document No: AX88780/V1.0/10/4/05
Features
High-performance non-PCI local bus
16/32-bit SRAM-like host interface
Support big/little endian data bus type
Large embedded SRAM for packet buffers
32K bytes for receive buffer
8K bytes for transmit buffer
Support IP/TCP/UDP checksum offloads
Support interrupt with high or low active trigger
mode
Single-chip Fast Ethernet controller
Compatible with IEEE802.3, 802.3u standards
Integrated Fast Ethernet MAC/PHY transceiver in
one chip
Support 10Mbps and 100Mbps data rate
Support full and half duplex operations
Support 10/100Mbps N-way Auto-negotiation
operation
Support IEEE 802.3x flow control for full-duplex
operation
Support back-pressure flow control for half-duplex
operation
Support packet length set by software
Support optional MII interface for Ethernet PHY
and HomePNA/HomePlug PHY applications
Support Wake-on-LAN function by following events
Detection of a change in the network link state
Receipt of a Magic Packet
Support optional EEPROM interface
Support PCMCIA in 16-bit mode
Support system reference clock from 40MHz to
100MHz
Support LED pins for various network activity
indications
Integrated voltage regulator and 25MHz crystal
oscillator
3.3V power supply with 5V I/O tolerance
128-pin LQFP with CMOS process, RoHS package
US patent approved
Product Description
The AX88780 is a high-performance and cost-effective single-chip Fast Ethernet controller for various embedded
systems
including
consumer electronics and home network markets that require a higher level of network connectivity.
The AX88780 supports 16/32-bit SRAM-like host interface and integrates on-chip Fast Ethernet MAC and PHY, which
is IEEE802.3 10Base-T and IEEE802.3u 100Base-T compatible. The AX88780 supports full-duplex or half-duplex
operation at 10/100Mbps speed with auto-negotiation or manual setting. The AX88780 integrates large embedded SRAM
for packet buffers to accommodate high bandwidth applications and supports IP/TCP/UDP checksum to offload
processing loading from microprocessor/microcontroller in an embedded system.
System Block Diagram
Always contact ASIX for possible updates before starting a design.
This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product
specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent
accompany the sale of the product.
ASIX ELECTRONICS CORPORATION
Released Date: 10/4/2005
4F, NO.8, Hsin Ann Rd., Science-Based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: 886-3-579-9500
FAX: 886-3-579-9558
http://www.asix.com.tw/
AX88780
Target Applications
Multimedia applications
Content distribution application
Audio distribution system (Whole-house audio)
Video-over IP solutions, IP PBX and video phone
Video distribution system, multi-room PVR
Cable, satellite, and IP set-top box
Digital video recorder
DVD
recorder/player
High
definition
TV
Digital media client/server
Home
gateway
IPTV for triple play
Others
Printer, kiosk, security system
Wireless router & access point
Applications
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AX88780
Content
1.0 Introduction.......................................................................................................................................................................6
1.1 General Description .......................................................................................................................................................6
1.2 AX88780 Block Diagram...............................................................................................................................................6
1.3 AX88780 Pinout Diagram..............................................................................................................................................7
2.0 Signal Description .............................................................................................................................................................8
2.1 Signal Type Definition ...................................................................................................................................................8
2.2 Host Interface.................................................................................................................................................................8
2.3 EEPROM Interface (Optional).......................................................................................................................................9
2.4 Regulator Interface.......................................................................................................................................................10
2.5 10/100M PHY Interface ...............................................................................................................................................10
2.6 MII Interface (optional)................................................................................................................................................10
2.7 Miscellaneous ..............................................................................................................................................................11
2.8 Power/ground pin.........................................................................................................................................................11
3.0 Functional Description ...................................................................................................................................................12
3.1 Host Interface...............................................................................................................................................................12
3.2 System Address Range.................................................................................................................................................12
3.3 TX Buffer Operation ....................................................................................................................................................12
3.4 RX Buffer Operation....................................................................................................................................................12
3.5 Flow Control ................................................................................................................................................................13
3.6 Checksum Offloads and Wake-up ................................................................................................................................13
3.7 Fast-Mode support .......................................................................................................................................................13
3.8 Big/Little-endian support .............................................................................................................................................13
3.9 10/100BASE-TX PHY.................................................................................................................................................13
3.10 16-bit Mode................................................................................................................................................................14
3.11 EEPROM Format .......................................................................................................................................................14
4.0 Register Description........................................................................................................................................................16
4.1 CMD--Command Register ...........................................................................................................................................17
4.2 IMR--Interrupt Mask Register .....................................................................................................................................17
4.3 ISR--Interrupt Status Register......................................................................................................................................18
4.4 TX_CFG--TX Configuration Register .........................................................................................................................19
4.5 TX_CMD--TX Command Register .............................................................................................................................19
4.6 TXBS--TX Buffer Status Register ...............................................................................................................................19
4.7 PHY_CTRL-- Internal PHY Control Register .............................................................................................................20
4.8 TXDES0--TX Descriptor0 Register.............................................................................................................................21
4.9 TXDES1--TX Descriptor1 Register.............................................................................................................................21
4.10 TXDES2--TX Descriptor2 Register...........................................................................................................................21
4.11 TXDES3--TX Descriptor3 Register ...........................................................................................................................22
4.12 RX_CFG--RX Configuration Register.......................................................................................................................22
4.13 RXCURT--RX Current Pointer Register ....................................................................................................................22
4.14 RXBOUND--RX Boundary Pointer Register ............................................................................................................23
4.15 MAC_CFG0--MAC Configuration0 Register............................................................................................................23
4.16 MAC_CFG1--MAC Configuration1 Register............................................................................................................23
4.17 MAC_CFG2--MAC Configuration2 Register............................................................................................................24
4.18 MAC_CFG3--MAC Configuration3 Register............................................................................................................24
4.19 TXPAUT--TX Pause Time Register ...........................................................................................................................24
4.20 RXBTHD0--RX buffer Threshold0 Register .............................................................................................................25
4.21 RXBTHD1--RX Buffer Threshold1 Register ............................................................................................................25
4.22 RXFULTHD--RX Buffer Full Threshold Register.....................................................................................................25
4.23 MISC--Misc. Control Register .................................................................................................................................25
4.24 MACID0--MAC ID0 Register ...................................................................................................................................26
4.25 MACID1--MAC ID1 Register ...................................................................................................................................26
4.26 MACID2--MAC ID2 Register ...................................................................................................................................26
4.27 TXLEN--TX Length Register ....................................................................................................................................26
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AX88780
4.28 RXFILTER--RX Packet Filter Register .....................................................................................................................27
4.29 MDIOCTRL--MDIO Control Register ......................................................................................................................27
4.30 MDIODP--MDIO Data Port Register ........................................................................................................................28
4.31 GPIO_CTRL--GPIO Control Register.......................................................................................................................28
4.32 RXINDICATOR--Receive Indicator Register............................................................................................................28
4.33 TXST--TX Status Register .........................................................................................................................................29
4.34 MDCLKPAT--MDC Clock Pattern Register ..............................................................................................................29
4.35 RXCHKSUMCNT--RX IP/UDP/TCP Checksum Error Counter...............................................................................29
4.36 RXCRCNT--RX CRC Error Counter.........................................................................................................................29
4.37 TXFAILCNT--TX Fail Counter .................................................................................................................................30
4.38 PROMDPR--EEPROM Data Port Register ...............................................................................................................30
4.39 PROMCTRL--EEPROM Control Register................................................................................................................30
4.40 MAXRXLEN--Max. RX Packet Length Register......................................................................................................30
4.41 HASHTAB0--Hash Table0 Register ..........................................................................................................................31
4.42 HASHTAB1--Hash Table1 Register ..........................................................................................................................31
4.43 HASHTAB2--Hash Table2 Register ..........................................................................................................................31
4.44 HASHTAB3--Hash Table3 Register ..........................................................................................................................31
4.45 DOGTHD0--Watch Dog Timer Threshold0 Register ...............................................................................................31
4.46 DOGTHD1--Watch Dog timer Threshold1 Register ................................................................................................32
5.0 PHY Register...................................................................................................................................................................33
5.1 BMCR--Basic Mode Control Register.........................................................................................................................33
5.2 BMSR--Basic Mode Status Register............................................................................................................................34
5.3 PHYIDR0--PHY Identifier 0 Register .........................................................................................................................34
5.4 PHYIDR1--PHY Identifier 1 Register .........................................................................................................................35
5.5 ANAR--Auto-negotiation Advertisement Register ......................................................................................................35
5.6 ANLPAR--Auto-negotiation Link Partner Ability Register .........................................................................................35
5.7 ANER--Auto-negotiation Expansion Register .............................................................................................................36
6.0 Electrical Specification and Timings..........................................................................................................................37
6.1 DC Characteristics .......................................................................................................................................................37
6.1.1 Absolute Maximum Ratings..................................................................................................................................37
6.1.2 General Operation Conditions.............................................................................................................................37
6.1.3 Leakage Current and Capacitance.......................................................................................................................37
6.1.4 DC Characteristics of 2.5V IO Pins .....................................................................................................................37
6.1.5 DC Characteristics of 3.3V IO Pins .....................................................................................................................38
6.1.6 Transmission Characteristics ...............................................................................................................................38
6.1.7 Reception Characteristics ....................................................................................................................................38
6.1.8 Power Consumption .............................................................................................................................................39
6.1.9 Thermal Characteristics.......................................................................................................................................39
6.2 A.C. Timing Characteristics .........................................................................................................................................40
6.2.1 Host Clock............................................................................................................................................................40
6.2.2 Reset Timing .........................................................................................................................................................40
6.2.3 Host Single Write Timing...................................................................................................................................40
6.2.4 Host Fast Write Timing.........................................................................................................................................41
6.2.5 Host Single Read Timing ......................................................................................................................................41
6.2.6 Host Fast Read Timing .........................................................................................................................................41
6.2.7 MII Receive Timing (100Mb/s).............................................................................................................................42
6.2.8 MII Transmit Timing (100Mbps) ..........................................................................................................................42
6.2.9 MDIO Timing .......................................................................................................................................................43
6.2.10 Serial EEPROM Timing .....................................................................................................................................44
7.0 Package Information ......................................................................................................................................................45
Ordering Information...........................................................................................................................................................46
Appendix................................................................................................................................................................................47
Revision History....................................................................................................................................................................48
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List of Figures
Figure 1 : AX88780 block diagram .......................................................................................................................................6
Figure 2 : AX88780 pin connection diagram.........................................................................................................................7
Figure 3 : 32-bit mode address mapping..............................................................................................................................12
Figure 4 : data swap block ...................................................................................................................................................13
Figure 5 : 16-bit mode map block........................................................................................................................................14
Figure 6 : Transmit waveform specification ........................................................................................................................38
List of Tables
Table 1 : Host Interface signals group ...................................................................................................................................8
Table 2 : EEPROM Interface signals group...........................................................................................................................9
Table 3 : Regulator signals group ........................................................................................................................................10
Table 4 : 10/100M Twisted-pair signals group.....................................................................................................................10
Table 5 : MII Interface signals group...................................................................................................................................10
Table 6 : Miscellaneous signals group ................................................................................................................................. 11
Table 7 : Power/Ground pins group ..................................................................................................................................... 11
Table 8 : MAC Register Mapping........................................................................................................................................16
Table 9 : PHY Register Mapping .........................................................................................................................................33
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