ASIX ELECTRONICS CORPORATION
2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: 886-3-579-9500
FAX: 886-3-579-9558
http://www.asix.com.tw
AX88871AP
10/100BASE Dual Speed Bripeater Controller
ASIX
ASIX AX88871AP
10/100BASE
Dual Speed "Bripeater" Controller
Data Sheets (08/11/' 99)
DOCUMENT NO. : AX871A-05.DOC
This data sheets contain new products information. ASIX ELECTRONICS reserves the rights to modify the products
specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent
accompany the sale of the product.
Always contact ASIX for possible updates
before starting a design.
AX88871AP Bripeater
ASIX ELECTRONICS CORPORATION
2
CONTENTS
1.0 AX88871A OVERVIEW..................................................................................................................................... 4
1.1 G
ENERAL
D
ESCRIPTION
...................................................................................................................................... 4
1.2 F
EATURES
.......................................................................................................................................................... 5
1.3 B
LOCK
D
IAGRAM
............................................................................................................................................... 6
1.4 P
IN
C
ONNECTION
D
IAGRAM
(
MODE
0)................................................................................................................. 7
1.5 P
IN
C
ONNECTION
D
IAGRAM
(
MODE
1)................................................................................................................. 8
2.0 PIN DESCRIPTION ........................................................................................................................................... 9
2.1 MII
INTERFACES
................................................................................................................................................ 9
2.2 E
XPANSION
B
US
I
NTERFACE FOR
100 M
BPS
....................................................................................................... 10
2.3 LED D
ISPLAY
.................................................................................................................................................. 11
2.4 B
UFFER MEMORY PINS GROUP
........................................................................................................................... 12
2.5 M
ISCELLANEOUS
.............................................................................................................................................. 13
2.6 P
OWER ON CONFIGURATION SETUP SIGNALS CROSS REFERENCE TABLE
................................................................ 14
3.0 FUNCTIONAL DESCRIPTION ..................................................................................................................... 15
3.1 R
EPEATER
S
TATE
M
ACHINE
.............................................................................................................................. 16
3.2 RXE /TXE CONTROL .................................................................................................................................. 16
3.3 J
ABBER
S
TATE
M
ACHINE
.................................................................................................................................. 17
3.4 P
ARTITION
S
TATE
M
ACHINE
............................................................................................................................. 17
3.5 E
XPANSION
L
OGIC
(C
ASCADE
I
NTERFACE
) ......................................................................................................... 17
3.6 D
ATA
F
LOW CONTROL
...................................................................................................................................... 17
3.7 RID R
ECEIVE
-T
RANSMIT
I
NTERFACE
(D
AISY
C
HAIN
L
OGIC
)............................................................................... 18
3.8 LED D
ISPLAY
I
NTERFACE
................................................................................................................................ 18
4.0 INTERNAL REGISTERS ................................................................................................................................ 20
4.1 C
ONFIGURATION
R
EGISTER
(CONFIG) ............................................................................................................. 20
4.2 R
EPEATER
ID R
EGISTER
................................................................................................................................... 20
5.0 ELECTRICAL SPECIFICATION AND TIMING.......................................................................................... 21
5.1 A
BSOLUTE
M
AXIMUM
R
ATINGS
........................................................................................................................ 21
5.2 G
ENERAL
O
PERATION
C
ONDITIONS
................................................................................................................... 21
5.3 DC C
HARACTERISTICS
..................................................................................................................................... 21
5.4 AC
SPECIFICATIONS
......................................................................................................................................... 22
5.4.1 MII Interface Timing Tx & Rx ................................................................................................................. 22
5.4.2 Expansion Bus ......................................................................................................................................... 23
5.4.3 SRAM read cycle and write cycle ............................................................................................................. 24
5.4.4 LED DISPLAY ......................................................................................................................................... 25
5.4.5 LED Display After Reset ......................................................................................................................... 25
5.4.6 Repeater ID Daisy Chain ......................................................................................................................... 26
6.0 PACKAGE INFORMATION........................................................................................................................... 27
APPENDIX A: APPLICATIONS.......................................................................................................................... 28
A.1 S
TAND
-
ALONG
8-
PORTS
10/100M
BPS
HUB A
PPLICATION
................................................................................. 28
A.2 M
ULTIPLE
S
TAND
-
ALONG
HUB C
ASCADE
A
PPLICATION
(
OLD STACK SCHEME
) .................................................. 28
A.3 M
ULTIPLE
S
TAND
-
ALONG
HUB C
ASCADE
A
PPLICATION
(N
EW STACK SCHEME
) ................................................. 29
APPENDIX B: USING MII I/F CONNECTS TO MAC ...................................................................................... 30
AX88871AP Bripeater
ASIX ELECTRONICS CORPORATION
3
FIGURES
F
IG
- 1 C
HIP
B
LOCK
D
IAGRAM
..................................................................................................................................... 6
F
IG
- 2 P
IN
C
ONNECTION
D
IAGRAM FOR MODE
0 ........................................................................................................... 7
F
IG
- 3 P
IN
C
ONNECTION
D
IAGRAM FOR MODE
1 ........................................................................................................... 8
F
IG
- 4 F
UNCTIONAL
B
LOCK
D
IAGRAM
....................................................................................................................... 15
F
IG
- 5 A
PPLICATION FOR
LED
DISPLAY
..................................................................................................................... 19
F
IG
- 6 S
TAND
-
ALONG
8-
PORTS
10/100M
BPS
HUB A
PPLICATION
................................................................................ 28
F
IG
- 7 M
ULTIPLE
S
TAND
-
ALONG
HUB C
ASCADE
A
PPLICATION WITH OLD CASCADE METHOD
....................................... 28
F
IG
- 8 M
ULTIPLE
S
TAND
-
ALONG
HUB C
ASCADE
A
PPLICATION WITH NEW CASCADE METHOD
...................................... 29
AX88871AP Bripeater
ASIX ELECTRONICS CORPORATION
4
1.0 AX88871A Overview
The AX88871A 10/100Mbps Dual Speed "Bripeater" Controller is "a dual speed
repeater with build in bridge function" It is design for low cost dumb HUB application. The
AX88871A directly supports up-to eight 10/100Mbps automatic links MII interfaces. Maximum
up-to 192 ports can be constructed when using inter-repeater bus horizontally cascades 4
AX88871A and vertically cascades 6 repeaters. When using the legacy method, maximum up-to
64 ports can be constructed when using expansion bus cascades 8 AX88871As. The AX88871A
is designed base on IEEE 802.3u clause 27 " Repeater for 100Mb/s base-band networks" It is
fully compatible with IEEE 802.3u standard.
All of the ASIX repeater products with the same speeds has the same cascade
methodology. So the AX88871A can cascade with AX88850, AX88860 and AX88870 series
chips. That is ASIX maintain the consistency of the cascade method for all the repeater product
line.
1.1 General Description
The AX88871A Repeater Controller is a subset of a repeater set containing all the
repeater-specific components and functions, exclusive of PHY components and functions. The
AX88871A has only Media Independent Interface (MII) to connect to PHY devices. Other then
AX88850 series chips that has 2 kinds of interfaces. There are Physical coding sub-layer (PCS)
interface and Media Independent Interface (MII).
The AX88871A supports 8 MII interfaces ports, a bridge packet buffer SRAM interface, a
100Mbps port expansion interface and LED display interface.
The AX88871A supports stand along 10/100Mbps dual speed repeater applications. Also
it can expand the ports count via cascade to other AX88850 and AX88860 pure 100Mbps
repeater chips..
The AX88871A has two application mode.
Mode 0
Single chip repeater application.
Mode 1
Multiple chips cascaded repeater application.
AX88871AP Bripeater
ASIX ELECTRONICS CORPORATION
5
1.2 Features
IEEE 802.3u repeater compatible
Supports per port 10/100Mbps alternative with auto detected
Build in 10/100Mbps Bridge engine with following features
1.
Minimum 32K bytes, maximum 256K bytes SRAM to buffer packets
2.
Seamless buffer management without waste any space of buffer memory
3.
Simple asynchronous 8-bit SRAM interface to reduce system cost
4.
256 or 1024 entries is supported
5.
Auto learning and filtering
6.
Two forwarding modes are supported : Store-n-Forward and fragment-free
7.
Flow-control is supported optionally.
8.
Buffer RAM auto testing
9.
Routing and Learning at wire speed (148810 packets/sec at 100Mbps)
Supports 8 10/100Mbps network connections
8 dedicated MII interfaces can support 100BASE-TX/T4/FX PHY interfaces
Port 7 and/or 8 can connect to bridge, switch or MAC type device optionally.
Up-to 8 repeater chips can be cascaded for large HUB application(old method)
Up-to 6 repeaters can be cascaded for vertical expansion(new feature)
Up-to 4 chips can be cascaded locally for horizontal expansion(new feature)
Support two application mode : single or cascade
Low latency design supports Class II repeater implementation with large port number
All ports can be separately isolated or partitioned in response to fault condition
Separate jabber and partition state machines for each port
Per-port LED display for Jabber, Partition, Activity. Global partition, RAM test fail and
collision, utilization (%) for 10/100Mbps presentation
Power on LED diagnosis. All the LED display will follow the "ON-OFF-ON-OFF-Normal"
operation procedure during/after power on reset
208-pin PQFP
PDF 
ZIP