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Электронный компонент: AX88875A

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ASIX ELECTRONICS CORPORATION
2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: 886-3-579-9500
FAX: 886-3-579-9558
http://www.asix.com.tw
AX88875AP
10/100BASE Dual Speed Bripeater Controller
ASIX
ASIX AX88875AP
10/100BASE 5-Port
Dual Speed "Bripeater" Controller
Data Sheets (10/16/'00)
DOCUMENT NO. : AX875A-06.DOC
This data sheets contain new products information. ASIX ELECTRONICS reserves the rights to modify the products
specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent
accompany the sale of the product.
Always contact ASIX for possible updates
before starting a design.
AX88875AP Bripeater
ASIX ELECTRONICS CORPORATION
2
CONTENTS
1.0 AX88875A OVERVIEW..................................................................................................................................... 3
1.1 G
ENERAL
D
ESCRIPTION
...................................................................................................................................... 3
1.2 F
EATURES
.......................................................................................................................................................... 4
1.3 B
LOCK
D
IAGRAM
............................................................................................................................................... 5
1.4 P
IN
C
ONNECTION
D
IAGRAM
(M
ODE
0) ................................................................................................................ 6
1.5 P
IN
C
ONNECTION
D
IAGRAM
(M
ODE
1) ................................................................................................................ 7
2.0 PIN DESCRIPTION ........................................................................................................................................... 8
2.1 MII
INTERFACES
................................................................................................................................................ 8
2.2 LED D
ISPLAY
.................................................................................................................................................... 9
2.3 B
UFFER MEMORY PINS GROUP
........................................................................................................................... 10
2.4 M
ISCELLANEOUS
.............................................................................................................................................. 11
2.5 P
OWER ON CONFIGURATION SETUP SIGNALS CROSS REFERENCE TABLE
................................................................ 12
3.0 FUNCTIONAL DESCRIPTION ..................................................................................................................... 13
3.1 R
EPEATER
S
TATE
M
ACHINE
.............................................................................................................................. 13
3.2 RXE /TXE CONTROL ................................................................................................................................... 13
3.3 J
ABBER
S
TATE
M
ACHINE
.................................................................................................................................. 14
3.4 P
ARTITION
S
TATE
M
ACHINE
............................................................................................................................. 14
3.5 LED D
ISPLAY
I
NTERFACE
................................................................................................................................ 14
4.0 INTERNAL REGISTERS ................................................................................................................................ 16
4.1 C
ONFIGURATION
R
EGISTER
(CONFIG) ............................................................................................................. 16
5.0 ELECTRICAL SPECIFICATION AND TIMING.......................................................................................... 17
5.1 A
BSOLUTE
M
AXIMUM
R
ATINGS
........................................................................................................................ 17
5.2 G
ENERAL
O
PERATION
C
ONDITIONS
................................................................................................................... 17
5.3 DC C
HARACTERISTICS
..................................................................................................................................... 17
5.4 AC
SPECIFICATIONS
......................................................................................................................................... 18
5.4.1 MII Interface Timing Tx & Rx .................................................................................................................. 18
5.4.2 SRAM read cycle and write cycle ............................................................................................................. 19
5.4.3 LED DISPLAY ......................................................................................................................................... 20
5.4.4 LED Display After Reset .......................................................................................................................... 20
6.0 PACKAGE INFORMATION........................................................................................................................... 21
APPENDIX A: APPLICATIONS.......................................................................................................................... 22
A.1 S
TAND
-
ALONG
5-
PORTS
10/100M
BPS
HUB A
PPLICATION
................................................................................. 22
A.2 S
TAND
-
ALONG
4-
PORTS
10/100M
BPS
HUB
WITH ONE
MAC A
PPLICATION
........................................................ 22
APPENDIX B: USING MII I/F CONNECTS TO MAC ...................................................................................... 23
FIGURES
F
IG
- 1 C
HIP
B
LOCK
D
IAGRAM
..................................................................................................................................... 5
F
IG
- 2 P
IN
C
ONNECTION
D
IAGRAM
(M
ODE
0) .............................................................................................................. 6
F
IG
- 3 P
IN
C
ONNECTION
D
IAGRAM
(M
ODE
1) .............................................................................................................. 7
F
IG
- 4 A
PPLICATION FOR
LED
DISPLAY
..................................................................................................................... 15
F
IG
- 5 S
TAND
-
ALONG
5-
PORTS
10/100M
BPS
HUB A
PPLICATION
................................................................................ 22
F
IG
- 6 S
TAND
-
ALONG
4-
PORTS
10/100M
BPS
HUB
WITH ONE
MAC A
PPLICATION
....................................................... 22
AX88875AP Bripeater
ASIX ELECTRONICS CORPORATION
3
1.0 AX88875A Overview
The AX88875A 10/100Mbps Dual Speed "Bripeater" Controller is "a dual speed
repeater with build in bridge function" It is design for low cost dumb HUB application. The
AX88875A directly supports up-to five 10/100Mbps automatic links MII interfaces specially for
SOHO market. The AX88875A is designed base on IEEE 802.3u clause 27 " Repeater for
100Mb/s base-band networks" It is fully compatible with IEEE 802.3u standard.
1.1 General Description
The AX88875A Repeater Controller is a subset of a repeater set containing all the
repeater-specific components and functions, exclusive of PHY components and functions. The
AX88875A has five Media Independent Interfaces (MII) to connect to PHY or MAC devices.
The AX88875A supports 5 MII interfaces ports, a bridge packet buffer SRAM interface
and LED display interface. AX88875A without support expansion port to cascade to other
AX88850 and AX88860 pure 100Mbps repeater chips..
The AX88875A supports stand along 10/100Mbps dual speed repeater applications with
two LED display mode.
The AX88871A has two LED display mode.
Mode 0
Direct LED display mode.
Mode 1
Rich LED display mode.
AX88875AP Bripeater
ASIX ELECTRONICS CORPORATION
4
1.2 Features
IEEE 802.3u repeater compatible
Supports per port 10/100Mbps alternative with auto detected
Build in 10/100Mbps bridge engine with following features
1.
Minimum 32K bytes, maximum 128K bytes SRAM to buffer packets
2.
Seamless buffer management without waste any space of buffer memory
3.
Simple asynchronous 8-bit SRAM interface to reduce system cost
4.
256 or 1024 entries is supported
5.
Auto learning and filtering
6.
Two forwarding modes are supported : Store-n-Forward and fragment-free
7.
Flow-control is supported optionally.
8.
Buffer RAM auto testing
9.
Routing and Learning at wire speed (148810 packets/sec at 100Mbps)
Supports 5 10/100Mbps network connections
5 dedicated MII interfaces can support 100BASE-TX/T4/FX PHY interfaces
5
th
Port can connect to bridge, switch or MAC type device optionally.
Low latency design supports Class II repeater implementation
All ports can be separately isolated or partitioned in response to fault condition
Separate jabber and partition state machines for each port
Per-port LED display for Jabber, Partition, Activity. Global partition, RAM test fail and
collision, utilization (%) for 10/100Mbps presentation
Power on LED diagnosis. All the LED display will follow the "ON-OFF-ON-OFF-Normal"
operation procedure during/after power on reset
160-pin PQFP
AX88875AP Bripeater
ASIX ELECTRONICS CORPORATION
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1.3 Block Diagram
Fig - 1
Chip Block Diagram
10/100
Q-PHY
10/100
PHY
or
MAC
MII
I/F
MII
interface
Re-concilia-
tion
Sub-layer
(Port 0 -
Port 4 )
Speed
Detection
circuit
Elasticity Buffer
for 100Mbps
and 10Mbps
MUX
Repeater State
Machine of 100Mbps
Collision
Handling Logic
for 100Mbps
and10Mbps
Per port Jabber ctl,
auto-partition SM &
Per port Collision ,
Partition counters.
Registers
MIB I/F
(Reserved)
Cascade
Arbitration Logic
of 100Mbps
(Reserved)
........
MII
I/F
Repeater State
Machine of 10Mbps
100Mbps
to
10Mbps
Bridge
MEM I/F
(Reserved)