1
CAT34RC02
2-kb I
2
C Serial EEPROM, Serial Presence Detect
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I
2
C Bus Protocol.
PIN CONFIGURATION
FUNCTIONAL SYMBOL
DIP Package (P, L)
TSSOP Package (U, Y)
SOIC Package (J, W)
FEATURES
s
400 kHz I
2
C bus compatible*
s
1.7 to 5.5 volt operation
s
16-byte page write buffer
s
Hardware write protection for entire memory
s
Permanent and reversible software write
protection for lower 128 bytes
s
Schmitt trigger on SCL and SDA inputs
s
Low power CMOS technology
s
1,000,000 program/erase cycles
s
100 year data retention
s
8-pin DIP, SOIC, TSSOP and TDFN packages
s
Industrial and extended temperature ranges
DESCRIPTION
The CAT34RC02 is a 2-kb Serial CMOS EEPROM
internally organized as 256 words of 8 bits each. Catalyst's
advanced CMOS technology substantially reduces
device power requirements. The CAT34RC02 features
a 16-byte page write buffer. The device operates via the
I
2
C bus serial interface and is available in 8-pin DIP,
SOIC, TSSOP and TDFN packages.
2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1052, Rev. F
A2
A0
A1
VSS
A0
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
A1
A2
VSS
VCC
WP
SCL
SDA
8
7
6
5
VCC
WP
SCL
SDA
A2
A0
A1
VSS
1
2
3
4
HA
LOGEN FREE
TM
LEAD FREE
Preliminary Information
TDFN Package (SP2, VP2)
PIN FUNCTIONS
Pin Name
Function
A
0
, A
1
, A
2
Device Address Inputs
SDA
Serial Data/Address
SCL
Serial Clock
WP
Write Protect
V
CC
1.7 V to 5.5 V Power Supply
V
SS
Ground
8
7
6
5
1
2
3
4
A0
A1
A2
VSS
VCC
WP
SCL
SDA
VCC
VSS
SDA
SCL
WP
CAT34RC02
A2, A1, A0
CAT34RC02
2
Doc. No. 1052, Rev. F
CAPACITANCE T
A
= 25
C, f = 400 kHz, V
CC
= 5 V
Symbol
Test
Conditions
Min
Typ
Max
Units
C
I/O
(2)
Input/Output Capacitance (SDA)
V
I/O
= 0 V
8
pF
C
IN
(2)
Input Capacitance (other pins)
V
IN
= 0 V
6
pF
Z
WPL
WP Input Impedance
V
IN
< 0.5 V
5
70
k
Z
WPH
WP Input Impedance
V
IN >
V
CC
x 0.7
500
k
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Reference Test Method
Min
Units
N
END
(2)(*)
Endurance
MIL-STD-883, Test Method 1033
1,000,000
Program/ Erase Cycles
T
DR
(2)(*)
Data Retention
MIL-STD-883, Test Method 1008
100
Years
V
ZAP
(2)(*)
ESD Susceptibility
MIL-STD-883, Test Method 3015
4000
Volts
I
LTH
(2)(3)
Latch-up
JEDEC Standard 17
100
mA
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias .................. -55
C to +125
C
Storage Temperature ........................ -65
C to +150
C
Voltage on Any Pin with
Respect to Ground
(1)
............ -2.0 V to V
CC
+ 2.0 V
Voltage on A
0 ..................................................
-2.0 V to +12.0 V
V
CC
with Respect to V
SS ..............................
-2.0 V to +7.0 V
Note:
(1) The DC input voltage on any pin should not be lower than -0.5 V or higher than V
CC
+ 0.5 V. During transitions, the voltage on any pin
may undershoot to no less than -2.0 V or overshoot to no more than VCC + 2.0 V, for periods of less than 20 ns. The maximum DC
voltage on address pin A
0
is +12.0 V.
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) Latch-up protection is provided for stresses up to 100 mA on I/O pins from -1.0 V to V
CC
+ 1.0 V.
(4) Standby Current, I
SB
= 0
A (<900 nA).
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
outside of those listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for extended periods
may affect device performance and reliability.
(*) Page Mode, VCC = 5 V, 25
C
D.C. OPERATING CHARACTERISTICS
V
CC
= 1.7 V to 5.5 V, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
I
CC
Power Supply Current (Read)
f
SCL
= 100 kHz
1
mA
I
CC
Power Supply Current (Write)
f
SCL
= 100 kHz
3
mA
I
SB
(4)
Standby Current (V
CC
= 5.0 V)
V
IN
= GND or V
CC
0
A
I
LI
Input Leakage Current
V
IN
= GND to V
CC
1
A
I
LO
Output Leakage Current
V
OUT
= GND to V
CC
1
A
V
IL
Input Low Voltage
1
V
CC
x 0.3
V
V
IH
Input High Voltage
V
CC
x 0.7
V
CC
+ 1.0
V
V
OL1
Output Low Voltage (V
CC
= 3.0 V)
I
OL
= 3 mA
0.4
V
V
OL2
Output Low Voltage (V
CC
= 1.7 V)
I
OL
= 1.5 mA
0.5
V
V
HV
RSWP Set/Clear Overdrive
V
CC
> 2.7 V
5.2
V
Voltage, (V
HV
- V
CC
)
CAT34RC02
3
Doc No. 1052, Rev. F
Write Cycle Limits
Symbol
Parameter
Min
Typ
Max
Units
t
WR
Write Cycle Time
5
ms
A.C. CHARACTERISTICS
V
CC
= 1.7 V to 5.5 V, unless otherwise specified.
Read & Write Cycle Limits
Symbol
Parameter
1.7 V - 5.5 V
2.5 V - 5.5 V
Min
Max
Min
Max
Units
F
SCL
Clock Frequency
100
400
kHz
T
I
(1)
Noise Suppression Time
100
100
ns
Constant at SCL, SDA Inputs
t
AA
SCL Low to SDA Data Out
3.5
0.9
s
and ACK Out
t
BUF
(1)
Time the Bus Must be Free Before
4.7
1.3
s
a New Transmission Can Start
t
HD:STA
Start Condition Hold Time
4
0.6
s
t
LOW
Clock Low Period
4.7
1.3
s
t
HIGH
Clock High Period
4
0.6
s
t
SU:STA
Start Condition Setup Time
4.7
0.6
s
(for a Repeated Start Condition)
t
HD:DAT
Data In Hold Time
0
0
ns
t
SU:DAT
Data In Setup Time
250
100
ns
t
R
(1)
SDA and SCL Rise Time
1
0.3
s
t
F
(1)
SDA and SCL Fall Time
300
300
ns
t
SU:STO
Stop Condition Setup Time
4
0.6
s
t
DH
Data Out Hold Time
100
100
ns
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
Power-Up Timing
(1)(2)
Symbol
Parameter
Min
Typ
Max
Units
t
PUR
Power-up to Read Operation
1
ms
t
PUW
Power-up to Write Operation
1
ms
The write cycle time is the time elapsed between the
STOP command (following the write instruction) and the
completion of the internal write cycle. During the internal
write cycle, SDA is released by the Slave and the device
does not acknowledge external commands.
CAT34RC02
4
Doc. No. 1052, Rev. F
FUNCTIONAL DESCRIPTION
The CAT34RC02 supports the I
2
C (2-wire) Bus data
transmission protocol. This Inter-Integrated Circuit Bus
protocol defines any device that sends data to the bus to
be a transmitter and any device receiving data to be a
receiver. Data transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT34RC02
operates as a Slave device. Both the Master and Slave
devices can operate as either transmitter or receiver, but
the Master alone assigns those roles. A maximum of 8
devices may be connected to the bus as determined by
the device address inputs A
0
, A
1
, and A
2
.
PIN DESCRIPTIONS
SCL: Serial Clock
The serial clock input pin is used to clock all data
transfers into or out of the device.
SDA: Serial Data/Address
The bidirectional serial data/address pin is used to
transfer data into and out of the device. This pin is an
open drain output in transmit mode.
A
0
, A
1
, A
2
: Device Address Inputs
These inputs set the device address. When left floating,
the address pins are internally pulled to ground.
WP: Write Protect
This input, when grounded or left floating, allows write
operations to the entire memory. When this pin is tied to
V
CC
, the entire memory is write protected.
START BIT
SDA
STOP BIT
SCL
Figure 3. Start/Stop Timing
Figure 2. Write Cycle Timing
Figure 1. Bus Timing
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
ACK
8th Bit
Byte n
SCL
SDA
tHIGH
SCL
SDA IN
SDA OUT
tLOW
tF
tLOW
tR
tBUF
tSU:STO
tSU:DAT
tHD:DAT
tHD:STA
tSU:STA
tAA
tDH
CAT34RC02
5
Doc No. 1052, Rev. F
I
2
C BUS PROTOCOL
The I
2
C bus consists of two `wires', SCL and SDA. The
two `wires' are connected to the supply (V
CC
) via pull-up
resistors. Master and Slave devices connect to the bus
via their respective SCL and SDA pins. The transmitting
device pulls down the SDA line to `transmit' a `0' and
releases it to `transmit' a `1'.
(1) Data transfer may be initiated only when the bus is
not busy (see A.C. Characteristics).
(2) During a data transfer, the data line must remain
stable whenever the SCL line is high. An SDA
transition while SCL is high will be interpreted as a
START or STOP condition.
START Condition
The START Condition precedes all commands. It consists
of a HIGH to LOW transition on SDA while SCL is HIGH.
The START condition acts as a `wake-up' call for the
Slave devices. A Slave will not respond to commands
unless the MASTER generates a START condition.
STOP Condition
The STOP condition completes all commands. It consists
of a LOW to HIGH transition on SDA while SCL is HIGH.
The STOP condition starts the internal write cycle, when
following a WRITE command and sends the Slave into
standby mode, when following a READ command.
Device Addressing
The Master initiates a data transfer by creating a START
condition on the bus. The Master then broadcasts an 8-
bit serial Slave address. The four most significant bits of
the Slave address (the `preamble') are fixed to 1010
(Ah), for normal read/write operations and 0110 (6h) for
Software Write Protect (SWP) operations (Fig. 5). The
next three bits, A
2
, A
1
and A
0
, select one of eight possible
Slave devices. The last bit, R/
W
, specifies whether a
Read (1) or Write (0) operation is to be performed.
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA
line during the 9
th
clock cycle. The Slave will aslo
acknowledge the 8-bit byte address and every data byte
presented in WRITE mode. In READ mode the Slave
shifts out eight bits of data, and then `releases' the SDA
line durng the 9
th
clock cycle. If the Master acknowledges
in the 9
th
clock cycle (by pulling down the SDA line), then
the Slave continues transmitting. When data transfer is
complete, the Master responds with a NoACK (it does
not acknowledge the last data byte) and the Slave stops
transmitting and waits for a STOP condition.
Figure 4. Acknowledge Timing
Figure 5. Slave Address Bits
ACKNOWLEDGE
1
START
SCL FROM
MASTER
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
1
DEVICE ADDRESS
0
1
0
A2
A1
A0
R/W
0
1
1
0
A2
A1
A0
R/W
Normal Read and Write
Programming the Write
Protect Register
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