1
Features
Utilizes the AVR
RISC Architecture
AVR High-performance and Low-power RISC Architecture
89 Powerful Instructions Most Single Clock Cycle Execution
32 x 8 General Purpose Working Registers
Up to 12 MIPS Throughput at 12 MHz
Data and Non-volatile Program Memory
1K Byte of In-System Programmable Flash
Endurance: 1,000 Write/Erase Cycles
64 Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
Programming Lock for Flash Program and EEPROM Data Security
Peripheral Features
One 8-bit Timer/Counter with Separate Prescaler
On-chip Analog Comparator
Programmable Watchdog Timer with On-chip Oscillator
SPI Serial Interface for In-System Programming
Special Microcontroller Features
Low-power Idle and Power-down Modes
External and Internal Interrupt Sources
Selectable On-chip RC Oscillator for Zero External Components
Specifications
Low-power, High-speed CMOS Process Technology
Fully Static Operation
Power Consumption at 4 MHz, 3V, 25
C
Active: 2.0 mA
Idle Mode: 0.4 mA
Power-down Mode: <1 A
I/O and Packages
15 Programmable I/O Lines
20-pin PDIP, SOIC and SSOP
Operating Voltages
2.7 - 6.0V (AT90S1200-4)
4.0 - 6.0V (AT90S1200-12)
Speed Grades
0 - 4 MHz, (AT90S1200-4)
0 - 12 MHz, (AT90S1200-12)
Pin Configuration
8-bit
Microcontroller
with 1K Byte
of In-System
Programmable
Flash
AT90S1200
Rev. 0838HAVR03/02
2
AT90S1200
0838HAVR03/02
Description
The AT90S1200 is a low-power CMOS 8-bit microcontroller based on the AVR RISC
architecture. By executing powerful instructions in a single clock cycle, the AT90S1200
achieves throughputs approaching 1 MIPS per MHz allowing the system designer to
optimize power consumption versus processing speed.
The AVR core combines a rich instruction set with the 32 general purpose working reg-
isters. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU),
allowing two independent registers to be accessed in one single instruction executed in
one clock cycle. The resulting architecture is more code efficient while achieving
throughputs up to ten times faster than conventional CISC microcontrollers.
Block Diagram
Figure 1. The AT90S1200 Block Diagram
The architecture supports high-level languages efficiently as well as extremely dense
assembler code programs. The AT90S1200 provides the following features: 1K byte of
In-System Programmable Flash, 64 bytes EEPROM, 15 general purpose I/O lines, 32
general purpose working registers, internal and external interrupts, programmable
watchdog timer with internal oscillator, an SPI serial port for program downloading and
two software selectable power-saving modes. The Idle Mode stops the CPU while allow-
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AT90S1200
0838HAVR03/02
ing the Registers, Timer/Counter, Watchdog and Interrupt system to continue
functioning. The Power-down mode saves the register contents but freezes the Oscilla-
tor, disabling all other chip functions until the next External Interrupt or hardware Reset.
The device is manufactured using Atmel's high-density nonvolatile memory technology.
The On-chip In-System Programmable Flash allows the program memory to be repro-
grammed in-system through an SPI serial interface or by a conventional nonvolatile
memory programmer. By combining an enhanced RISC 8-bit CPU with In-System Pro-
grammable Flash on a monolithic chip, the Atmel AT90S1200 is a powerful
microcontroller that provides a highly flexible and cost-effective solution to many embed-
ded control applications.
The AT90S1200 AVR is supported with a full suite of program and system development
tools including: macro assemblers, program debugger/simulators, in-circuit emulators,
and evaluation kits.
Pin Descriptions
VCC
Supply voltage pin.
GND
Ground pin.
Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors
(selected for each bit). PB0 and PB1 also serve as the positive input (AIN0) and the
negative input (AIN1), respectively, of the On-chip Analog Comparator. The Port B out-
put buffers can sink 20 mA and thus drive LED displays directly. When pins PB0 to PB7
are used as inputs and are externally pulled low, they will source current if the internal
pull-up resistors are activated. The Port B pins are tri-stated when a reset condition
becomes active, even if the clock is not active.
Port B also serves the functions of various special features of the AT90S1200 as listed
on page 30.
Port D (PD6..PD0)
Port D has seven bi-directional I/O pins with internal pull-up resistors, PD6..PD0. The
Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled
low will source current if the pull-up resistors are activated. The Port D pins are tri-stated
when a reset condition becomes active, even if the clock is not active.
Port D also serves the functions of various special features of the AT90S1200 as listed
on page 34.
RESET
Reset input. A low level on this pin for more than 50 ns will generate a reset, even if the
clock is not running. Shorter pulses are not guaranteed to generate a reset.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
Crystal Oscillator
XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can
be configured for use as an On-chip Oscillator, as shown in Figure 2. Either a quartz
crystal or a ceramic resonator may be used. To drive the device from an external clock
source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 3.
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AT90S1200
0838HAVR03/02
Figure 2. Oscillator Connections
Note:
When using the MCU Oscillator as a clock for an external device, an HC buffer should be
connected as indicated in the figure.
Figure 3. External Clock Drive Configuration
On-chip RC Oscillator
An On-chip RC Oscillator running at a fixed frequency of 1 MHz can be selected as the
MCU clock source. If enabled, the AT90S1200 can operate with no external compo-
nents. A control bit (RCEN) in the Flash Memory selects the On-chip RC Oscillator as
the clock source when programmed ("0"). The AT90S1200 is normally shipped with this
bit unprogram med ("1"). Parts with this bit progra mmed can be ord ered as
AT90S1200A. The RCEN-bit can be changed by parallel programming only. When
using the On-chip RC Oscillator for Serial Program downloading, the RCEN bit must be
programmed in Parallel Programming mode first.
XTAL2
XTAL1
GND
C2
C1
MAX 1 HC BUFFER
HC
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AT90S1200
0838HAVR03/02
Architectural
Overview
The fast-access register file concept contains 32 x 8-bit general purpose working regis-
ters with a single clock cycle access time. This means that during one single clock cycle,
one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output from
the register file, the operation is executed, and the result is stored back in the register
file in one clock cycle.
Figure 4. The AT90S1200 AVR RISC Architecture
The ALU supports arithmetic and logic functions between registers or between a con-
stant and a register. Single register operations are also executed in the ALU. Figure 4
shows the AT90S1200 AVR RISC microcontroller architecture. The AVR uses a Har-
vard architecture concept with separate memories and buses for program and data
memories. The program memory is accessed with a 2-stage pipeline. While one instruc-
tion is being executed, the next instruction is pre-fetched from the program memory.
This concept enables instructions to be executed in every clock cycle. The program
memory is In-System Programmable Flash memory.
With the relative jump and relative call instructions, the whole 512 address space is
directly accessed. All AVR instructions have a single 16-bit word format, meaning that
every program memory address contains a single 16-bit instruction.
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