1
Features
Serial EEPROM Family for Configuring Altera FLEX
Devices
Simple Interface to SRAM FPGAs
EE Programmable 512K and 1M-bit Serial Memories Designed to Store
Configuration Programs for Field Programmable Gate Arrays (FPGAs)
Cascadable Read Back to Support Additional Configurations or Future
Higher-density Arrays
Low-power CMOS EEPROM Process
Programmable Reset Polarity
Available in the Space-efficient Surface-mount PLCC Package
In-System Programmable Via 2-wire Bus
Emulation of Atmel's AT24CXXX Serial EEPROMs
Available in 3.3V 10% LV and 5V 5% C Versions
System-friendly READY Pin
Description
The AT17C512A/010A and AT17LV512A/010A (high-density AT17A Series) FPGA
Configuration EEPROMs (Configurators) provide an easy-to-use, cost-effective con-
figuration memory for programming Altera FLEX
devices. The AT17A Series is
packaged in the popular 20-pin PLCC. The AT17A Series family uses a simple serial-
access procedure to configure one or more FPGA devices. The AT17A Series organi-
zation supplies enough memory to configure one or multiple smaller FPGAs. Using a
feature of the AT17A Series, the user can select the polarity of the reset function by
programming four EEPROM bytes. The AT17A parts generate their own internal clock
and can be used as a system "master" for loading the FPGA devices.
The Atmel devices also support a system-friendly READY pin and a write protect
mechanism. The READY pin is used to simplify system power-up considerations. The
WP1 pin is used to protect part of the Configurator memory during in-system
programming.
The AT17A Series Configurators can be programmed with industry-standard program-
mers, or Atmel's ATDH2200E Programming Kit.
FPGA
Configuration
EEPROM
Memory
512K and 1M
Altera Pinout
AT17C512A
AT17LV512A
AT17C010A
AT17LV010A
Rev. 0974B07/99
Pin Configurations
PLCC
4
5
6
7
8
18
17
16
15
14
DCLK
WP1
NC
NC
OE
SER_EN
NC
NC
READY
NC
3
2
1
20
19
9
10
11
12
13
nCS
GND
NC
(A2) nCASC
NC
NC
DATA
NC
VCC
NC
AT17C/LV512A/010A
2
Block Diagram
Device Configuration
The control signals for the configuration EEPROMnCS,
OE, and DCLKinterface directly with the FPGA device
control signals. All FPGA devices can control the entire
configuration process and retrieve data from the configura-
tion EEPROM without requiring an external intelligent
controller.
The configuration EEPROM's OE and nCS pins control the
tri-state buffer on the DATA output pin and enable the
address counter and the oscillator. When OE is driven Low,
the configuration EEPROM resets its address counter and
tri-states its DATA pin. The nCS pin also controls the out-
put of the AT17A Series Configurator. If nCS is held High
after the OE reset pulse, the counter is disabled and the
DATA output pin is tri-stated. When nCS is driven Low, the
counter and the DATA output pin are enabled. When OE is
driven Low again, the address counter is reset and
the DATA output pin is tri-stated, regardless of the state
of the nCS.
When the Configurator has driven out all of its data and
nCASC is driven Low, the device tri-states the DATA pin to
avoid contention with other Configurators. Upon power-up,
the address counter is automatically reset.
The READY pin is available as an open-collector indicator
of the device's reset status; it is driven Low while the device
is in its power-on reset cycle and released (tri-stated) when
the cycle is complete.
This document discusses the EPF10K device interface.
For more details or information on other Altera applications,
please reference the "AT17A Series Conversions from
Altera FPGA Serial Configuration Memories" application
note.
EEPROM
CELL
MATRIX
ROW
DECODER
COLUMN
DECODER
TC
nCS
DCLK READY
OE
nCASC (A2)
DATA
BIT
COUNTER
OSC
OSC
CONTROL
PROGRAMMING
DATA SHIFT
REGISTER
PROGRAMMING
MODE LOGIC
ROW
ADDRESS
COUNTER
POWER ON
RESET
SER_EN
WP1
AT17C/LV512A/010A
3
FPGA Device Configuration
FPGA devices can be configured with an AT17A Series
EEPROM as shown in Figure 1. The AT17A Series device
stores configuration data in its EEPROM array and clocks
the data out serially with its internal oscillator. The OE,
nCS, and DCLK pins supply the control signals for the
address counter and the output tri-state buffer. The AT17A
Series device sends a serial bitstream of configuration data
to its DATA pin, which is connected to the DATA0 input pin
on the FPGA device.
When configuration data for an FPGA device exceeds the
capacity of a single AT17A Series device, multiple AT17A
Series devices can be serially linked together (Figure 2).
When multiple AT17A Series devices are required, the
nCASC and nCS pins provide handshaking between the
cascaded EEPROMs.
The position of an AT17A Series device in a chain deter-
mines its operation. The first AT17A Series device in a
Configurator chain is powered up or reset with nCS Low
and is configured for the FPGA device's protocol. This
AT17A Series device supplies all clock pulses to one or
more FPGA devices and to any downstream AT17A Series
Configurator during configuration. The first AT17A Series
Configurator also provides the first stream of data to the
FPGA devices during multi-device configuration. Once the
first AT17A Series device finishes sending configuration
data, it drives its nCASC pin Low, which drives the nCS pin
of the second AT17A Series device Low. This activates the
second AT17A Series device to send configuration data to
the FPGA device.
The first AT17A Series device clocks all subsequent
AT17A Series devices until configuration is complete. Once
all configuration data is transferred and nCS on the first
AT17A Series device is driven High by CONF_DONE on
the FPGA devices, the first AT17A Series device clocks 16
additional cycles to initialize the FPGA device before going
into zero-power (idle) state. If nCS on the first AT17A
Series device is driven High before all configuration data is
transferredor if the nCS is not driven High after all configu-
ration data is transferred nSTATUS is driven Low,
indicating a configuration error.
The READY pin is available as an open-collector indicator
of the device's reset status; it is driven Low while the device
is in its power-on reset cycle and released (tri-stated) when
the cycle is complete. It can be used to hold the FPGA
device in reset while it is completing its power-on reset but
it cannot be used to effectively delay configuration (i.e., the
output is released well before the system VCC has
stabilized).
Figure 1. Configuration with a Single AT17A Series Configurator
Notes:
1. 1.0 k
resistors used unless otherwise specified.
2. Applicable to EPF6K.
3. Use of the READY pin is optional.
4. Introducing a RC delay to the input of nCONFIG is recommended to ensure that VCC (5V/3.3V) is reached before
configuration begins. (nCONFIG can instead be connected to an active Low system reset signal.)
5. Reset polarity of EEPROM must be set active Low (OE active High).
MSEL1
nSTATUS
MSEL0
CONF_DONE
DATA0
DCLK
nCONFIG
EPF10K
AT17C512A/010A
AT17LV512A/010A
GND
OE
nCS
DATA
DCLK
nCE
VCC
VCC
VCC
READY
AT17C/LV512A/010A
4
Figure 2. Configuration with Multiple AT17A Series Configurators
Notes:
1. 1.0 k
resistors used unless otherwise specified.
2. Use of the READY pin is optional.
3. Introducing a RC delay to the input of nCONFIG is recommended to ensure that VCC (5V/3.3V) is reached before
configuration begins. (nCONFIG can instead be connected to an active Low system reset signal.)
4. Reset polarity of EEPROM must be set active Low (OE active High).
AT17A Series Reset Polarity
The AT17A Series Configurator allows the user to program
the reset polarity as either RESET/OE or RESET/OE. For
more details, please reference the "Programming Specifi-
cation for Atme l's FPGA Config uration EEPROMs"
application note.
Programming Mode
The programming mode is entered by bringing SER_EN
Low. In this mode the chip can be programmed by the
2-wire serial interface. The programming is done at VCC
supply only. Programming super voltages are generated
inside the chip. See the "Programming Specification for
Atmel's Configuration EEPROMs" application note for fur-
ther information. The AT17 A-series parts are read/write at
5V nominal. The AT17LV A-series parts are read/write at
3.3V nominal.
Standby Mode
The AT17A Series Configurator enters a low-power
standby mode whenever nCS is asserted High. In this
mode, the configuration consumes less than 0.5 mA of cur-
rent at 5V. The output remains in a high-impedance state
regardless of the state of the OE input.
MSEL1
nSTATUS
MSEL0
CONF_DONE
DATA0
DCLK
nCONFIG
EPF10K
AT17C512A/010A
AT17LV512A/010A
DEVICE 1
GND
VCC
VCC
OE
nCS
nCASC
DATA
DCLK
AT17C512A/010A
AT17LV512A/010A
DEVICE 2
OE
nCS
DATA
DCLK
VCC
READY
READY
nCE
AT17C/LV512A/010A
5
Pin Configurations
20
PLCC
Pin Name
I/O
Description
2
DATA
I/O
Three-state data output for configuration. Open-collector bi-directional pin for programming.
4
DCLK
I/O
Clock output or clock input. Rising edges on DCLK increment the internal address counter and present the
next bit of data to the DATA pin. The counter is incremented only if the OE input is held High, the nCS input
is held Low, and all configuration data has not been transferred to the target device (otherwise, as the
master device, the DCLK pin drives Low).
5
WP1
I
WRITE PROTECT (1). Used to protect portions of memory during programming. Disabled by default due
to internal pull-down resistor. This input pin is not used during FPGA loading operations. See
programming specifications for details.
8
OE
I
Output enable (active High) and reset (active Low) when SER_EN is High. A Low logic level resets the
address counter. A High logic level (with nCS Low) enables DATA and permits the address counter to
count. In the mode, if this pin is Low (reset), the internal oscillator becomes inactive and DCLK drives Low.
The logic polarity of this input is programmable and must be programmed active High (RESET active Low)
by the user during programming for Altera applications.
9
nCS
I
Chip select input (active Low). A Low input (with OE High) allows DCLK to increment the address counter
and enables DATA to drive out. If the AT17A Series is reset with nCS Low, the device initializes as the first
(and master) device in a daisy-chain. If the AT17A Series is reset with nCS High, the device initializes as a
subsequent AT17A Series device in the chain.
10
GND
Ground pin. A 0.2 F decoupling capacitor should be placed between the VCC and GND pins.
12
nCASC
O
Cascade select output (active Low). This output goes Low when the address counter has reached its
maximum value. In a daisy-chain of AT17A Series devices, the nCASC pin of one device is usually
connected to the nCS input pin of the next device in the chain, which permits DCLK from the master
Configurator to clock data from a subsequent AT17A Series device in the chain.
A2
I
Device selection input, A2. This is used to enable (or select) the device during programming, (i.e., when
SER_EN is Low; please refer to the "Programming Specification" application note for more details).
15
READY
O
Open collector reset state indicator. Driven Low during power-up reset, released (tri-stated) when
power-up is complete. (Recommend a 4.7 k
pull-up on this pin if used).
18
SER_EN
I
Serial enable must be held High during FPGA loading operations. Bringing SER_EN Low, enables the
2-wire serial programming mode.
20
VCC
+3.3V/+5V power supply pin
Absolute Maximum Ratings*
Operating Temperature.................................. -55
C to +125
C
*NOTICE:
Stresses beyond those listed under Absolute Maxi-
mum Ratings may cause permanent damage to the
device. These are stress ratings only, and functional
operation of the device at these or any other condi-
tions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum
Ratings conditions for extended periods of time
may affect device reliability.
Storage Temperature ..................................... -65
C to +150
C
Voltage on Any Pin
with Respect to Ground ..............................-0.1V to V
CC
+0.5V
Supply Voltage (V
CC
) .........................................-0.5V to +7.0V
Maximum Soldering Temp. (10 sec @ 1/16 in.)..............260
C
ESD (R
ZAP
= 1.5K, C
ZAP
= 100 pF) ................................ 2000V
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