1
Pin Configurations
PLCC
DIP
SOIC
4
5
6
7
8
18
17
16
15
14
CLK
NC
(WP) RESET/OE
NC
CE
NC
SER_EN
NC
NC
CEO (A2)
3
2
1
20
19
9
10
11
12
13
NC
GND
NC
NC
NC
NC
DATA
NC
VCC
NC
1
2
3
4
8
7
6
5
DATA
CLK
(WP) RESET/OE
CE
VCC
SER_EN
CEO (A2)
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
NC
DATA
NC
CLK
NC
(WP) RESET/OE
NC
CE
NC
GND
VCC
NC
NC
SER_EN
NC
NC
CEO (A2)
NC
NC
NC
Features
EE Programmable 65,536 x 1-, 131,072 x 1-, and 262,144 x 1-bit Serial Memories
Designed to Store Configuration Programs for Field Programmable Gate
Arrays (FPGAs)
In-System Programmable Via 2-wire Bus
Simple Interface to SRAM FPGAs
Compatible with Atmel AT6000, AT40K FPGAs, Altera FLEX
Devices, Lucent ORCA
FPGAs, Xilinx XC3000, XC4000, XC5200, SPARTAN
FPGAs, Motorola MPA1000 FPGAs
Cascadable Read Back to Support Additional Configurations or Future Higher-density
Arrays (128K and 256K only)
Low-power CMOS EEPROM Process
Programmable Reset Polarity
Available in the Space-efficient Plastic DIP or SOIC Packages; PLCC Package is
Pin-compatible Across Product Family
Emulation of Atmel's AT24CXXX Serial EEPROMs
Available in 3.3V 10% LV and 5V 5% C Versions
Low-power Standby Mode
Description
The AT17C65/128/256 and AT17LV65/128/256 (low-density AT17 Series) FPGA
Configuration EEPROMs (Configurators) provide an easy-to-use, cost-effective con-
figuration memory for Field Programmable Gate Arrays. The low-density AT17 Series
is packaged in the 8-pin DIP and the popular 20-pin PLCC and SOIC. The AT17
Series family uses a simple serial-access procedure to configure one or more FPGA
devices. The AT17 Series organization supplies enough memory to configure one or
multiple smaller FPGAs. Using a feature of the AT17 Series, the user can select the
polarity of the reset function by programming a special EEPROM byte. These devices
also support a write-protection mechanism within its programming mode.
The AT17 Series Configurators can be programmed with industry-standard program-
mers, or Atmel's ATDH2200E Programming Kit.
Rev. 0391F07/99
FPGA
Configuration
EEPROM
Memory
64K, 128K and 256K
AT17C65
AT17LV65
AT17C128
AT17LV128
AT17C256
AT17LV256
AT17C/LV65/128/256
2
Block Diagram
FPGA Master Serial Mode Summary
The I/O and logic functions of the FPGA and their associ-
ated interconnections are established by a configuration
program. The program is loaded either automatically upon
power-up, or on command, depending on the state of the
FPGA mode pins. In Master Mode, the FPGA automatically
loads the configuration program from an external memory.
The AT17 Serial Configuration EEPROM has been
designed for compatibility with the Master Serial Mode.
This document discusses the AT6000 FPGA interface. For
more details or AT40K FPGA applications, please refer-
ence "AT6000 Series Configuration" or "AT40K Series
Configuration" application notes.
Controlling the Low-density AT17
Series Serial EEPROMs During
Configuration
Most connections between the FPGA device and the AT17
Serial EEPROM are simple and self-explanatory.
The DATA output of the AT17 Series Configurator drives
DIN of the FPGA devices.
The master FPGA CCLK output drives the CLK input of
the AT17 Series Configurator.
The CEO output of any AT17C/LV128/256 drives the CE
input of the next AT17C/LV128/256 in a cascade chain of
EEPROMs. An AT17C/LV65 can only be used at the end
of a cascade chain or as a standalone device.
SER_EN must be connected to VCC (except
during ISP).
There are two different ways to use the inputs CE and OE.
Condition 1
The simplest connection is to have the FPGA CON pin
drive both CE and RESET/OE
(1)
in parallel (Figure 1). Due
to its simplicity, however, this method will fail if the FPGA
receives an external reset condition during the configura-
tion cycle. If a system reset is applied to the FPGA, it will
abort the original configuration and then reset itself for a
new configuration, as intended. Of course, the AT17 Series
Configurator does not see the external reset signal and will
not reset its internal address counters and, consequently,
will remain out of sync with the FPGA for the remainder of
the configuration cycle.
Note:
1. For this condition, the reset polarity of the EEPROM
must be set active High.
POWER ON
RESET
AT17C/LV65/128/256
3
Figure 1. Condition 1 Connection
Notes:
1. 4.7 k
resistors used unless otherwise specified.
2. Reset polarity of EEPROM must be set active High.
Condition 2
The FPGA CON pin drives only the CE input of the AT17
Series Configurator, while the RESET/OE input is driven by
an input to the FPGA RESET input pin. This connection
works under all normal circumstances, even when the user
aborts a configuration before CON has gone High. A Low
level on the RESET/OE
(1)
input during FPGA reset
clears the Configurator's internal address pointer, so that
the reconfiguration starts at the beginning.
Note:
1. For this condition, the reset polarity of the EEPROM
must be set active Low.
The AT17 Series Configurator does not require an
inverter for either condition since the RESET polarity is
programmable.
Cascading Serial Configuration
EEPROMs
(AT17C/LV128 and AT17C/LV256 only)
(1)
For multiple FPGAs configured as a daisy-chain, or for
future FPGAs requiring larger configuration memories,
cascaded Configurators provide additional memory.
After the last bit from the first Configurator is read, the next
clock signal to the Configurator asserts its CEO output low
and disables its DATA line driver. The second Configurator
recognizes the Low level on its CE input and enables its
DATA output.
After configuration is complete, the address counters of all
cascaded Configurators are reset if the RESET/OE on
each Configurator is driven to its active (default High) level.
If the address counters are not to be reset upon comple-
tion, then the RESET/OE input can be tied to its inactive
(default Low) level.
Note:
1. A single AT17C/LV65 may be used at the end of a
cascade chain.
AT17 Series Reset Polarity
The AT17 Series Configurator allows the user to program
the reset polarity as either RESET/OE or RESET/OE. This
feature is supported by industry-standard programmer
a l g o ri t h m s . Fo r m o re d e t a i l s o n p ro g r a m m i n g t h e
EEPROM's reset polarity, please reference the "Program-
ming Specification for Atmel's FPGA Configuration
EEPROMs" application note.
Programming Mode
The programming mode is entered by bringing SER_EN
Low. In this mode the chip can be programmed by the
2-wire serial bus. The programming is done at VCC supply
only. Programming super voltages are generated inside the
chip. See the "Programming Specification for Atmel's
FPGA Configuration EEPROMs" application note for
further information. The AT17C parts are read/write at 5V
nominal. The AT17LV parts are read/write at 3.3V nominal.
Standby Mode
The AT17C/LV65/128/256 enters a low-power standby
mode whenever CE is asserted High. In this mode, the
Configurator consumes less than 75 A of current at 5.0V.
The output remains in a high impedance state regardless of
the state of the OE input.
M0
M1
CON
CCLK
D0
REBOOT
AT60xx
AT17C65/128/256
AT17LV65/128/256
GND
VCC
RESET/OE
SER_EN
CE
CLK
DATA
M2
CS
VCC
AT17C/LV65/128/256
4
Pin Configurations
20
PLCC/
SOIC
Pin
8
DIP
Pin
Name
I/O
Description
2
1
DATA
I/O
Three-state DATA output for configuration. Open-collector bi-directional pin for
programming.
4
2
CLK
I
Clock input. Used to increment the internal address and bit counter for reading and
programming.
6
3
RESET/OE
I
RESET/Output Enable input (when SER_EN is High). A Low level on both the CE and
RESET/OE inputs enables the data output driver. A High level on RESET/OE resets
both the address and bit counters. The logic polarity of this input is programmable as
either RESET/OE or RESET/OE. This document describes the pin as RESET/OE.
WP
I
Write protect (WP) input (when CE is Low). When WP is Low, the entire memory can
be written. When WP is enabled (High), the lowest block of the memory cannot be
written. This feature is only active in the 2-wire serial Programming Mode (i.e., when
SER_EN is Low; see "Programming Specification" application note for more details).
8
4
CE
I
Chip Enable input. Used for device selection. A Low level on both CE and OE enables
the data output driver. A High level on CE disables both the address and bit counters
and forces the device into a low-power standby mode. Note that this pin will not
enable/disable the device in the 2-wire Serial Programming Mode (i.e., when SER_EN
is Low).
10
5
GND
Ground pin. A 0.2 F decoupling capacitor between VCC and GND is recommended.
14
6
CEO
O
Chip Enable Output. This signal is asserted Low on the clock cycle following the last bit
read from the memory. It will stay Low as long as CE and OE are both Low. It will then
follow CE until OE goes High. Thereafter, CEO will stay High until the entire EEPROM
is read again.
A2
I
Device selection input, A2. This is used to enable (or select) the device during
programming (i.e. when SER_EN is Low; see the "Programming Specification"
application note for more details.
17
7
SER_EN
I
Serial enable must be held High during FPGA loading operations. Bringing SER_EN
Low enables the 2-wire Serial Programming Mode.
20
8
VCC
+3.3V/+5V Power Supply Pin.
Absolute Maximum Ratings*
Operating Temperature.................................. -55C to +125 C
*NOTICE:
Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those listed under oper-
ating conditions is not implied. Exposure to Abso-
lute Maximum Rating conditions for extended
periods of time may affect device reliability.
Storage Temperature ..................................... -65 C to +150C
Voltage on Any Pin
with Respect to Ground ..............................-0.1V to V
CC
+0.5V
Supply Voltage (V
CC
) .........................................-0.5V to +7.0V
Maximum Soldering Temp. (10 sec. @ 1/16 in.).............260
C
ESD (R
ZAP
= 1.5K, C
ZAP
= 100pF).................................. 2000V
AT17C/LV65/128/256
5
Operating Conditions
Symbol
Description
AT17CXXX
AT17LVXXX
Units
Min/Max
Min/Max
V
CC
Commercial
Supply voltage relative to GND
-0
C to +70
C
4.75/5.25
3.0/3.6
V
Industrial
Supply voltage relative to GND
-40
C to +85
C
4.5/5.5
3.0/3.6
V
Military
Supply voltage relative to GND
-55
C to +125
C
4.5/5.5
3.0/3.6
V
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