2570BAVR09/04
Features
High Performance, Low Power AVR
8-Bit Microcontroller
Advanced RISC Architecture
130 Powerful Instructions Most Single Clock Cycle Execution
32 x 8 General Purpose Working Registers
Fully Static Operation
Up to 16 MIPS Throughput at 16 MHz
On-Chip 2-cycle Multiplier
Non-volatile Program and Data Memories
In-System Self-Programmable Flash, Endurance: 10,000 Write/Erase Cycles
32K bytes (ATmega325/ATmega3250)
64K bytes (ATmega645/ATmega6450)
Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
EEPROM, Endurance: 100,000 Write/Erase Cycles
1K bytes (ATmega325/ATmega3250)
2K bytes (ATmega645/ATmega6450)
Internal SRAM
2K bytes (ATmega325/ATmega3250)
4K bytes (ATmega645/ATmega6450)
Programming Lock for Software Security
JTAG (IEEE std. 1149.1 compliant) Interface
Boundary-scan Capabilities According to the JTAG Standard
Extensive On-chip Debug Support
Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
Peripheral Features
Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
Real Time Counter with Separate Oscillator
Four PWM Channels
8-channel, 10-bit ADC
Programmable Serial USART
Master/Slave SPI Serial Interface
Universal Serial Interface with Start Condition Detector
Programmable Watchdog Timer with Separate On-chip Oscillator
On-chip Analog Comparator
Interrupt and Wake-up on Pin Change
Special Microcontroller Features
Power-on Reset and Programmable Brown-out Detection
Internal Calibrated Oscillator
External and Internal Interrupt Sources
Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and
Standby
I/O and Packages
53/68 Programmable I/O Lines
64-lead TQFP, 64-pad MLF, and 100-lead TQFP
Speed Grade:
ATmega325V/ATmega3250V/ATmega645V/ATmega6450V:
0 - 4 MHz @ 1.8 - 5.5V, 0 - 8 MHz @ 2.7 - 5.5V
ATmega325/3250/645/6450:
0 - 8 MHz @ 2.7 - 5.5V, 0 - 16 MHz @ 4.5 - 5.5V
Temperature range:
-40C to 85C Industrial
8-bit
Microcontroller
with In-System
Programmable
Flash
ATmega325/V
ATmega3250/V
ATmega645/V
ATmega6450/V
Preliminary
5
ATmega325/3250/645/6450
2570BAVR09/04
The AVR core combines a rich instruction set with 32 general purpose working registers.
All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing
two independent registers to be accessed in one single instruction executed in one clock
cycle. The resulting architecture is more code efficient while achieving throughputs up to
ten times faster than conventional CISC microcontrollers.
The ATmega325/3250/645/6450 provides the following features: 32/64K bytes of In-
System Programmable Flash with Read-While-Write capabilities, 1/2K bytes EEPROM,
2/4K byte SRAM, 53/68 general purpose I/O lines, 32 general purpose working regis-
ters, a JTAG interface for Boundary-scan, On-chip Debugging support and
programming, three flexible Timer/Counters with compare modes, internal and external
interrupts, a serial programmable USART, Universal Serial Interface with Start Condi-
tion Detector, an 8-channel, 10-bit ADC, a programmable Watchdog Timer with internal
Oscillator, an SPI serial port, and five software selectable power saving modes. The Idle
mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt
system to continue functioning. The Power-down mode saves the register contents but
freezes the Oscillator, disabling all other chip functions until the next interrupt or hard-
ware reset. In Power-save mode, the asynchronous timer will continue to run, allowing
the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise
Reduction mode stops the CPU and all I/O modules except asynchronous timer and
ADC to minimize switching noise during ADC conversions. In Standby mode, the crys-
tal/resonator Oscillator is running while the rest of the device is sleeping. This allows
very fast start-up combined with low-power consumption.
The device is manufactured using Atmel's high density non-volatile memory technology.
The On-chip In-System re-Programmable (ISP) Flash allows the program memory to be
reprogrammed In-System through an SPI serial interface, by a conventional non-volatile
memory programmer, or by an On-chip Boot program running on the AVR core. The
Boot program can use any interface to download the application program in the Applica-
tion Flash memory. Software in the Boot Flash section will continue to run while the
Application Flash section is updated, providing true Read-While-Write operation. By
combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic
chip, the Atmel ATmega325/3250/645/6450 is a powerful microcontroller that provides a
highly flexible and cost effective solution to many embedded control applications.
The ATmega325/3250/645/6450 AVR is supported with a full suite of program and sys-
tem development tools including: C Compilers, Macro Assemblers, Program
Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.
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