Features
Advanced Programmable Logic Device - High Gate Utilization
Flexible Interconnect Architecture - Universal Routing
Flexible Logic Cells - 128 Flip-Flops and 52 Latches
Multiple Flip-Flop Types - Synchronous or Asynchronous Registers
High Speed - 50 MHz Operation
Complete Third Party Software Support
No Placement, Routing or Layout Software Required
Proven and Reliable High Speed CMOS EPROM Process
2000 V ESD Protection
200 mA Latchup Immunity
Reprogrammable - Tested 100% for Programmability
Commercial, Industrial and Military Temperature Grades
UNIVERSAL
AND
REGIONAL
INTERCONNECT
52 INPUT
LATCHES
52 LOGIC CELLS
(104 FLIP-FLOPS)
24 BURIED CELLS
(24 FLIP-FLOPS)
8
INPUT
PINS
52
I/O
PINS
Block Diagram
Chip Carrier
Pin Configuration
Pin Name
Function
IN
Logic and Clock Inputs
Pins 2,32,36,66
Input/Register Clocks 1-4
Pins 1,34,35,68
Input/Latch Clocks 1-4
I/O
Bidirectional Buffers
VCC
+5 V Supply
High Density
UV Erasable
Programmable
Logic Device
Description
The Atmel V5000 is an easy to use, high density programmable logic device. Its simple, regu-
lar architecture translates into increased utilization and high performance.
The ATV5000 has one programmable combinatorial logic array. This guarantees easy inter-
connection of and uniform performance from all nodes. "Sum terms", which are easy to use
groupings of AND-OR gates, provide combinatorial logic blocks. Sum terms can be wire-
OR'd together to integrate larger logic blocks. To expand the levels of logic, buried sum terms
feed back into the logic array. The 52 I/O pins can each be driven by a register or a sum term.
Each I/O pin has an individually enabled input latch.
All 128 registers are configurable as D- or T-types without using extra logic gates. Individual
sum terms, asynchronous presets, resets and clocks give each flip-flop added flexibility. A
direct "clock from pin" option guarantees synchronization and fast clock to output perform-
ance.
Standard, off-the-shelf third-party software tools and programmers support the ATV5000.
This minimizes start-up investment and improves product support.
I/Os
GND
I/Os
VCC
I/Os
I/Os
VCC
I/Os
GND
I/Os
18
52
35
1
I/Os
I/Os
VCC
GND
IN
IN
GND
VCC
IN
I/Os
I/Os
IN
JLCC
0065B
ATV5000/L
1-193
UNIVERSAL BUS
REGIONAL
TO ALL
BUS
QUADRANTS
PINS
I/O
REGISTERCLOCKS
REGIONAL INPUTS
REGIONAL INPUTS
UNIVERSAL
PRODUCT
UNIVERSAL INPUTS
TERMS
REGIONAL
PRODUCT
TERMS
INPUT
PINS
REGISTERCLOCKS
TERMS
PRODUCT
REGIONAL
TERMS
PRODUCT
UNIVERSAL
INPUT/OUTPUT
LOGIC CELLS
(13 TOTAL
PERQUADRANT)
BURIED
LOGIC CELLS
(6 TOTAL
PERQUADRANT)
Quadrant Functional Logic
Diagram ATV5000
Figure 1
Functional Logic Diagram Description
There are 52 identical input/ouput logic cells and 24 identical
buried logic cells in the ATV5000. Each I/O cell has two flip-
flops, up to three sum terms, individual clock, reset, and preset
terms per flip-flop, and one output enable term. Independent of
output configuration, all flip-flops are always usable, and have
at least four product term inputs each.
Each I/O pin (52 total) signal or its latched version drives the
logic array. There is one latch clock per quadrant.
The ATV5000 has four identical quadrants (see Figure 2). The
universal bus routes true and false signals from each of the 52
I/O pins to all four quadrants. Regional buses route each quad-
rant's flip-flop Q and Q locally. The eight input-only pins are
available in all four regional buses.
Each logic cell has a number of "regional" and "universal" prod-
uct terms (see Figure 1). The I/O logic cells contain three sum
terms, two flip-flops, and an I/O buffer.
The buried logic cells each contain one flip-flop. In addition, in
each buried logic cell the sum term can drive the regional bus.
This allows for logic expansion.
Serial register preload and observability simplify testing. All
registers automatically clear at power up.
Temperature Under Bias.................-55
o
C to +125
o
C
Storage Temperature......................-65
o
C to +150
o
C
Voltage on Any Pin with
Respect to Ground..........................-2.0 V to +7.0 V
1
Voltage on Input Pins
with Respect to Ground
During Programming.....................-2.0 V to +14.0 V
1
Programming Voltage with
Respect to Ground........................-2.0 V to +14.0 V
1
Integrated UV Erase Dose .............. 7258 W
sec/cm
2
*NOTICE: Stresses beyond those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions beyond those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect de-
vice reliability.
Note:
1. Minimum voltage is -0.6 V dc which may undershoot to -2.0 V
for pulses of less than 20 ns. Maximum output pin voltage is
V
CC
+0.75 V dc which may overshoot to +7.0 V for pulses of less
than 20 ns.
Absolute Maximum Ratings*
D.C. and A.C. Operating Range
ATV5000-25
ATV5000/L-30
ATV5000/L-35
Operating Temperature (Case)
Commercial
Industrial
Military
0
o
C - 70
o
C
0
o
C - 70
o
C
-55
o
C - 125
o
C
V
CC
Power Supply
5 V
5%
5 V
10%
5 V
10%
1-194
ATV5000/L
Quadrant Logic Diagram
and Description
The ATV5000 has: four identical quadrants, 52 identical input/
output logic cells, and 24 identical buried logic cells. The uni-
versal bus routes true and false signals from each of the 52 I/O
pins to all four quadrants. Regional buses route each quadrant's
flip-flop Q and Q locally. The eight input-only pins are available
in every regional bus.
Each logic cell has a number of "regional" and "universal" prod-
uct terms (see Figure 3). The I/O logic cells (Figures 7, 8, 9)
contain three sum terms, two flip-flops, and an I/O buffer. Sum
term B has five product terms - two universal and three regional.
Sum terms A and C each have four product terms - one universal
and three regional. Flip-flop Q1 has global asynchronous preset,
reset, and clock product terms. Flip-flop Q2 has universal asyn-
chronous reset and clock terms and a regional asynchronous pre-
set term. There is one universal product term for the I/O pin out-
put enable.
The buried logic cells (Figure 4) each contain one flip-flop. The
sum term has one universal product term and four regional prod-
uct terms for a total of five. The flip-flop has universal asynchro-
nous preset, reset, and clock terms. In addition, in each buried
logic cell the sum term can be fed back into the regional bus
instead of the flip-flop. This allows for logic expansion.
Regional product terms have as inputs all quadrant flip-flop out-
puts (or buried flip-flop inputs) and the eight dedicated input
pins. Universal product terms have the same inputs plus the 52
I/O pins and their complements.
Quadrant Clock Pin Assignments
Quadrant
Number
Register
Clock Pin
Latch
Clock Pin
1
2
1
2
32
34
3
36
35
4
66
68
13 I/O
PINS
REGISTER
CLOCK
LATCH
CLOCK
IN/LIN
Q1
Q2
INPUT/
OUTPUT
LOGIC
CELLS
(13 TOTAL)
REGISTER
CLOCK
16
REGIONAL
BUS
UNIVERSAL
BUS TO ALL
QUADRANTS
Q1/D1
BURIED
LOGIC
CELLS
(6 TOTAL)
OE
UNIVERSAL BUS INPUTS
REGIONAL BUS INPUTS
UNIVERSAL
PRODUCT
TERMS
REGIONAL
PRODUCT
TERMS
ALL 8
INPUT ONLY PINS
Quadrant Structure
Figure 3
16
16
16
16
UNIVERSAL
BUS
REGIONAL
BUS
REGIONAL
BUS
13 I/O CELLS
6 BURIED
LOGIC CELLS
13 I/O CELLS
6 BURIED
LOGIC CELLS
QUADRANT
1
QUADRANT
2
INPUT PINS
1,2,32,34,35,
36,66,68
REGISTER
CLOCK PIN 32
LATCH
CLOCK PIN 34
13 I/O PINS
18,19,21-31
REGISTER
CLOCK PIN 2
LATCH
CLOCK PIN 1
13 I/O PINS
4-15,17
REGIONAL
BUS
REGIONAL
BUS
13 I/O CELLS
6 BURIED
LOGIC CELLS
13 I/O CELLS
6 BURIED
LOGIC CELLS
QUADRANT
4
QUADRANT
3
REGISTER
CLOCK PIN 36
LATCH
CLOCK PIN 35
13 I/O PINS
38-49,51
REGISTER
CLOCK PIN 66
LATCH
CLOCK PIN 68
13 I/O PINS
52,53,55-65
ATV5000 Block Diagram
Figure 2
ATV5000/L
1-195
Logic Cell Options
The ATV5000 logic cells contain most of the chip's logic op-
tions. The standard logic cell contains two flip-flops, three sum
terms and three array inputs. The three sum terms can be com-
bined to provide sum term options of four, five, nine, or 13 prod-
uct terms. A combinatorial signal or the output of Q1 can be sent
to the I/O cell.
The ATV5000 retains the ATV2500's ability to bury both reg-
isters in the I/O cell and still output a combinatorial signal (see
Figure 8). A new feature, unique to the ATV5000, is the ability
to output Q1 and feedback the combinatorial term directly (see
Figure 7). This high speed logic expansion term increases the
devices flexibility and gate utilization.
Buried Logic Cells
Each quadrant has six buried logic cells (see Figure 4). Each cell
contains one sum term with five product terms, a flip-flop, and
individual preset, clear, and clock terms. A configuration bit se-
lects either the Q output or the D input for feedback into the
regional bus.
CK1
AP1
AR2
CK2
Q1
AP2
AR1
R
R
R
U
U
U
U
R
R
R
U
R
R
R
U
U
U
U
R
Q2
CLOCK
OPTION
D2/T2
TO
I/O
CELL
D1/T1
R
R
R
R
U
U
Q2
Q1
OPTION
CLOCK
B
A
C
Logic Cell with Buried Sum Term and
Register to I/O Cell
Figure 7
0/1
LCKn
SELECT
LOGIC
TO
CELL
FROM
LOGIC
CELL
D
Q
I/O
U
OE
C
I/O Pin Logic
Figure 6
CK1
AR1
AP1
U
R
U
U
R
R
U
R
Q1
D1/T1
OPTION
CLOCK
R
R
SELECT
Buried Logic Cells
Figure 4
SELECT
LOGIC
TO
CELL
CLOCK
PRODUCT
TERM
RCKn
Clock Option
Figure 5
Flip-Flop Clock Options
Each register may be connected to its regional clock to provide
fast clock-to-output timing (see Figure 5). In this "synchronous"
mode, the clock is one of four input pins, a unique clock pin for
each chip quadrant. One product term defines each flip-flop's
clock in the "asynchronous" mode.
In the "synchronous" mode, the regional clock is ANDed with
the product term. This provides the fast timing of a synchronous
clock with the local control of the product term.
I/O Pin Latches
Each I/O pin of the ATV5000 has an input latch which can be
individually enabled or disabled (see Figure 6). Each chip quad-
rant has a unique latch clock. When the latch is inactive, pin
input flows directly into the array. When activated, the latch is
flow-through when the clock signal is low, and data is captured
on the clock's rising edge.
Flip-Flop Types
Each flip-flop in the ATV5000 may be configured as either a T-
or D-type flip-flop. A T-type flip-flop can also easily be config-
ured into a JK or SR flip-flop.
1-196
ATV5000/L
Q1
CK1
AP1
AR2
CK2
Q1
Q2
AP2
AR1
R
R
R
U
U
U
U
R
R
R
U
R
R
R
U
U
U
U
R
Q2
OPTION
CLOCK
D1/T1
D2/T2
TO
I/O
CELL
CELL
I/O
FROM
D1/T1
TO
CLOCK
OPTION
U
U
R
R
R
R
A
B
C
Logic Cell with Combinable
Sum Terms, Register to I/O Cell
Figure 9
Q1
CK1
AP1
AR2
CK2
Q1
Q2
AP2
AR1
R
R
R
U
U
U
U
R
R
R
U
R
R
R
U
U
U
U
R
Q2
CLOCK
OPTION
D1/T1
D2/T2
TO
I/O
CELL
CELL
I/O
FROM
OPTION
CLOCK
U
U
R
R
R
R
A
B
C
Logic Cell, Two Buried Registers,
Combinatorial to I/O Cell
Figure 8
D.C. Characteristics
Symbol Parameter
Condition
Min
Typ
Max
Units
I
LI
Input Load Current
V
IN
= -0.1 V to V
CC
+1 V
10
A
I
LO
Output Leakage Current
V
OUT
= -0.1 V to V
CC
+0.1 V
10
A
I
CC
Power Supply Current
ATV5000
V
CC
= MAX, V
IN
= GND or
V
CC
Outputs Open
Com.
200
350
mA
Ind.,Mil.
200
400
mA
I
CC
Power Supply Current
ATV5000L
V
CC
= MAX, V
IN
= GND or
V
CC
Outputs Open
Com.
32
40
mA
Ind.,Mil.
32
50
mA
I
CC2
Clocked Power Supply
Current, ATV5000L Only
f = 1 MHz, V
CC
= MAX
Outputs Open
Com.
30
(2)
mA
Ind.,Mil.
30
(2)
mA
I
OS
(
1
)
Output Short Circuit
Current
V
OUT
= 0.5 V
-120
mA
V
IL
Input Low Voltage
-0.6
0.8
V
V
IH
Input High Voltage
2.0
V
CC
+0.75
V
V
OL
Output Low Voltage
V
IN
= V
IH
or V
IL,
I
OL
= 8 mA Com,Ind; 6 mA Mil.
0.5
V
V
OH
Output High Voltage
I
OH
= -100
A
V
CC
-0.3
V
I
OH
= -4.0 mA
2.4
V
Notes:
1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 seconds.
2. See I
CC
vs. Frequency curve.
ATV5000/L
1-197
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