Rev. 4137JAERO06/02
1
Features
Full Range of Matrices up to 700K Cells
0.5 m Drawn CMOS, 3 Metal Layers, Sea of Gates
RAM and DPRAM Compilers
Library Optimized for Synthesis, Floor Plan and Automatic Test Generation (ATG)
High Speed Performances:
200 ps Typical Gate Delay at 5V
Typical 625 MHz Toggle Frequency at 5V and 360 MHz at 3.3V
High System Frequency Skew Control:
250 MHz PLL for Clock Generation
Clock Tree Synthesis Software
3V and 5V Operation; Single or Dual Supply Modes
Low Power Consumption:
0.6 W/Gate/MHz at 3V
2.2 W/Gate/MHz at 5V
Integrated Power on Reset
Matrices With a Max of 582 Full Programmable Pads
Standard 3, 6, 12 and 24 mA I/Os
Versatile I/O Cell: Input, Output, I/O, Supply, Oscillator
CMOS/TTL/PCI Interface
ESD (2 KV) and Latch-up Protected I/O
High Noise and EMC Immunity:
I/O with Slew Rate Control
Internal Decoupling
Signal Filtering between Periphery and Core
Application Dependent Supply Routing and Several Independent Supply Sources
Wide Range of Packages Including PGA, CQFP, PLCC PQFP, BGA, SSOP
Delivery in Die Form
Advanced CAD Support: Floor Plan, Proprietary Delay Models, Timing Driven Layout,
Power Management
Cadence
, Mentor
TM
, Vital and Synopsys
Reference Platforms
EDIF and VHDL Reference Formats
Available In Commercial, Industrial and Military Quality Grades: for Space Application
see MG2RT and MG2RTP Specifications
QML Q with SMD 5962-00B02
Description
The MG2 series is a 0.5 micron, array based, CMOS product family. Several arrays up
to 700K cells cover all system integration needs. The MG2 is manufactured using a
0.5 micron drawn, 3 metal layers CMOS process.
The MG2 series base cell architecture provides high routability of logic with extremely
dense compiled memories: RAM and DPRAM. ROM can be generated using synthe-
sis tools. For instance, the largest array is capable of integrating 128K bits of DPRAM
with 128K bits of ROM and over 300,000 random gates.
Accurate control of clock distribution can be achieved by PLL hardware and CTS
(Clock Tree Synthesis) software. New noise prevention techniques are applied in the
array and in the periphery: three or more independent supplies, internal decoupling,
customizing dependent supply routing, noise filtering, skew controlled I/Os, low swing
differential I/Os, all contribute to improve the noise immunity and reduce the emission
level.
The MG2 is supported by an advanced software environment based on industry stan-
dards linking proprietary and commercial tools. Cadence, Mentor, Synopsys and
VHDL are the reference front-end tools. Floor planning associated with timing driven
layout provides a short back-end cycle. The MG2 family continues the Atmel offering
in array based commercial, industrial and military circuits.
500K Used Gates
0.5 Micron CMOS
Sea of Gates
MG2
2
MG2
4137JAERO06/02
A netlist based on this library can be simulated as either MG2, or MG2RT or MG2RTP.
Table 1. Description of Matrices
Notes:
1. The Max. number of usable gates is application dependent.
2. Contact Atmel for availability.
Libraries
The MG2 cell library has been designed to take full advantage of the features offered by
both logic and test synthesis tools.
Design testability is assured by the full support of SCAN, JTAG (IEEE 1149) and BIST
methodologies.
More complex macro functions are available in VHDL, for example: I2C, UART,
Timer, etc.
Block Generators
Block generators are used to create a customer-specific simulation model and metallisa-
tion pattern for regular functions like RAM, DPRAM and FIFO. The basic cell
architecture allows 1-bit per cell for RAM and DPRAM. The main characteristics of these
generators are summarized below.
Table 2. Block Generator Capability
Type
Total Cells
Max. Usable
Cells
(1)
Total Pads
Maximum Programmable I/Os
MG2044 44616
35693
171
148
MG2091 91464
73171
235
212
MG2140 140322
112258
285
262
MG2194 193800
155040
331
308
MG2265 264375
211500
384
362
MG2360 361680
289344
435
412
MG2480 481143
384914
507
484
MG2700
(2)
698523
558818
605
582
Function
Maximum
Size (bits)
Bits/Word
Typical Characteristics (16k bits) at 5V
Access Time (ns)
Used Cells
RAM
36k
1-36
8
20 k
DPRAM
36k
1-36
8.6
23 k
3
MG2
4137JAERO06/02
I/O Buffer Interfacing
I/O Flexibility
All I/O buffers may be configured as input, output, bi-directional, oscillator or supply. A
level translator is located close to each buffer.
Inputs
Input buffers with CMOS or TTL thresholds are non-inverting and feature versions with
and without hysteresis. The CMOS and TTL input buffers may incorporate pull-up or pull
down terminators. For special purposes, a buffer allowing direct input to the matrix core
is available.
Outputs
Several kinds of CMOS and TTL output drivers are offered: fast buffers with 3, 6, 12 and
24 mA drive at 5V, low noise buffers with 12 mA drive at 5V.
Clock Generation and PLL
Clock Generation
Atmel offers 7 different types of oscillators: 5 high frequency crystal oscillators and 2 RC
oscillators. For all devices, the mark-space ratio is better than 40/60 and the start-up
time less than 10 ms.
PLL (On request)
Contact Atmel for availability.
Frequency (MHz)
Typical Consumption (mA)
Max 5V
Max 3V
5V
3V
Xtal 7M
12
7
1.2
0.4
Xtal 20M
28
17
2.5
0.8
Xtal 50M
70
40
7
2
Xtal 100M
130
75
16
5
Xtal 32K
32
3
4
RC 10M
10
2
1
RC 32M
32
3
1.5
4
MG2
4137JAERO06/02
Power Supply and
Noise Protection
The speed and density of the SCMOS3/2RT technology causes large switching current
spikes, for example, when:
16 high current output buffers switch simultaneously,
or 10% of the 700,000 gates are switching within a window of 1 ns.
Sharp edges and high currents cause some parasitic elements in the packaging to
become significant. In this frequency range, the package inductance and series resis-
tance should be taken into account. It is known that an inductor slows down the settling
time of the current and causes voltage drops on the power supply lines. These drops
can affect the behavior of the circuit itself or disturb the external application (ground
bounce).
In order to improve the noise immunity of the MG core matrix, several mechanisms have
been implemented inside the MG arrays. Two kinds of protection have been added: one
to limit the I/O buffer switching noise and the other to protect the I/O buffers against the
switching noise coming from the matrix.
I/O Buffers Switching
Protection
Three features are implemented to limit the noise generated by the switching current:
The power supplies of the input and output buffers are separated.
The rise and fall times of the output buffers can be controlled by an internal
regulator.
A design rule concerning the number of buffers connected on the same power
supply line has been imposed.
Matrix Switching Current
Protection
This noise disturbance is caused by a large number of gates switching simultaneously.
To allow this without impacting the functionality of the circuit, three new features have
been added:
Decoupling capacitors are integrated directly on the silicon to reduce the power
supply drop.
A power supply network has been implemented in the matrix. This solution reduces
the number of parasitic elements such as inductance and resistance and constitutes
an artificial VDD and Ground plane. One mesh of the network supplies
approximately 150 cells.
A low pass filter has been added between the matrix and the input to the output
buffer. This limits the transmission of the noise coming from the ground or the VDD
supply of the matrix to the external world via the output buffers.
Note:
For additional information, see 'MG2/Phase Locked Loop' Rev 1.0, 15 Oct., 1996.
5
MG2
4137JAERO06/02
Power Consumption
The power consumption of an MG2 array is due to three factors: leakage (P1), core (P2)
and I/O (P3) consumption.
P = P1 + P2 + P3
Leakage (Standby)
Power Consumption
The consumption due to leakage currents is defined as:
P1 = (VDD - VSS) * I
CCSB
* N
CELL
Where I
CCSB
is the leakage current through a polarized basic gate and N
CELL
is the num-
ber of used cells.
Core Power
Consumption
The power consumption due to the switching of cells in the core of the matrix is defined
as:
P2 = N
CELL
* P
GATE
* C
ACTIVITY
* F
Where N
CELL
is the number of used cells, F the data toggling frequency, which is equal
to half the clock frequency for random data and P
GATE
is the power consumption per
cell.
P
GATE
= P
CA
+ P
CO
ACTIVITY is the fraction of the total number of cells toggling per cycle.
Capacitance Power
P
CA
= C * (VDD - VSS)
2
/2
C is the total output capacitance and may be expressed as the sum of the drain capaci-
tance of the driver, the wiring capacitance and the gate capacitance of the inputs.
Worst case value: PCA # 1.8 W/gate/MHz at 5 V
Commutation Power
P
CO
= (VDD - VSS) * I
dsohm
Where I
dsohm
is the current flowing into the driver between supply and ground during the
commutation. I
dsohm
is about 15% of the PMOS saturation current.
Worst case value: Pco # 0.7 W/gate/MHz at 5 V
I/O Power Consumption
The power consumption due to the I/Os is:
P3 = Ni * C
O
* (VDD - VSS)
2
* Fi/2
With Ni equals to the number of buffers running at Fi and C
O
is the output capacitance.
Note: If a signal is a clock, Fi = F, if it is a data with random values, Fi = F/4.
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