1
Features
Compatible with an Embedded ARM7TDMI
TM
Processor
Generates Transfers to/from Serial Peripheral such as USART and SPI
Supports Up to Eight USARTs/Four SPIs Parametrizable on Request
One ARM Cycle Needed for a Transfer from Memory to Peripheral
Two ARM Cycles Needed for a Transfer from Peripheral to Memory
Fully Scan Testable up to 98% Fault Coverage
Can be Directly Connected to the Atmel Implementation of the AMBA
TM
Bridge
Not Fully Compatible with AMBA: Retract Response not Supported
Description
The Peripheral Data Controller (PDC) transfers data between on-chip peripherals
such as the USART and SPI and the on- and off-chip memories. This transfer is
achieved via the AMBA Bridge using a simple arbitration mechanism between the
AMBA System Bus (ASB) and the PDC to control Bridge access. This avoids proces-
sor intervention, and removes the processor interrupt handling overhead. This
significantly reduces the number of clock cycles required for a data transfer and, as a
result, improves the performance of the microcontroller and makes it more power-
efficient.
The PDC channels are implemented in pairs, each pair dedicated to a particular
peripheral. One PDC channel in the pair is dedicated to the receiving channel and one
to the transmitting channel of each USART and SPI.
The user interface of a PDC channel is integrated in the memory space of each
peripheral. It contains a 32-bit memory pointer register and a 16-bit transfer count reg-
ister. The peripheral triggers PDC transfers using transmit and receive signals. When
the programmed data is transferred, an end of transfer interrupt is generated by the
corresponding peripheral.
32-bit
Embedded ASIC
Macrocell
Peripheral Data
Controller
(PDC)
Rev. 1363DCASIC04/02
2
Peripheral Data Controller (PDC)
1363DCASIC04/02
Figure 1. PDC Symbol
Table 1. PDC Pin Description
Name
Definition
Type
Active
Level
Comments
Chip-wide
nreset_r
System Reset
Input
Low
Resets all counters and signalsclocked on
rising edge of clock
nreset_f
System Reset
Input
Low
Resets all counters and signalsclocked on
falling edge of clock
clock
System Clock
Input
System clock
nclock
System Clock
Input
Inverted system clock
AMBA System Bus (ASB)
agnt
Grant Signal
Input
High
Arbiter grants the bus to the PDC when this
input is set to 1
bwait
Bus Wait
Input
High
1 cycle wait is required
bridge_sel
Bridge Select
Input
High
From address decoder of system bus
areq
Request Signal
Output
High
Bus request sent to the Arbiter
oe_master_address
Output Enable
Output
High
Output address enablethis signal indicates
that master_add[31:0], blok, bprot[1:0],
bsize[1:0] and bwrite signals are currently
valid with PDC granted on the bus
master_add[31:0]
Address System Bus
Output
Address bus generated by master
blok
Bus Locked
Output
High
Indicates that the ongoing instruction must
not be interrupted
bprot[1:0]
Bus Protection
Output
Protection information
nreset_r
PDC
nreset_f
clock
agnt
bwait
bridge_sel
periph_write
periph_stb
periph_add[13:0]
p_d_in[31:0]
periph_clocks[(per_n
1
-1):0]
periph_rx_rdy[(per_n
1
-1):0]
periph_tx_rdy[(per_n
1
-1):0]
p_sel_periph[(per_n
1
-1):0]
spi_size[(2*spi_n
2
):0]
scan_test_mode
test_si[(1+per_n
1
):1]
test_se
areq
oe_master_address
master_add[31:0]
bprot[1:0]
blok
p_d_out[31:0]
memory_write
-
btran[1:0]
bwrite
bsize[1:0]
pdc_add[20:0]
pdc_sel
pdc_size[1:0]
pdc_write
periph_rx_end[(per_n
1
-1):0]
periph_tx_end[(per_n
1
-1):0]
test_so[(1+per_n
1
):1]
AMBA
System
Bus (ASB)
AMBA
Peripheral
Bus (APB)
Test
Scan
Peripherals
Test Scan
Peripherals
Bridge
AMBA
Peripheral
Bus (APB)
AMBA
System
Bus (ASB)
Memory
Management
Unit/EBI
1 per_n: Number of peripherals
2
spi_n: Number of SPI blocks
nclock
3
Peripheral Data Controller (PDC)
1363DCASIC04/02
bsize[1:0]
Size of Transfer
Output
Bus size
btran[1:0]
Type of Transfer
Output
Bus transfer
bwrite
Bus Write
Output
High
The PDC transfers data from the peripheral
to internal memory
AMBA Peripheral Bus (APB)
periph_write
Peripheral Write Enable
Input
High
From host (Bridge)
periph_stb
Peripheral Strobe
Input
High
From host (Bridge)
periph_add[13:0]
Peripheral Address Bus
Input
From host (Bridge)
p_d_in[31:0]
Peripheral Data Bus
Input
From host (Bridge)user interface data bus
p_d_out[31:0]
Peripheral Data Bus output
Output
User interface data bus
Peripherals
periph_clocks
[per_n-1:0]
Peripheral System Clocks
(USART/SPI)
Input
Per_n values range from 1 to 12. Maximum
number of SPIs is 4. Zero possible.
Maximum number of USARTs is 8. Zero
possible.
LSBs are reserved for USARTs. Remaining
upper bits reserved for SPIs.
periph_rx_rdy
[(per_n-1):0]
Peripheral Receiver Ready
Input
High
Once a character has been received by
peripheral, one of these bits is set to 1.
LSBs are reserved for USARTs. Remaining
upper bits are reserved for SPIs
periph_tx_rdy
[(per_n-1):0]
Peripheral Transmitter Ready
Input
High
Once the holding transmit register is
available, one of these bits is set to 1
spi_size[(2*spi_n):0]
SPI Transfer Sizes
Input
The spi_n is the number of SPIs connected to
the PDC. The MSB is reserved and must be
tied to 0
This value changes the memory pointer
2 bits are reserved for each SPI, for example,
SPI1=SPI_SIZE[1:0], SPI2=SPI_SIZE[3:2].
Each field indicates the size of the transfer
(byte, half-word, word).
p_sel_periph
[(per_n-1):0]
Peripheral selects
Input
High
From host (Bridge)also input of each
peripheral connected
periph_rx_end
[(per_n-1):0]
Peripheral receive end
Output
High
End of receive transfer (each bit corresponds
to a peripheral)the associated buffer for the
channel is full
periph_tx_end
[(per_n-1):0]
Peripheral Transmit End
Output
High
End of transmit transfer (each bit
corresponds to a peripheral)the associated
buffer for the channel is full
Bridge Interface
pdc_add[20:0]
PDC Address Bus
Output
Used by the Bridge to access the peripherals
pdc_sel
PDC Select
Output
High
Used by the Bridge to access the peripherals
Table 1. PDC Pin Description (Continued)
Name
Definition
Type
Active
Level
Comments
4
Peripheral Data Controller (PDC)
1363DCASIC04/02
Scan Test
Configuration
The fault coverage is maximum if all non-scan inputs can be controlled and all non-scan
outputs can be observed. In order to achieve this, the ATPG vectors must be generated
on the entire circuit (top-level) which includes the PDC, or all PDC I/Os must have a top
level access and ATPG vectors must be applied to these pins.
Configuration
The PDC has a standard Atmel Bridge interface that enables the user to configure and
control the data transfers for each channel.
The size of the transfer is configured in an internal 16-bit transfer counter register, and it
is possible, at any moment, to read the number of transfers left for each channel.
The base memory address is configured in a 32-bit memory pointer, by defining the
location of the first access point in the memory. It is possible, at any moment, to read the
location in memory of the next transfer.
The PDC does not have a dedicated status register--the status for each channel is
located in the peripheral. The PDC sends status flags (periph_end) to the peripheral,
which latches the flag in its status register.
System Bus Interface
The PDC interfaces with the AMBA System Bus (ASB) and generates all the control sig-
nals for interfacing with a Memory Management Unit or EBI for memory read and write.
pdc_size[1:0]
PDC Size of Transfer
Output
Multiplex the spi_size inputsused by the
Bridge to determine the size of the transfer
between memories and the SPI
pdc_write
PDC Write
Output
High
Used by the Bridge to access the peripherals
Memory Interface
memory_write
Memory Write from Peripheral
Output
High
Used by Memory Management Unit or EBI to
select data coming from masters or
peripherals (Bridge)
Test Scan
scan_test_mode
Clock Selection for Test
Purposes
Input
High
Tied to 1 during scan testtied to 0 when in
function mode
test_se
Scan Test Enable
Input
High
/low
Scan shift/scan capture
test_si [(1+per_n):1]
Scan Test Input
Input
Entry of scan chain
test_so [(1+per_n):1]
Scan Test Output
Output
Ouput of scan chain
Table 1. PDC Pin Description (Continued)
Name
Definition
Type
Active
Level
Comments
5
Peripheral Data Controller (PDC)
1363DCASIC04/02
Memory Pointers
Each peripheral is connected to the PDC by a receive data channel and a transmit data
channel. Each channel has an internal 32-bit memory pointer. Each memory pointer
points to a location in the system bus memory space (on-chip memory or external bus
interface memory)
Depending on the type of transfer (byte, half-word or word) the memory pointer is incre-
mented by 1, 2 or 4 respectively for SPI transfers.
USART-associated memory pointers only increment by 1.
If a memory pointer is reprogrammed while the PDC is in operation, the transfer
addresses are changed, and the PDC performs transfers using the new address.
Transfer Counters
There is one internal 16-bit transfer counter for each channel. Each counter is used to
count the size of the block already transferred by its associated channel. These
counters are decremented after each data transfer. When the counter reaches zero, the
transfer is complete and the PDC stops transferring data and disables the trigger.
If the counter is reprogrammed while the PDC is operating then the number of transfers
is changed, and the PDC counts transfers from the new value.
Data Transfers
The peripheral triggers PDC transfers using transmit (periph_tx_rdy) and receive
(periph_rx_rdy) signals.
When the peripheral receives an external character, it sends a Receive Ready signal to
the PDC, which then requests access to the system bus (ASB) from the Bus Arbiter.
When access is granted, the PDC starts a read of the peripheral Receive Holding Regis-
ter, via the dedicated pdc_add, pdc_sel, pdc_write and pdc_size signals to the Bridge.
Next, the PDC triggers a write in the memory by setting the ASB control signals and, at
the same time, the Bridge provides the data that is to be written to the memory.
After each transfer, the relevant PDC memory pointer is incremented, and the numbers
of transfers left is decremented. When the memory block size is reached, a signal is
sent to the peripheral and the transfer stops.
The same procedure is followed, in reverse, for transmit transfers.
These timing exchanges are shown in Figures 4, 5, 6, 7, and 8.
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