T5552
Rev. A1, 04-May-01
1 (12)
Read/Write IDIC Micromodule with 1 Kbit Memory
Description
The T5552 is a two terminal, contactless
R/W-IDentification IC (IDIC
)* for tag applications in
the 125 kHz (
25 kHz) range. The IC uses the external
RF signal to generate it's own power supply and internal
clock reference. It is built into a standard micromodule
wich is suitable for contactless R/W identification ap-
plications. It is a plastic encapsulated package on a copper
lead-frame substate.
The micromodule contains the IDIC with a total of
1056
bits of EEPROM memory grouped into 32
individually addressable data blocks and a 435-pF capaci-
tor. Each block of the IDIC is made up of 32 bits of data
plus an associated lock bit for block write protection.
Blocks 1 to 31 are provided for user related data and block
0 for system configuration.
Data is transmitted from the IC (uplink) using reflective
load (backscatter) modulation. This is achieved by
damping the external RF field by switching a resistive
load between the two terminals ClockA/ClockB as
shown in figure 14 (downlink). The IC receives and
decodes amplitude modulated data from the base station.
As soon as the tag included the T5552 is exposed to an RF
field and the field is strong enough to derive enough
energy to operate, the tag will respond by continuously
transmitting stored data (uplink mode). The base station
can at any time switch the tag into downlink mode to write
new user or configuration data. Generally the tag will
automatically return to the default uplink mode when the
downlink transfer is complete or interrupted or if an error
condition occurs.
Features
D Low power, low voltage operation
D Contactless power supply
D Contactless read/write data transmission
D Radio Frequency (RF): 100 kHz to 150 kHz
D 1056 bits of EEPROM memory
D 992 bits (31 x 32 bits) of user memory
D Defined start of data transmission
D Auto-verify after EEPROM programming
D 400 mm thickness of the micromodule
D 435-pF capacitor
D Block write protection for each block
D Configurable options include:
Modulation type:
PSK | Manchester
Bit rate [bit/s]:
RF/16 | RF/32
Max block feature
Modulation defeat
POR start-up delay:
1 ms |
65 ms
Applications
D Industrial asset management
D Process control and automation
D Logistic process flow monitoring
Transponder
Base station
Power
Transponder
Base station
Data
Power
Controller
Data
downlink
uplink
Memory
Coil interface
C
Micromodule
Coil 1
Coil 2
Figure 1. Transponder system example using T5552
*
IDIC
stands for IDentification Integrated Circuit and is a trademark of Atmel Wireless & Microcontrollers
T5552
Rev. A1, 04-May-01
2 (12)
Ordering Information
Extended Type Number
Package
Remarks
T555200 PAE
Micromodule
Reel; 35 mm; 3 rows; 435 pF
Functional Modules
Analog Front End (AFE)
The analog front end (AFE) includes all circuits which are
directly connected to the coil. It generates the IC's power
supply and handles the bidirectional data communication
with the basestation. It consists of the following blocks:
D Rectifier to generate a DC supply voltage from the AC
coil voltage.
D ESD protection
D Clock extractor
D Switchable load between Coil 1/ Coil 2 for data trans-
mission from the IC to the reader electronics (uplink
mode).
D Field gap detector for data transmission from the base
station to the IC (downlink mode).
Controller
The control logic is responsible for the following:
D Initializing and refresh configuration register from
EEPROM block 0.
D Controlling read and write memory accesses.
D Handling data transmission and opcode decoding.
D Error detection and error handling.
Clock Extraction
The clock extraction circuit generates the internal clock
source out of the external RF signal.
Data Rate Generator
The data rate in uplink mode can be selected to operate
at either RF/16 (nominally 7.81 kHz, default) or RF/32
(nominally 3.91 kHz).
Bit Decoder
This function block decodes the field gaps and verifies the
validity of the incoming data stream.
Charge Pump
This circuit generates the high voltage required for pro-
gramming the EEPROM.
Power-On Reset (POR)
This circuit delays the IC's functionality until an accept-
able voltage threshold has been reached.
Mode Register
This register holds the configuration data bits stored in
EEPROM block 0. It is refreshed at the start of every
block read operation.
Modulator
The modulator encodes the serial data stream shifted out
of the selected EEPROM data block and controls the
damping circuit in the AFE. The T5552 frontend supports
PSK and Manchester encoding.
T5552
Rev. A1, 04-May-01
3 (12)
Mode
register
Analog front end
(rectifier, regulator, clock extractor, ESD protection)
POR
Bit decoder
Bit rate generator
EEPROM memory
Start-up
delay
Charge
pump
Controller
Input register
Modulator
Coil 2
Coil 1
16543
Figure 2. Functional block diagram
Operating the T5552
Damping on
Damping off
Power-on reset
Read data with selected
modulation and bitrate
16547
Loading block 0 (114 FC
[ 1 ms),
start-up delay inactive
Figure 3. Voltage at Coil 1/ Coil 2 after power on
General
The basic functions of the T5552 are to supply the IC from
the RF field, read data out of the EEPROM and shift them
to the modulator, receive data and program these data bits
into the EEPROM. An error detecting circuit prevents the
EEPROM from being written with wrong data.
Power Supply
The IC is supplied via a tuned LC circuit which is con-
nected to the Coil 1/Coil 2 pads. The incoming RF
induces a current in the coil. The on-chip rectifier gener-
ates the DC supply voltage. Overvoltage protection
prevents the IC from damage due to high field strengths.
Depending on the coil, the open-circuit voltage across the
LC circuit can reach more than 100 V.
Initialization
The occurrence of a RF field triggers a poweron reset
pulse, ensuring a defined start-up. The Power-On-Reset
circuit (POR) remains active until an adequate voltage
threshold has been reached. This in turn triggers the de-
fault start-up delay sequence. During this period of 114
field clock cycles (FC) the T5552 is initialized with the
configuration data stored in EEPROM block 0. This is fol-
lowed by an additional delay time which is defined by the
"Start-up Delay" bit.
If the "Start-up Delay" bit is set the T5552 remains inac-
tive until 8192 RF clock cycles have occured. If this
option is deactivated, no delay is observed after the con-
figuration period of 114 RF clock cycles (
1 ms).
T5552
Rev. A1, 04-May-01
4 (12)
Block 1
Block 2
Block 30
Block 31
MAXBLK = 31
MAXBLK = 1
MAXBLK = 2
Block 1
Block 1
Block 1
Block 1
Block 1
Block 1
Block 2
Block 1
Block 2
Block 1
16546
0
0
0
Loading block 0
Loading block 0
Loading block 0
MAXBLK = 0
Block 0
Block 0
Block 0
Block 0
Block 0
0
Loading block 0
Block 1
Block 1
Block 2
Block 0
Block 2
Block 1
Block 1
Block 0
....
....
....
....
(not transmitted)
Refreshing configuration register
Figure 4. Datastream pattern depending on MAXBLK
Any field gap occuring during initialization will restart
the complete sequence.
T
INIT
= (114 + 8,192*delay bit)/125 kHz
65 ms
After this initialization time the T5552 enters uplink
mode and modulation starts automatically using the pa-
rameters defined in the configuration block.
Uplink Operation
All transmissions from the IC to the base station utilizes
amplitude modulation (ASK) of the RF carrier. This takes
place by switching a resistive load between the coil pads
(Coil 1 and Coil 2) which in turn modulates the RF field
generated by the base station (reflective backscatter mod-
ulation).
MaxBlock
Data from the memory is serially transmitted, starting
with block 1, bit 1, up to the last block (MAXBLK), bit
32. The last block which will be transmitted is defined by
the mode parameter field MAXBLK is stored in EE-
PROM block 0. When the MAXBLK address has been
reached, data transmission restarts with block 1.
The user defines the cyclic datastream by setting the
MAXBLK between 0 and 31 (representing each of the 32
data blocks). If set to 1, only block 1 is transmitted. If set
to 31, blocks 1 to 31 will be sequentially transmitted. If
set to 0, only the contents of the configuration block (nor-
mally not accessible) will be transmitted (see figure 4).
On the other hand it is also possible to access a single data
block selectively, independant of the MAXBLK value,
with the direct access command (Opcode `11'). The thus
addressed data block is transmitted repeatedly.
Data Encoding
Everytime when entering uplink mode, the data stream is
preceeded by a single start bit (always `0'). Then the data
stream continues with block 1, bit 1, and continues
through MAXBLK, bit 32. This data stream pattern
cycles continuously.
The modulator is configurable for
D MANCHESTER
Manchester encoded data represent a logical `1' with a
rising edge and a logical `0' with a falling edge.
D PSK using sub-carrier frequency RF/2
The PSK modulator changes phase with each change of
data. The first phase shift represents a data change from
`0' > `1'.
T5552
Rev. A1, 04-May-01
5 (12)
16552
8 FC
8 FC
Data rate =
16 Field Clocks (FC)
Datastream
Manchester
encoded
RF-field
1
0
0
1
9
2
1
16
8
1
8
1
8
9
16
16 1
8
9
16
Figure 5. Example of Manchester encoding with data rate RF/16
Datastream
Inverted
modulator
signal
subcarrier RF/2
RF-field
1
0
0
1
8 FC
8 FC
Data rate =
16 Field Clocks (FC)
2
1
8 9
161
8
16 1
8
16 1
8
16559
Figure 6. Example of PSK encoding with data rate RF/16
Downlink Operation
Data is transmitted from the base station by amplitude
modulation of the field (m = 1) using a series of so called
gaps. With the exception of the initial synchronisation
gap (start gap), all field gaps have the same duration, the
logical data being encoded in the length of the unmodu-
lated phases (see figure 7)
A valid data stream is always preceeded by a start gap
which is approximately twice as long as a normal field
gap. Detection of this first gap causes the T5552 to switch
immediately into the downlink mode where it can receive
and decode the following data stream. This stream con-
sists of two opcode bits, followed by (0, 3 or 5) address
bits and finally (0 or 33) data bits (including the lock bit).
In downlink mode the transponder damping is perma-
PDF 
ZIP