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Электронный компонент: T5753

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Rev. 4510FRKE07/04
Features
Integrated PLL Loop Filter
ESD Protection (4 kV HBM/ 200 V MM; Except Pin 2: 4 kV HBM/ 100 V MM)
also at ANT1/ANT2
High Output Power (8.0 dBm) with Low Supply Current (9.0 mA)
Modulation Scheme ASK/FSK
FSK Modulation is Achieved by Connecting an Additional Capacitor Between the
XTAL Load Capacitor and the Open Drain Output of the Modulating Microcontroller
Easy to Design-in Due to Excellent Isolation of the PLL from the PA and Power Supply
Single Li-cell for Power Supply
Supply Voltage 2.0 V to 4.0 V in the Temperature Range of -40
C to 85
C/125
C
Package TSSOP8L
Single-ended Antenna Output with High Efficient Power Amplifier
CLK Output for Clocking the Microcontroller
One-chip Solution with Minimum External Circuitry
125
C Operation for Tire Pressure Systems
Description
The T5753 is a PLL transmitter IC which has been developed for the demands of RF
low-cost transmission systems at data rates up to 32 kBaud. The transmitting
frequency range is 310 MHz to 330 MHz. It can be used in both FSK and ASK
systems.
Figure 1. System Block Diagram
Demod.
IF Amp
LNA
VCO
PLL
XTO
Control
U3741B/
U3745B/
T5743/
T5744
1...3
Mic
r
o-
c
ont
ro
ll
e
r
Power
amp.
XTO
VCO
PLL
T5753
Antenna Antenna
UHF ASK/FSK
Remote control transmitter
UHF ASK/FSK
Remote control receiver
Encoder
ATARx9x
1 Li cell
Keys
UHF ASK/FSK
Transmitter
T5753
2
T5753
4510FRKE07/04
Pin Configuration
Figure 2. Pinning TSSOP8L
1
2
3
4
8
7
6
5
CLK
PA_ENABLE
ANT2
ANT1
ENABLE
GND
VS
XTAL
T5753
Pin Description
Pin
Symbol
Function
Configuration
1
CLK
Clock output signal for microcontroller
The clock output frequency is set by the
crystal to f
XTAL
/4
2
PA_ENABLE
Switches on power amplifier, used for
ASK modulation
3
4
ANT2
ANT1
Emitter of antenna output stage
Open collector antenna output
5
XTAL
Connection for crystal
6
VS
Supply voltage
See ESD protection circuitry (see Figure 8 on page 8)
7
GND
Ground
See ESD protection circuitry (see Figure 8 on page 8)
8
ENABLE
Enable input
CLK
VS
100
100
PA_ENABLE
50k
U
ref
= 1.1V
20 A
ANT1
ANT2
XTAL
1.2k
VS
1.5k
VS
182 A
ENABLE
200k
3
T5753
4510FRKE07/04
Figure 3. Block Diagram
General Description
This fully integrated PLL transmitter allows particularly simple, low-cost RF miniature
transmitters to be assembled. The VCO is locked to 32 f
XTAL
hence a 9.8438 MHz
crystal is needed for a 315 MHz transmitter. All other PLL and VCO peripheral elements
are integrated.
The XTO is a series resonance oscillator so that only one capacitor together with a
crystal connected in series to GND are needed as external elements.
The crystal oscillator together with the PLL needs typically < 3 ms until the PLL is locked
and the CLK output is stable. There is a wait time of
3 ms until the CLK is used for the
microcontroller and the PA is switched on.
The power amplifier is an open-collector output delivering a current pulse which is nearly
independent from the load impedance. The delivered output power is hence controllable
via the connected load impedance.
This output configuration enables a simple matching to any kind of antenna or to 50
. A
high power efficiency of
= P
out
/(I
S,PA
V
S
) of 40% for the power amplifier results when
an optimized load impedance of Z
Load
= (255 + j192)
is used at 3 V supply voltage.
CLK
PA_ENABLE
ANT2
ANT1
ENABLE
GND
VS
XTAL
1
2
3
4
5
6
7
8
VCO
LF
CP
f
32
XTO
PLL
PA
f
4
Power up/down
T5753
PFD
4
T5753
4510FRKE07/04
Functional
Description
If ENABLE = L and the PA_ENABLE = L, the circuit is in standby mode consuming only
a very small amount of current so that a lithium cell used as power supply can work for
several years.
With ENABLE = H the XTO, PLL and the CLK driver are switched on. If PA_ENABLE
remains L only the PLL and the XTO is running and the CLK signal is delivered to the
microcontroller. The VCO locks to 32 times the XTO frequency.
With ENABLE = H and PA_ENABLE = H the PLL, XTO, CLK driver and the power
amplifier are on. With PA_ENABLE the power amplifier can be switched on and off,
which is used to perform the ASK modulation.
ASK Transmission
T h e T 5 7 5 3 i s a c t i v a t e d b y E N A B L E = H . P A _ E N A B L E m u s t r e m a i n L f o r
typically
3 ms, then the CLK signal can be taken to clock the microcontroller and the
output power can be modulated by means of Pin PA_ENABLE. After transmission
PA_ENABLE is switched to L and the microcontroller switches back to internal clocking.
The T5753 is switched back to standby mode with ENABLE = L.
FSK Transmission
T h e T 5 7 5 3 i s a c t i v a t e d b y E N A B L E = H . P A _ E N A B L E m u s t r e m a i n L f o r
typically
3 ms, then the CLK signal can be taken to clock the microcontroller and the
power amplifier is switched on with PA_ENABLE = H. The chip is then ready for FSK
modulation. The microcontroller starts to switch on and off the capacitor between the
XTAL load capacitor and GND with an open-drain output port, thus changing the refer-
ence frequency of the PLL. If the switch is closed, the output frequency is lower than if
the switch is open. After transmission PA_ENABLE is switched to L and the microcon-
troller switches back to internal clocking. The T5753 is switched back to standby mode
with ENABLE = L.
The accuracy of the frequency deviation with XTAL pulling method is about 25% when
the following tolerances are considered.
Figure 4. Tolerances of Frequency Modulation
Using C
4
= 8.2 pF 5%, C
5
= 10 pF 5%, a switch port with C
Switch
= 3 pF 10%, stray
capacitances on each side of the crystal of C
Stray1
= C
Stray2
= 1 pF 10%, a parallel
capacitance of the crystal of C
0
= 3.2 pF 10% and a crystal with C
M
= 13 fF 10%, an
FSK deviation of 21.5 kHz typical with worst case tolerances of 16.25 kHz to
28.01 kHz results.
CLK Output
An output CLK signal is provided for a connected microcontroller, the delivered signal is
CMOS compatible if the load capacitance is lower than 10 pF.
Clock Pulse Take-over
The clock of the crystal oscillator can be used for clocking the microcontroller. Atmel's
ATARx9x has the special feature of starting with an integrated RC-oscillator to switch on
the T5753 with ENABLE = H, and after 1 ms to assume the clock signal of the transmis-
sion IC, so that the message can be sent with crystal accuracy.
~
~
V
S
XTAL
C
Stray1
C
M
L
M
R
S
C
0
C
Stray2
C
4
C
5
Crystal equivalent circuit
C
Switch
5
T5753
4510FRKE07/04
Output Matching and Power
Setting
The output power is set by the load impedance of the antenna. The maximum output
power is achieved with a load impedance of Z
Load,opt
= (255 + j192)
. There must be a
low resistive path to V
S
to deliver the DC current.
The delivered current pulse of the power amplifier is 9 mA and the maximum output
power is delivered to a resistive load of 400
if the 1.0 pF output capacitance of the
power amplifier is compensated by the load impedance.
An optimum load impedance of:
Z
Load
= 400
|| j/(2
1.0 pF) = (255 + j192)
thus results for the maximum output
power of 8 dBm.
The load impedance is defined as the impedance seen from the T5753's ANT1, ANT2
into the matching network. Do not confuse this large signal load impedance with a small
signal input impedance delivered as input characteristic of RF amplifiers and measured
from the application into the IC instead of from the IC into the application for a power
amplifier.
Less output power is achieved by lowering the real parallel part of 400
where the
parallel imaginary part should be kept constant.
Output power measurement can be done with the circuit of Figure 5. Note that the com-
ponent values must be changed to compensate the individual board parasitics until the
T5753 has the right load impedance Z
Load,opt
= (255 + j192)
. Also the damping of the
cable used to measure the output power must be calibrated out.
Figure 5. Output Power Measurement
Application Circuit
For the blocking of the supply voltage a capacitor value of C
3
= 68 nF/X7R is recom-
mended (see Figure 6 on page 6 and Figure 7 on page 7). C
1
and C
2
are used to match
the loop antenna to the power amplifier where C
1
typically is 22 pF/NP0 and C
2
is
10.8 pF/NP0 (18 pF + 27 pF in series); for C
2
two capacitors in series should be used to
achieve a better tolerance value and to have the possibility to realize the Z
Load,opt
by
using standard valued capacitors.
C
1
forms together with the pins of T5753 and the PCB board wires a series resonance
loop that suppresses the 1
st
harmonic, hence the position of C
1
on the PCB is important.
Normally the best suppression is achieved when C
1
is placed as close as possible to the
pins ANT1 and ANT2.
The loop antenna should not exceed a width of 1.5 mm, otherwise the Q-factor of the
loop antenna is too high.
L
1
([50 nH to 100 nH) can be printed on PCB. C
4
should be selected that the XTO runs
on the load resonance frequency of the crystal. Normally, a value of 12 pF results for a
15 pF load-capacitance crystal.
~
~
ANT2
ANT1
R
in
Power
meter
C
1
= 1n
L
1
= 56n
C
2
= 3.3p
Z
Lopt
V
S
Z = 50
50