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Электронный компонент: U2731B-M

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U2731B
Preliminary Information
Rev. A2, 09-Oct-00
1 (20)
DAB One-Chip Front End
Description
The U2731B is a monolithically integrated DAB
one-chip front end circuit manufactured using Atmel
Wireless & Microcontrollers' advanced UHF5S
technology. Its functionality covers a gain-controlled RF
amplifier with two selectable RF inputs, a gain-controlled
RF mixer, a VCO which provides the LO signal for the RF
mixers, either directly or after passing a frequency
divider, a SAW filter driver, an AGC block for the RF
section, a gain-controlled IF amplifier, an IF mixer which
can also be bypassed, an AGC block for the IF section and
a fractional-N frequency synthesizer. The frequency
synthesizer controls the VCO to synthesize frequencies in
the range of 70 MHz to 500 MHz in a 16-kHz raster;
within certain limits the reference divide factor is fully
programmable. The lock status of the phase detector is
indicated at a special output pin; three switching outputs
can be addressed. A reference signal which is generated
by an on-chip reference oscillator is available at an output
pin. This reference signal is also used to generate the LO
signal for the IF mixer, either by doubling the frequency
or by using the reference frequency itself. Three D/A
converters at a resolution of 8 bits provide a digitally
controllable output voltage. The thresholds inside the
AGC blocks can be digitally controlled by means of
on-chip 4-bit D/A converters. All functions of this IC are
controlled by the I
2
C bus.
Electrostatic sensitive device.
Observe precautions for handling.
Features
D 8.5 V supply voltage
D Voltage regulator for stable operating conditions
D Microprocessor controlled via an I
2
C bus
D 4 addresses selectable
D Gain-controlled RF amplifier with two inputs,
selectable by I
2
C-bus control
D Balanced RF amplifier inputs
D Gain-controlled RF mixer
D Four-pin voltage-controlled oscillator
D SAW filter driver with differential low-impedance
output
D AGC voltage generation for RF section, available at
charge-pump output (can also be used to control a PIN
diode attenuator)
D Gain-controlled IF amplifier
D Balanced IF amplifier inputs
D Selectable gain-controlled IF mixer
D Single-ended IF output
D AGC voltage generation for IF section, available at
charge-pump output
D Separate differential input for the IF AGC block
D All AGC time constants adjustable
D AGC thresholds programmable via the I
2
C bus
D Three AGC charge pump currents selectable
(zero, low, high)
D Reference oscillator
D Programmable 9-bit reference divider
D Programmable 15-bit counter 1:2048 to 1:32767
effectively
D Tristate phase detector with programmable charge
pump
D Superior phase-noise performance
D Deactivation of tuning output programmable
D 3 switching outputs (open collector)
D 3 D/A converters (resolution: 8 bits)
D Lock status indication (open collector)
Ordering Information
Extended Type Number
Package
Remarks
U2731B-MFN
SSO44
Tube
U2731B-MFNG1
SSO44
Taped and reeled
U2731B
Rev. A2, 09-Oct-00
Preliminary Information
2 (20)
Block Diagram
15037
Programmable
13bit counter
N/N+1
FractionalN
control
Reference
counter
15bit latch
9bit latch
4bit latch
Switches
MUX
MUX
3bit latch
Tristate
phase
detector
Programmable
charge pump
8bit latch
8bit latch
8bit latch
OSCI
42
OSCO
43
FREF
5
I
2
C businterface/control
D/A
D/A
D/A
VD
40
Lock
detector
4bit latch
PLCK
41
PD
39
D/A
x1/x2
1/ 2
C1VCO
32
B2VCO
B1VCO
C2VCO
33
34
35
VCO
RFA1
RFA2
12
13
RFB1
RFB2
14
15
th1
th2
19
18
23
24
28
SAW1
SAW2
IFIN1 IFIN2
CPIF
th3
IF
AGCIN2
26
IF
AGCIN1
27
SLI
21
WAGC
22
IFOUT
29
10, 11, 17, 30, 31,36, 37
VS
20, 25, 38
1
SCL
44
ADR
2
SDA
6
SWC
4
SWB
3
SWA
7
CAO
8
CBO
9
CCO
V
AGC
V
AGC
D/A
D/A
4bit latch
4bit latch
4bit latch
CPRF
16
GND
Figure 1. Block diagram
U2731B
Preliminary Information
Rev. A2, 09-Oct-00
3 (20)
Pin Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
ADR
OSCO
OSCI
VD
PD
VS
GND
GND
C2VC
B2VCO
C1VC
GND
GND
IFOUT
CPIF
IFAGCIN1
IFAGCIN2
VS
IFIN1
IFIN2
SDA
SWA
SWB
FREF
SWC
CAO
CCO
GND
RFA1
RFB2
CPRF
GND
SAW1
SAW2
VS
SLI
WAGC
14855
RFB1
SCL
PLCK
B1VCO
RFA2
GND
CBO
Figure 2. Pinning
Pin
Symbol
Function
1
SCL
Clock (I
2
C bus)
2
SDA
Data (I
2
C bus)
3
SWA
Switching output (open collector)
4
SWB
Switching output (open collector)
5
FREF
Ref. frequency output (for U2730B)
6
SWC
Switching output (open collector)
7
CAO
Output of D/A converter A
8
CBO
Output of D/A converter B
9
CCO
Output of D/A converter C
10
GND
Ground
11
GND
Ground
12
RFA1
Input 1 of RF amplifier A (differential)
13
RFA2
Input 2 of RF amplifier A (differential)
14
RFB1
Input 1 of RF amplifier B (differential)
15
RFB2
Input 2 of RF amplifier B (differential)
16
CPRF
Charge-pump output (RF AGC block)
17
GND
Ground
18
SAW1
SAW driver output 1 (differential)
19
SAW2
SAW driver output 2 (differential)
20
VS
Supply voltage
21
SLI
AGC mode selection
(charge-pump current high)
22
WAGC
AGC mode selection
(charge-pump current off)
23
IFIN2
Input 2 of IF amplifier (differential)
24
IFIN1
Input 1 of IF amplifier (differential)
25
VS
Supply voltage
26
IFAGCIN2
Input 2 of IF AGC block (differential)
27
IFAGCIN1
Input 1 of IF AGC block (differential)
28
CPIF
Charge-pump output (IF AGC block)
29
IFOUT
IF output (single ended)
30
GND
Ground
31
GND
Ground
32
C1VC
Collector 1 of VCO
33
B2VCO
Base 2 of VCO
34
B1VCO
Base 1 of VCO
35
C2VC
Collector 2 of VCO
36
GND
Ground
37
GND
Ground
38
VS
Supply voltage
39
PD
Tristate charge pump output
40
VD
Active-filter output
41
PLCK
Lock-indicating output (open collector)
42
OSCI
Input of reference oscillator/buffer
43
OSCO
Output of reference oscillator/buffer
44
ADR
Address selection (I
2
C bus)
U2731B
Rev. A2, 09-Oct-00
Preliminary Information
4 (20)
Functional Description
The U2731B-A represents a monolithically integrated
front end IC designed for applications in DAB receivers.
It covers RF and IF signal processing, the PLL section and
also supporting functions such as D/A converters or
switching outputs.
Two RF input ports offer the possibility of handling
various input signals such as a down-converted L-band
signal or band II and band III RF signals. The high
dynamic range of the RF inputs and the use of a
gain-controlled amplifier and a gain-controlled mixer in
the RF section offer the possibility of even strong RF
input signals. The LO signal of the first mixer stage is
derived from an on-chip VCO. The VCO frequency is
either divided by two or directly fed to the mixer. In this
way band II and band III can be covered easily.
In the IF section, it can be selected if the first IF signal is
down-converted to a second, lower IF or if it is simply
amplified to appear at the IF output. If the down-
conversion option is chosen, it can be selected if the LO
signal of the IF mixer is directly derived from the
reference signal of the PLL, or if it is generated by
doubling its frequency. The amplifiers in the IF section
are gain-controlled in similar fashion to the RF section.
The RF and the IF part also contain AGC functional
blocks which generate the AGC control voltages. The
AGC thresholds can be defined by means of three on-chip
4-bit D/A converters.
The frequency of the VCO is locked to a reference
frequency by an on-chip fractional-N PLL circuit which
guarantees a superior phase-noise performance. The
reference frequency is generated by an on-chip crystal
oscillator which can also be overdriven by an external
signal. Starting from a minimum value, the reference
scaling factor is freely programmable.
Three switching outputs can be used for various switching
tasks on the front end board. Three 8-bit D/A converters
providing an output voltage between 0 and 8.5 V are used
to improve the tuning voltages of the tuned preselectors
which are derived from the tuning voltage of the VCO.
All functions of this circuit are controlled by an I
2
C bus.
RF Part
RF Gain-Controlled Amplifier
In order to support two different channels, two identical
input buffers with balanced inputs (RFA1, RFA2; RFB1,
RFB2) are integrated. By setting the I
2
C bus bits M0 and
M1 (see section `I
2
C-bus functions'),the active buffer can
be selected. The buffers are followed by a gain-controlled
amplifier whose output signal is fed to a gain-controlled
mixer. The RF amplifiers are capable of handling input
signals up to a power of 6 dBm without causing
third-order intermodulation components stronger than
40 dBc.
RF Gain-Controlled Mixer,
VCO and LO Divider
The purpose of the RF mixer is to down-convert the
incoming signal (band II, band III) to an IF frequency
which is typically 38.912 MHz. This IF signal is fed to an
AGC voltage-generation block (which is described in the
following section) and an output buffer stage. This driver
stage has a low output impedance and is capable to drive
a SAW filter directly via its differential output Pins
SAW1, SAW2. The mixer's LO signal is generated by a
balanced voltage-controlled oscillator whose frequency
is stabilized by a fractional-N phase-locked loop. An
example circuit of the VCO is shown in figure 12. The
oscillator 's tank is applied to the Pins B1VC, C1VC,
B2VC, C2VC as shown in the application circuit in
figure 6. Before the VCO's signal is fed to the RF mixer,
it has to pass an LO divider block where the VCO
frequency is either divided by 1 or 2. The setting of this
divider is defined by means of the I
2
C-bus bits M0 and M1
as indicated in the section `I
2
C-bus functions'. This
feature offers the possibility of covering both band II and
band III by tuning the VCO frequency in the range
between 200 MHz to 300 MHz.
U2731B
Preliminary Information
Rev. A2, 09-Oct-00
5 (20)
RF AGC Voltage-Generation Block
In this functional block, the output signal of the RF mixer
is amplified, weakly bandpass filtered (transition range:
X8 MHz to X80 MHz), rectified and finally lowpass
filtered. The voltage derived in this `power-measurement
process' is compared to a voltage threshold (th1) which
can be digitally controlled by an on-chip 4-bit D/A
converter. The setting of this converter is defined by
means of the I
2
C-bus bits TAi (i = 1, 2, 3, 4). Depending
on the result of this comparison, a charge pump feeds a
positive or negative current to Pin CPRF in order to
charge or discharge an external capacitor. The voltage of
this external capacitor can be used to control the gain of
an external preamplifier or attenuator stage: Furthermore,
it is also used to generate the internal control voltages of
an RF amplifier and mixer. For this purpose, the voltage
at Pin CPRF is compared to a voltage threshold (th2)
which is also controlled by an on-chip 4-bit D/A converter
whose setting is fixed by the I
2
C-bus bits
TBi (i =1, 2, 3, 4).
By means of the input Pins WAGC and SLI the current of
the RF AGC charge pump can be selected according to the
following table:
WAGC
SLI
Charge-Pump Current /
mA
HIGH
X
off
LOW
LOW
50
mA (slow mode)
LOW
HIGH
190
mA (fast mode)
The block functionality can be seen in figure 10.
IF Part
IF Gain-Controlled Amplifier
The signal applied to the balanced input Pins IFIN1,
IFIN2 is amplified by a gain-controlled IF amplifier. The
gain-control signal is generated by an IF AGC voltage-
generation block which is described in the next section.
To avoid offset problems, the output of the
gain-controlled amplifier is fed to an amplifier/mixer
combination by AC coupling.
IF Gain-Controlled Amplifier/Mixer
Combination
Depending on the setting of the I
2
C-bus bits M2, M3, the
output signal of the gain-controlled IF amplifier is either
mixed down to a lower, second IF or, after passing an
output buffer stage, amplified before it appears at the
single-ended output Pin IFOUT. If the down-conversion
option is chosen this circuit still offers two possibilities
concerning the synthesis of the IF mixers LO signal. This
LO signal is derived from the PLL's on-chip reference
oscillator. By means of the I
2
C-bus bits M2, M3, it can be
decided whether the reference frequency is doubled
before it is given to the mixer's LO port, or if it is used
directly. The gain-control voltage of the amplifier/mixer
combination is similar to the gain-controlled IF amplifier
generated by an internal gain-control circuit.
IF AGC Voltage-Generation Block
The purpose of this gain-control circuit in the IF part is to
measure the power of the incoming signal at the balanced
input Pins IFAGCIN1, IFAGCIN2, to compare it with a
certain power level and to generate a control voltage for
the IF gain-controlled amplifiers and mixer. This
architecture offers the possibility of ensuring an optimal
use of the dynamic range of the A/D converter which
transforms the output signal at Pin IFOUT from the
analog to the digital domain despite possible insertion
losses of (anti-aliasing) filters which are arranged in front
of the converter. Such a constellation is indicated in the
application circuit in figure 6.
The incoming signal at the balanced input Pins IFAGC1,
IFAGC2 passes a `power-measurement process' similar
to that described in the section `RF AGC Voltage-
Generation Block'. For flexibility reasons, no bandpass
filtering is implemented. The voltage derived in this
process is compared to a voltage threshold (th3) which is
defined by an on-chip 4-bit D/A converter. The setting of
this converter is defined by the I
2
C-bus bits
TCi (i = 1, 2, 3, 4). Depending on the result of this
comparison, a charge pump feeds a positive or negative
current to Pin CPIF in order to charge or discharge an
external capacitor. By means of the Pins WAGC and SLI
the current of this charge pump can be selected according
to the following table:
WAGC
SLI
Charge Pump Current /
mA
HIGH
X
off
LOW
LOW
50
mA (slow mode)
LOW
HIGH
190
mA (fast mode)
The block functionality can be seen in figure 11.