ChipFind - документация

Электронный компонент: U2731B-NFNG1

Скачать:  PDF   ZIP
Rev. 4671CDAB06/04
Features
8.5 V Supply Voltage
Voltage Regulator for Stable Operating Conditions
Microprocessor-controlled Via a Simple Two-wire Bus
Two Addresses Selectable
Gain-controlled RF Amplifier with Two Inputs, Selectable Via a Simple Two-wire Bus
Control
Balanced RF Amplifier Inputs
Gain-controlled RF Mixer
Four-pin Voltage-controlled Oscillator
SAW Filter Driver with Differential Low-impedance Output
AGC Voltage Generation for RF Section, Available at Charge-pump Output
(Can Also Be Used to Control a PIN Diode Attenuator)
Gain-controlled IF Amplifier
Balanced IF Amplifier Inputs
Selectable Gain-controlled IF Mixer
Single-ended IF Output
AGC Voltage Generation for IF Section, Available at Charge-pump Output
Separate Differential Input for the IF AGC Block
All AGC Time Constants Adjustable
AGC Thresholds Programmable Via a Simple Two-wire Bus
Three AGC Charge Pump Currents Selectable (Zero, Low, High)
Reference Oscillator
Programmable 9-bit Reference Divider
Programmable 15-bit Counter 1:2048 to 1:32767 Effectively
Tristate Phase Detector with Programmable Charge Pump
Superior Phase-noise Performance
Deactivation of Tuning Output Programmable
Three Switching Outputs (Open Collector)
Three D/A Converters (Resolution: 8 Bits)
Lock Status Indication (Open Collector)
Electrostatic sensitive device.
Observe precautions for handling.
Description
The U2731B is a monolithically integrated Digital Audio Broadcasting one-chip front
end circuit manufactured using Atmel's advanced UHF5S technology. Its functionality
covers a gain-controlled RF amplifier with two selectable RF inputs, a gain-controlled
RF mixer, a VCO which provides the LO signal for the RF mixers, either directly or
after passing a frequency divider, a SAW filter driver, an AGC block for the RF section,
a gain-controlled IF amplifier, an IF mixer which can also be bypassed, an AGC block
for the IF section and a fractional-N frequency synthesizer. The frequency synthesizer
controls the VCO to synthesize frequencies in the range of 70 MHz to 500 MHz in a
16-kHz raster; within certain limits the reference divider factor is fully programmable.
The lock status of the phase detector is indicated at a special output pin; three switch-
ing outputs can be addressed. A reference signal which is generated by an on-chip
reference oscillator is available at an output pin. This reference signal is also used to
generate the LO signal for the IF mixer, either by doubling the frequency or by using
the reference frequency itself. Three D/A converters at a resolution of 8 bits provide a
digitally controllable output voltage. The thresholds inside the AGC blocks can be digi-
tally controlled by means of on-chip 4-bit D/A converters. All functions of this IC are
controlled via a simple two-wire bus.
DAB One-chip
Front End
U2731B
2
U2731B
4671CDAB06/04
Figure 1. Block Diagram
Programmable
13-bit counter
N/N+1
Fractional-N
control
Reference
counter
15-bit latch
9-bit latch
4-bit latch
Switches
MUX
MUX
3-bit latch
Tristate
phase
detector
Programmable
charge pump
8-bit latch
8-bit latch
8-bit latch
OSCI
42
OSCO
43
FREF
5
Simple two-wire bus interface/control
D/A
D/A
D/A
VD
40
Lock
detector
4-bit latch
PLCK
41
PD
39
D/A
x1/x2
1/ 2
C1VCO
32
B2VCO
B1VCO
C2VCO
33
34
35
VCO
RFA1
RFA2
12
13
RFB1
RFB2
14
15
th1
th2
19
18
23
24
28
SAW1
SAW2
IFIN1
IFIN2
CPIF
th3
IF
AGCIN2
26
IF
AGCIN1
27
SLI
21
WAGC
22
IFOUT
29
10, 11, 17, 30, 31,36, 37
VS
20, 25, 38
1
SCL
44
ADR
2
SDA
6
SWC
4
SWB
3
SWA
7
CAO
8
CCO
9
CBO
V
AGC
V
AGC
D/A
D/A
4-bit latch
4-bit latch
4-bit latch
CPRF
16
GND
3
U2731B
4671CDAB06/04
Pin Configuration
Figure 2. Pinning
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
ADR
OSCO
OSCI
VD
PD
VS
GND
GND
C2VC
B2VCO
C1VC
GND
GND
IFOUT
CPIF
IFAGCIN1
IFAGCIN2
VS
IFIN1
IFIN2
SDA
SWA
SWB
FREF
SWC
CAO
CBO
GND
RFA1
RFB2
CPRF
GND
SAW1
SAW2
VS
SLI
WAGC
RFB1
SCL
PLCK
B1VCO
RFA2
GND
CCO
4
U2731B
4671CDAB06/04
Pin Description
Pin
Symbol
Function
1
SCL
Clock (simple two-wire bus)
2
SDA
Data (simple two-wire bus)
3
SWA
Switching output (open collector)
4
SWB
Switching output (open collector)
5
FREF
Reference frequency output (for U2731B)
6
SWC
Switching output (open collector)
7
CAO
Output of D/A converter A
8
CCO
Output of D/A converter B
9
CBO
Output of D/A converter C
10
GND
Ground
11
GND
Ground
12
RFA1
Input 1 of RF amplifier A (differential)
13
RFA2
Input 2 of RF amplifier A (differential)
14
RFB1
Input 1 of RF amplifier B (differential)
15
RFB2
Input 2 of RF amplifier B (differential)
16
CPRF
Charge-pump output (RF AGC block)
17
GND
Ground
18
SAW1
SAW driver output 1 (differential)
19
SAW2
SAW driver output 2 (differential)
20
VS
Supply voltage RF part
21
SLI
AGC mode selection (charge-pump current high)
22
WAGC
AGC mode selection (charge-pump current off)
23
IFIN2
Input 2 of IF amplifier (differential)
24
IFIN1
Input 1 of IF amplifier (differential)
25
VS
Supply voltage IF part
26
IFAGCIN2
Input 2 of IF AGC block (differential)
27
IFAGCIN1
Input 1 of IF AGC block (differential)
28
CPIF
Charge-pump output (IF AGC block)
29
IFOUT
IF output (single ended)
30
GND
Ground
31
GND
Ground
32
C1VC
Collector 1 of VCO
33
B2VCO
Base 2 of VCO
34
B1VCO
Base 1 of VCO
35
C2VC
Collector 2 of VCO
36
GND
Ground
37
GND
Ground
38
VS
Supply voltage PLL
39
PD
Tri-state charge pump output
40
VD
Active filter output
5
U2731B
4671CDAB06/04
Functional Description
The U2731B represents a monolithically integrated front end IC designed for applica-
tions in DAB receivers. It covers RF and IF signal processing, the PLL section and also
supporting functions such as D/A converters or switching outputs.
Two RF input ports offer the possibility of handling various input signals such as a down-
converted L-band signal or band II and band III RF signals. The high dynamic range of
the RF inputs and the use of a gain-controlled amplifier and a gain-controlled mixer in
the RF section offer the possibility of handling even strong RF input signals. The LO
signal of the first mixer stage is derived from an on-chip VCO. The VCO frequency is
either divided by two or directly fed to the mixer. In this way band II and band III can be
covered easily.
In the IF section, it can be selected if the first IF signal is down-converted to a second,
lower IF or if it is simply amplified to appear at the IF output. If the down-conversion
option is chosen, it can be selected if the LO signal of the IF mixer is directly derived
from the reference signal of the PLL, or if it is generated by doubling its frequency. The
amplifiers in the IF section are gain-controlled in similar fashion to the RF section.
The RF and the IF part also contain AGC functional blocks which generate the AGC
control voltages. The AGC thresholds can be defined by means of three on-chip 4-bit
D/A converters.
The frequency of the VCO is locked to a reference frequency by an on-chip fractional-N
PLL circuit which guarantees a superior phase-noise performance. The reference
frequency is generated by an on-chip crystal oscillator which can also be overdriven by
an external signal. Starting from a minimum value, the reference scaling factor is freely
programmable.
Three switching outputs can be used for various switching tasks on the front end board.
Three 8-bit D/A converters providing an output voltage between 0 and 8.5 V are used to
improve the tuning voltages of the tuned preselectors which are derived from the tuning
voltage of the VCO.
41
PLCK
Lock-indicating output (open collector)
42
OSCI
Input of reference oscillator/buffer
43
OSCO
Output of reference oscillator/buffer
44
ADR
Address selection (simple two-wire bus)
Pin Description (Continued)
Pin
Symbol
Function