Rev. 4770AAUTO11/03
Features
Pulse-width Modulation up to 2 kHz Clock Frequency
Protection Against Short-circuit, Load Dump Overvoltage and Reverse V
S
Duty Cycle 18 to 100% Continuously
Internally Reduced Pulse Slope of Lamp's Voltage
Interference and Damage Protection According to VDE 0839 and ISO/TR 7637/1
Charge-pump Noise Suppression
Ground-wire Breakage Protection
Description
The U6083B is a PWM IC in bipolar technology for the control of an N-channel power
MOSFET used as a high-side switch. The IC is ideal for use in brightness control sys-
tems (dimming) of lamps, for example, in dashboard applications.
PWM Power
Control IC with
Interference
Suppression
U6083B
4
U6083B
4770AAUTO11/03
Functional Description
Pin 1, Supply Voltage, V
S
or V
Batt
Overvoltage Detection
Stage 1
If overvoltages of V
Batt
> 20 V (typically) occur, the external transistor is switched off,
and switched on again at V
Batt
< 18.5 V (hysteresis).
Stage 2
If V
Batt
> 28.5 V (typically), the voltage limitation of the IC is reduced from V
S
= 26 V to
20 V. The gate of the external transistor remains at the potential of the IC ground, thus
producing voltage sharing between FET and lamps in the event of overvoltage pulses
( e . g . , l o a d d u m p ) . T h e s h o r t - c i r c u i t p r o t e c t i o n i s n o t i n o p e r a t i o n . A t
V
Batt
approximately < 23 V, the overvoltage detection stage 2 is switched off. Thus, dur-
ing overvoltage detection stage 2, the lamp voltage V
lamp
is calculated as follows:
V
Lamp
= V
Batt
- V
S
- V
GS
V
S
= supply voltage of the IC at overvoltage detection stage 2
V
GS
= gate - source voltage of the FET
Undervoltage Detection
In the event of voltages of approximately V
Batt
< 5.0 V, the external FET is switched off
and the latch for short-circuit detection is reset.
A hysteresis ensures that the FET is switched on again at approximately V
Batt
5.4 V.
Pin 2, GND
Ground-wire Breakage
To protect the FET in the case of ground-wire breakage, a 1 M
W
resistor between gate
and source is recommended to provide proper switch-off conditions.
Pin 3, Control Input
The pulse width is controlled by means of an external potentiometer (47 k
W
). The char-
acteristic (angle of rotation/duty cycle) is linear. The duty cycle can be varied from 18 to
100%. It is possible to further restrict the duty cycle with the resistors R
1
and R
2
(see
Figure 4 on page 10).
In order to reduce the power dissipation of the FET and to increase the lifetime of the
lamps, the IC automatically reduces the maximum duty cycle at pin 8 if the supply volt-
age exceeds V
2
= 13 V. Pin 3 is protected against short-circuit to V
Batt
and ground
(V
Batt
16.5 V).
Pin 4, Oscillator
The oscillator determines the frequency of the output voltage. This is defined by an
external capacitor, C
2
. It is charged with a constant current, I, until the upper switching
threshold is reached. A second current source is then activated which taps a double cur-
rent, 2
I, from the charging current. The capacitor, C
2
, is thus discharged at the
current, I, until the lower switching threshold is reached. The second source is then
switched off again and the procedure starts once more.
5
U6083B
4770AAUTO11/03
Example for Oscillator
Frequency Calculation
Switching thresholds
V
T100
= High switching threshold (100% duty cycle)
V
T100
=
V
S
a
1
= (V
Batt
- I
S
R
3
)
a
1
V
T<100
= High switching threshold (< 100% duty cycle)
V
T<100
=
V
S
a
2
= (V
Batt
- I
S
R
3
)
a
2
V
TL
= Low switching threshold
V
TL
=
V
S
a
3
= (V
Batt
- I
S
R
3
)
a
3
where
a
1
,
a
2
and
a
3
are fixed values
Calculation Example
The above mentioned threshold voltages are calculated for the following values given in
the data sheet.
V
Batt
= 12 V, I
S
= 4 mA, R
3
= 150
W
,
a
1
= 0.7,
a
2
= 0.67 and
a
3
= 0.28
V
T100
= (12 V - 4 mA
150
W
)
0.7
8 V
V
T<100
=
11.4
V
0.67 = 7.6 V
V
TL
=
11.4
V
0.28 = 3.2 V
Oscillator Frequency
3 cases have to be distinguished
1.
f
1
for duty cycle = 100%, no slope reduction with capacitor C
4
(see Figure 4 on page 10)
, where C
2
= 68 nF, I
OSC
= 45 A
f
1
= ... = 75 Hz
2.
f
2
for duty cycle < 100%, no slope reduction with capacitor C
4
For a duty cycle of less than 100%, the oscillator frequency, f, is as follows:
, where C
2
= 68 nF, I
OSC
= 45 A
f
2
= ... = 69 Hz
3.
f
3
with duty cycle < 100% with slope reduction capacitor C
4
(see "Output Slope
Control" on page 6)
where C
2
= 68 nF, I
OSC
= 45 A, C
4
= 1.8 nF
f
3
= ... = 70 Hz
By selecting different values of C
2
and C
4
, it is possible to have a range of oscillator fre-
quencies from 10 to 2000 Hz as shown in the data sheet.
f
1
I
OSC
2
V
T100
V
TL
(
)
C
2
----------------------------------------------------------
=
f
2
I
OSC
2
V
T<100
V
TL
(
)
C
2
-------------------------------------------------------------
=
f
3
I
osc
2
V
T<100
V
TL
(
)
C
2
2V
Batt
C
4
+
------------------------------------------------------------------------------------------------
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