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Электронный компонент: UA1120

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Rev. B 05-Dec-01
1
Features
High performance ULC family suitable for large-sized CPLDs and FPGAs
Conversion to 1,000,000 gates
Pin counts to over 976 pins
Any pinout matched due to limited number of dedicated pads
Full range of packages: DIP, SOIC, LCC/PLCC, PQFP/TQFP, BGA, PGA/PPGA
Low quiescent current: 0.3 nA/gate
Available in commercial and industrial grades
0.35 m Drawn CMOS, 3 and 4 Metal Layers
Library Optimised for Synthesis, Floor Plan & Automatic Test Pattern
Generation (ATPG)
High Speed Performances:
150 ps Typical Gate Delay @3.3V
Typical 600 MHz Toggle Frequency @3.3V
Typical 360 MHz Toggle Frequency @2.5V
High System Frequency Skew Control:
Clock Tree Synthesis Software
Low Power Consumption:
0.25
W/Gate/ MHz @3.3V
0.18
W
/Gate/ MHz @2.5V
Power on Reset
Standard 2, 4, 6, 8,10, 12 and 18mA I/Os
CMOS/TTL/PCI Interface
ESD (2 kV) and Latch-up Protected I/O
High Noise & EMC Immunity:
I/O with Slew Rate Control
Internal Decoupling
Signal Filtering between Periphery & Core
Description
The UA1 series of ULCs is well suited for conversion of large sized CPLDs and
FPGAs. Devices are implemented in highperformance CMOS technology with
0.35m (drawn) channel lengths, and are capable of supporting flipflop toggle rates
of 200 MHz at 3.3V and 180 MHz at 2.5V, and input to output delays as fast as 150ps
at 3.3V. The architecture of the UA1 series allows for efficient conversion of many PLD
architecture and FPGA device types with higher IO count. A compact RAM cell, along
with the large number of available gates allows the implementation of RAM in FPGA
architectures that support this feature, as well as JTAG boundaryscan and scan
path testing.
Conversion to the UA1 series of ULC can provide a significant reduction in operating
power when compared to the original PLD or FPGA. This is especially true when
compared to many PLD and CPLD architecture devices, which typically consume
100mA or more even when not being clocked. The UA1 series has a very low
standby consumption of 0.3nA/gate typically commercial temperature, which would
yield a standby current of 42A on a 144,000 gates design. Operating consumption is
a strict function of clock frequency, which typically results in a power reduction of 50%
to 90% depending on the device being compared.
The UA1 series provides several options for output buffers, including a variety of drive
levels up to 18mA. Schmitt trigger inputs are also an option. A number of techniques
are used for improved noise immunity and reduced EMC emissions, including: several
independent power supply busses and internal decoupling for isolation; slew rate lim-
ited outputs are also available if required. The UA1 series is designed to allow
conversion of high performance 3.3V devices as well as 2.5V devices.
0.35
m
ULC
Series
UA1
2
UA1
Rev. B 05-Dec-01
Support of mixed supply conversions is also possible, allowing optimal tradeoffs
between speed and power consumption.
Array Organization
Architecture
The basic element of the UA1 family is called a cell. One cell can typically implement
between one to four FPGA gates. Cells are located contiguously through out the core
of the device, with routing resources provided in three to four metal layers above the
cells. Some cell blockage does occur due to routing, and utilization will be significantly
greater with three metal routing than two. The sizes listed in the Product Outline are
estimated usable amounts using three metal layers. I/O cells are provided at each pad,
and may be configured as inputs, outputs, I/Os, V
DD
or V
SS
as required to match any
FPGA or PLD pinout.
In order to improve noise immunity within the device, separate V
DD
and V
SS
busses are
provided for the internal cells and the I/O cells.
Part Number
Max Pad Count
Full Programmable
Usable Pads
Routable Gates
Equivalent FPGA
Gates
UA1044
44
36
3729
14916
UA1068
68
60
11760
47044
UA1084
84
76
19734
78936
UA1100
100
92
29760
119040
UA1120
120
112
42211
168844
UA1132
132
124
52222
208888
UA1144
144
136
63298
253192
UA1160
160
152
79866
319464
UA1184
184
176
107538
430152
UA1208
208
200
13124
525296
UA1228
228
220
160020
640080
UA1256
256
240
204552
818208
UA1304
304
288
292288
1169152
UA1352
352
336
369164
1476656
UA1388
388
372
451269
1805076
UA1432
432
416
565431
2261724
UA1484
484
468
658314
2633256
UA1540
540
516
826353
3305412
UA1600
600
576
1025460
4101840
UA1700
700
676
1407636
5630544
UA1800
800
776
1691906
6767624
UA1900
900
876
2151765
8607060
UA1976
976
952
2360609
9226436
3
UA1
Rev. B 05-Dec-01
I/O buffer interfacing
I/O Flexibility
All I/O buffers may be configured as input, output, bi-directional, oscillator or supply. A
level translator could be located close to each buffer.
I/O Options
Inputs
Each input can be programmed as TTL, CMOS, or Schmitt Trigger, with or without a pull
up or pull down resistor.
Fast Output Buffer
Fast output buffers are able to source or sink 2 to 18mA at 3.3V according to the chosen
option. 36mA achievable, using 2 pads.
Slew Rate Controlled Output Buffer
In this mode, the p and noutput transistors commands are delayed, so that they are
never set "ON" simultaneously, resulting in a low switching current and low noise.
These buffers are dedicated to very high load drive.
2.5V Compatibility
The UA1 series of ULC's is fully capable of supporting highperformance operation at
2.5V or 3.3V. The performance specifications of any given ULC design however, must
be explicitly specified as 2.5V, 3.3V or both.
Power Supply and Noise
Protection
The speed and density of the UA1 technology cause large switching current spikes, for
example when:
16 high current output buffers switch simultaneously, or
10% of the 700 000 gates are switching within a window of 1ns.
Sharp edges and high currents cause some parasitic elements in the packaging to
become significant. In this frequency range, the package inductance and series resis-
tance should be taken into account. It is known that an inductor slows down the setting
time of the current and causes voltage drops on the power supply lines. These drops
can affect the behavior of the circuit itself or disturb the external application (ground
bounce).
In order to improve the noise immunity of the UA1 core matrix, several mechanisms
have been implemented inside the UA1 arrays. Two types of protection have been
added: one to limit the I/O buffer switching noise and the other to protect the I/O buffers
against the switching noise coming from the matrix.
I/O buffers switching protection
Three features are implemented to limit the noise generated by the switching current:
The power supplies of the input and output buffers are separated.
The rise and fall times of the output buffers can be controlled by an internal
regulator.
A design rule concerning the number of buffers connected on the same power
supply line has been imposed.
Matrix switching current
protection
This noise disturbance is caused by a large number of gates switching simultaneously.
To allow this without impacting the functionality of the circuit, three new features have
been added:
Decoupling capacitors are integrated directly on the silicon to reduce the power
supply drop.
4
UA1
Rev. B 05-Dec-01
A power supply network has been implemented in the matrix. This solution reduces
the number of parasitic elements such as inductance and resistance and constitutes
an artificial V
DD
and Ground plane. One mesh of the network supplies approximately
150 cells.
A low pass filter has been added between the matrix and the input to the output
buffer. This limits the transmission of the noise coming from the ground or the V
DD
supply of the matrix to the external world via the output buffers.
Absolute Maximum
Ratings
Max Supply Core Voltage (V
DD
) ..............................................................3.6V
Max Supply Periphery Voltage (V
DD5
) .....................................................5.5V
InputVoltage (V
IN
)V
DD
.............................................................................+ 0.5V
5V Tolerant/Compliant V
DD5
...................................................................+ 0.5V
Storage Temperature ..............................................................................-65
to 150
C
Operating Ambient Temperature .............................................................-55
to 125
C
Recommended
Operating Range
V
DD
....................................................................................................2.5V 5% or 3.3V
Operating Temperature
Commercial .............................................................................................0
to 70
C
Industrial ..................................................................................................-40
to 85
C
5
UA1
Rev. B 05-Dec-01
DC Characteristics
2.5V
Specified at V
DD
= +2.5V
Symbol
Parameter
Buffer
Min
Typ
Max
Unit
Conditions
TA
Operating Temperature
All
-40
+85
C
VDD
SupplyVoltage
All
2.3
2.5
2.7
V
I
IH
High level input current
CMOS
10
A
V
IN =
V
DD
,V
DD =
V
DD
(max)
PCI
10
I
IL
Low Level input current
CMOS
-10
A
V
IN
= V
SS
,V
DD =
V
DD
(max)
PCI
I
OZ
High-Impedance State
Output Current
All
-10
10
A
V
IN
= V
DD
or V
SS
,
V
DD
= V
DD
(max), No Pull-up
I
OS
Output short-circuit current
PO11
9
mA
V
OUT
= V
DD
,V
DD
= V
DD
(max)
V
OUT
= V
SS
,V
DD =
V
DD
(max)
PO11
6
V
IH
High-level InputVoltage
CMOS
0.7V
DD
V
PCI
0.475V
DD
CMOS Schmitt
0.7V
DD
1.5
V
IL
Low-Level InputVoltage
CMOS
0.3V
DD
V
PCI
0.325V
DD
CMOS Schmitt
1.0
0.3V
DD
V
hys
Hysteresis
CMOS Schmitt
0.5
V
V
OH
High-Level output voltage
PO11
0.7V
DD
V
I
OH
= 1.4mA,V
DD
= V
DD
(min)
I
OH
= -500A
PCI
0.9V
DD
V
OL
Low-Level output voltage
PO11
0.4
V
I
OL
= 1.4mA,V
DD
= V
DD
(min)
I
OL
= 1.5mA
PCI
0.1V
DD