2-93
AS4LC1M16
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
DS000020
AS4LC1M16 883C
1 MEG x 16 DRAM
PRELIMINARY
AUSTIN SEMICONDUCTOR, INC.
1 MEG x 16 DRAM
3.3V, EDO PAGE MODE,
OPTIONAL EXTENDED REFRESH
DRAM
PIN ASSIGNMENT (Top View)
GENERAL DESCRIPTION
The AS4LC1M16 is a randomly accessed solid-state
memory containing 16,777,216 bits organized in a x16 con-
figuration. The AS4LC1M16 has both BYTE WRITE and
WORD WRITE access cycles via two
?
C
?
A
/
S pins (
?
C
?
A
?
S
/
L and
?
C
?
A
?
S
?
H). These function in a similar manner to a single
?
C
?
AS
of other DRAMs in that either
?
C
?
A
?
S
/
L or
?C?A?S?H will generate
AVAILABLE AS MILITARY
SPECIFICATIONS
MIL-STD 883
SMD Planned
FEATURES
JEDEC- and industry-standard x16 timing, functions,
pinouts and packages
High-performance CMOS silicon-gate process
Single +3.3V
0.3V power supply
All device pins are TTL-compatible
Refresh modes:
?
R
?
A
/
S ONLY,
?
C
?
A
/
S-BEFORE-
?
R
?
A
/
S (CBR),
HIDDEN
BYTE WRITE access cycles
1,024-cycle refresh (10 row-, 10 column-addresses)
Low power, 0.3mW standby; 180mW active, typical
Extended Data-Out (EDO) PAGE access cycle
5V-tolerant I/Os (5.5V maximum V
IH
level)
OPTIONS
MARKING
Timing
60ns access (Contact Factory)
-6
70ns access
-7
80ns access
-8
Refresh Rate
Standard 16ms period
None
Packages
Ceramic SOJ
ECJ
No. 506
Ceramic Gull Wing
ECG No. 604
Ceramic LCC
EC
No. 213
44/50-Pin SOJ/LCC/Gull Wing
450mil
Vcc
DQ1
DQ2
DQ3
DQ4
Vcc
DQ5
DQ6
DQ7
DQ8
NC
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
Vcc
1
2
3
4
5
6
7
8
9
10
11
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
36
35
34
33
32
31
30
29
28
27
26
Vss
DQ16
DQ15
DQ14
DQ13
Vss
DQ12
DQ11
DQ10
DQ9
NC
NC
CASL
CASH
OE
A9
A8
A7
A6
A5
A4
Vss
KEY TIMING PARAMETERS
SPEED
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
CAS
-6
105ns
60ns
25ns
30ns
15ns
12ns
-7
125ns
70ns
30ns
35ns
20ns
12ns
-8
150ns
80ns
40ns
40ns
20ns
20ns
an internal
?
C
?
A
/
S.
The AS4LC1M16
?
C
?
A
/
S function and timing are deter-
mined by the first
?
C
?
A
/
S (
?
C
?
A
?
S
/
L or
?
C
?
A
?
S
?
H) to transition LOW
and the last
?
C
?
A
/
S to transition back HIGH. Use of only one
of the two results in a BYTE WRITE cycle.
?
C
?
A
?
S
/
L transitioning
LOW selects an access cycle for the lower byte (DQ1-DQ8)
and
?
C
?
A
?
S
?
H transitioning LOW selects an access cycle for the
upper byte (DQ9-DQ16).
Each bit is uniquely addressed through the 20 address bits
during READ or WRITE cycles. These are entered 10 bits
(A0 -A9) at a time.
?
R
?
A
/
S is used to latch the first 10 bits and
?
C
?
A
/
S the latter 10 bits. The
?
C
?
A
/
S function also determines
whether the cycle will be a refresh cycle (
?
R
?
A
/
S ONLY) or an
active cycle (READ, WRITE or READ WRITE) once
?
R
?
A
/
S
goes LOW.
2-94
AS4LC1M16
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
DS000020
AS4LC1M16 883C
1 MEG x 16 DRAM
PRELIMINARY
AUSTIN SEMICONDUCTOR, INC.
PAGE ACCESS
PAGE operations allow faster data operations (READ,
WRITE or READ-MODIFY-WRITE) within a row-address-
defined page boundary. The PAGE cycle is always initiated
with a row-address strobed-in by
?
R
?
A
/
S followed by a col-
umn-address strobed-in by
?C?A/S. ?C?A/S may be toggled-in
by holding
?
R
?
A
/
S LOW and strobing-in different column-
addresses, thus executing faster memory cycles. Returning
?
R
?
A
/
S HIGH terminates the PAGE MODE of operation.
EDO PAGE MODE
The AS4LC1M16 provides EDO PAGE MODE which is
an accelerated FAST PAGE MODE cycle. The primary
advantage of EDO is the availability of data-out even after
?
C
?
A
/
S returns HIGH. EDO provides for
?
C
?
A
/
S precharge time
(
t
CP) to occur without the output data going invalid. This
elimination of
?
C
?
A
/
S output control provides for pipeline
READs.
FAST-PAGE-MODE DRAMs have traditionally turned
the output buffers off (High-Z) with the rising edge of
?
C
?
A
/
S. EDO-PAGE-MODE DRAMs operate similar to
FAST-PAGE-MODE DRAMs, except data will remain valid
or become valid after
?
C
?
A
/
S goes HIGH during READs,
provided
?
R
?
A
/
S and
?
O
/
E are held LOW. If
?
O
/
E is pulsed while
?
R
?
A
/
S and
?
C
?
A
/
S are LOW, data will toggle from valid data to
High-Z and back to the same valid data. If
?
O
/
E is toggled or
pulsed after
?
C
?
A
/
S goes HIGH while
?
R
?
A
/
S remains LOW, data
will transition to and remain High-Z (refer to Figure 1).
The
?
C
?
A
/
S
/
L and
?
C
?
A
/
S
?
H inputs internally generate a
?
C
?
A
/
S
signal functioning in a similar manner to the single
?
C
?
A
/
S input of other DRAMs. The key difference is each
?
C
?
A
/
S input (
?
C
?
A
/
S
/
L and
?
C
?
A
/
S
?
H ) controls its corresponding
8 DQ inputs during WRITE accesses.
?
C
?
A
/
S
/
L controls DQ1
through DQ8 and
?
C
?
A
/
S
?
H controls DQ9 through DQ16. The
two
?
C
?
A
/
S controls give the MT4LC1M16E5(S) both BYTE
READ and BYTE WRITE cycle capabilities.
A logic HIGH on
?
W
/
E dictates READ mode while a logic
LOW on
?
W
/
E dictates WRITE mode. During a WRITE cycle,
data-in (D) is latched by the falling edge of WE or
?
C
?
A
/
S
(
?
C
?
A
/
S
/
L or
?
C
?
A
/
S
/
H), whichever occurs last. An EARLY WRITE
occurs when WE is taken LOW prior to either
?
C
?
A
/
S falling.
A LATE WRITE or READ-MODIFY-WRITE occurs when
WE falls after
?
C
?
A
/
S (
?
C
?
A
/
S
/
L or
?
C
?
A
/
S
/
H) was taken LOW.
During EARLY WRITE cycles, the data-outputs (Q) will
remain High-Z regardless of the state of
?
O
/
E. During LATE
WRITE or READ-MODIFY-WRITE cycles,
?
O
/
E must be
taken HIGH to disable the data-outputs prior to applying
input data. If a LATE WRITE or READ-MODIFY-WRITE is
attempted while keeping
?
O
/
E LOW, no write will occur, and
the data-outputs will drive read data from the accessed
location.
The 16 data inputs and 16 data outputs are routed through
16 pins using common I/O. Pin direction is controlled by
?
O
/
E and
?
W
/
E.
GENERAL DESCRIPTION (continued)
Figure 1
OUTPUT ENABLE AND DISABLE
,,
,,,
V
V
IH
IL
CASL/CASH
V
V
IH
IL
RAS
V
V
IH
IL
ADDR
,,
ROW
,,
,
COLUMN (A)
,,
,,,
,,
COLUMN (B)
,
,,,,
,,
DON'T CARE
UNDEFINED
,
,
,,
,,
V
V
IH
IL
OE
V
V
IOH
IOL
OPEN
DQ
tOD
VALID DATA (B)
VALID DATA (A)
,
COLUMN (C)
,,,
,,,
VALID DATA (A)
tOE
,,
VALID DATA (C)
,
COLUMN (D)
,,,
,,
,
VALID DATA (D)
tOD
tOEHC
tOD
tOEP
tOES
The DQs go back to
Low-Z if tOES is met.
The DQs remain High-Z
until the next CAS cycle
if tOEHC is met.
The DQs remain High-Z
until the next CAS cycle
if tOEP is met.
2-95
AS4LC1M16
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
DS000020
AS4LC1M16 883C
1 MEG x 16 DRAM
PRELIMINARY
AUSTIN SEMICONDUCTOR, INC.
EDO PAGE MODE
(continued)
?
W
/
E can also perform the function of disabling the output
drivers under certain conditions, as shown in Figure 2.
During an application, if the DQ outputs are wire OR'd,
?
O
/
E must be used to disable idle banks of DRAMs. Alterna-
tively, pulsing
?
W
/
E to the idle banks during
?
C
?
A
/
S HIGH time
will also High-Z the outputs. Independent of
?
O
/
E control,
the outputs will disable after
t
OFF, which is referenced
from the rising edge of
?
R
?
A
/
S or
?
C
?
A
/
S, whichever occurs last.
,,
,,
V
V
IH
IL
CASL/CASH
V
V
IH
IL
RAS
V
V
IH
IL
ADDR
,,
ROW
,,
,
COLUMN (A)
,,
,,,
,
DON'T CARE
UNDEFINED
,
,,
,,
,,
V
V
IH
IL
WE
V
V
IOH
IOL
OPEN
DQ
,
,
,
,,,
,
,,
,,
,,
,,
tWPZ
The DQs go to High-Z if WE falls, and if
t
WPZ is met,
will remain High-Z until CAS goes LOW with
WE HIGH (i.e., until a READ cycle is initiated).
V
V
IH
IL
OE
,
,
VALID DATA (B)
t
WHZ
WE may be used to disable the DQs to prepare
for input data in an EARLY WRITE cycle. The DQs
will remain High-Z until CAS goes LOW with
WE HIGH (i.e., until a READ cycle is initiated).
t
WHZ
COLUMN (D)
,,
,,,
,,,
VALID DATA (A)
COLUMN (B)
COLUMN (C)
INPUT DATA (C)
Figure 2
??
??
?
W
//
//
/
E CONTROL OF DQs
2-96
AS4LC1M16
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
DS000020
AS4LC1M16 883C
1 MEG x 16 DRAM
PRELIMINARY
AUSTIN SEMICONDUCTOR, INC.
BYTE ACCESS CYCLE
The BYTE WRITEs and BYTE READs are determined by
the use of
?
C
?
A
/
S
/
L and
?
C
?
A
/
S
?
H. Enabling
?
C
?
A
/
S
/
L will select a
lower BYTE access (DQ1-DQ8). Enabling
?
C
?
A
/
S
?
H will select
an upper BYTE access (DQ9-DQ16). Enabling both
?
C
?
A
/
S
/
L
and
?
C
?
A
/
S
?
H selects a WORD WRITE cycle.
The AS4LC1M16 may be viewed as two 1 Meg x 8
DRAMs that have common input controls, with the excep-
tion of the
/
?
C
?
A
/
S inputs. Figure 3 illustrates the BYTE WRITE
and WORD WRITE cycles.
Additionally, both bytes must always be of the same
mode of operation if both bytes are active. A
?
C
?
A
/
S precharge
must be satisfied prior to changing modes of operation
between the upper and lower bytes. For example, an EARLY
STORED
DATA
1
1
0
1
1
1
1
1
RAS
CASL
WE
X = NOT EFFECTIVE (DON'T CARE)
ADDRESS 1
ADDRESS 0
0
1
0
1
0
0
0
0
WORD WRITE
LOWER BYTE WRITE
CASH
INPUT
DATA
0
0
1
0
0
0
0
0
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
X
INPUT
DATA
1
1
0
1
1
1
1
1
INPUT
DATA
STORED
DATA
1
1
0
1
1
1
1
1
INPUT
DATA
STORED
DATA
0
0
1
0
0
0
0
0
1
0
1
0
1
1
1
1
STORED
DATA
0
0
1
0
0
0
0
0
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
X
1
0
1
0
1
1
1
1
UPPER BYTE
(DQ9-DQ16)
OF WORD
LOWER BYTE
(DQ1-DQ8)
OF WORD
Figure 3
WORD AND BYTE WRITE EXAMPLE
WRITE on one byte and a LATE WRITE on the other byte is
not allowed during the same cycle. However, an EARLY
WRITE on one byte and, after a
?
C
?
A
/
S precharge has been
satisfied, a LATE WRITE on the other byte is permissable.
REFRESH
Preserve correct memory cell data by maintaining power
and executing a
?
R
?
A
/
S cycle (READ, WRITE) or
?
R
?
A
/
S refresh
cycle (
?
R
?
A
/
S ONLY, CBR, or HIDDEN) so that all 1,024
combinations of
?
R
?
A
/
S addresses are executed at least every
16ms, regardless of sequence. The CBR REFRESH cycle will
invoke the refresh counter for automatic
?
R
?
A
/
S addressing.
2-97
AS4LC1M16
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
DS000020
AS4LC1M16 883C
1 MEG x 16 DRAM
PRELIMINARY
AUSTIN SEMICONDUCTOR, INC.
CASL
CAS
RAS
10
10
NO. 2 CLOCK
GENERATOR
REFRESH
CONTROLLER
NO. 1 CLOCK
GENERATOR
1024 x 1024 x 16
MEMORY
ARRAY
Vcc
Vss
10
OE
DQ1
DQ16
REFRESH
COUNTER
CASH
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
1024
1024 x 16
16
10
10
SENSE AMPLIFIERS
I/O GATING
1024
DATA-OUT
BUFFER
WE
16
ROW-
ADDRESS
BUFFERS (10)
ROW
DECODER
COLUMN-
ADDRESS
BUFFER
DATA-IN BUFFER
COLUMN
DECODER
16
FUNCTIONAL BLOCK DIAGRAM
PDF 
ZIP