SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
AS4SD4M16
Austin Semiconductor, Inc.
AS4SD4M16
Rev. 2.0 6/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
FEATURES
Extended Testing Over -55C to +125 C and
Industrial Temp -40C to 85 C
WRITE Recovery (
t
WR
/
t
DPL
)
t
WR
= 2 CLK
Fully synchronous; all signals registered on positive
edge of system clock
Internal pipelined operation; column address can be
changed every clock cycle
Internal banks for hiding row access/precharge
Programmable burst lengths: 1, 2, 4, 8 or full page
Auto Precharge and Auto Refresh Modes
Self Refresh Mode (Industrial, -40C to 85 C only)
4,096-cycle refresh
LVTTL-compatible inputs and outputs
Single +3.3V 0.3V power supply
Longer lead TSOP for improved reliability
(OCPL*)
Short Flow / Long Flow Test Screening Options
OPTIONS
MARKING
Configurations
4 Meg x 16 (1 Meg x 16 x 4 banks)
4M16
Plastic Package - OCPL*
54-pin TSOP (400 mil)
DG
No. 901
Timing (Cycle Time)
8ns; t
AC
= 6.5ns @ CL = 3 ( t
RP
- 24ns)
-8
10ns; t
AC
= 9ns @ CL = 2
-10
Operating Temperature Ranges
-Military (-55C to +125 C)
XT
-Industrial Temp (-40C to 85 C)
IT
KEY TIMING PARAMETERS
SPEED
CLOCK
SETUP
HOLD
GRADE
FREQUENCY
CL = 2**
CL = 3**
TIME
TIME
-8
125 MHz
6.5ns
2ns
1ns
-10
100 MHz
7ns
3ns
1ns
-8
83 MHz
9ns
2ns
1ns
-10
66 MHz
9ns
3ns
1ns
ACCESS TIME
*Off-center parting line
**CL = CAS (READ) latency
PIN ASSIGNMENT
(Top View)
54-Pin TSOP
Note: "\" indicates an active low.
Configuration
1 Meg x 16 x 4 banks
Refresh Count
4K
Row Addressing
4K (A0-A11)
Bank Addressing
4 (BA0, BA1)
Column Addressing
256 (A0-A7)
4 Meg x 16
4 Meg x 16 SDRAM
Synchronous DRAM Memory
For more products and information
please visit our web site at
www.austinsemiconductor.com
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
AS4SD4M16
Austin Semiconductor, Inc.
AS4SD4M16
Rev. 2.0 6/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
GENERAL DESCRIPTION
The 64Mb SDRAM is a high-speed CMOS, dynamic ran-
dom-access memory containing 67,108,864 bits. It is internally
configured as a quad-bank DRAM with a synchronous inter-
face (all signals are registered on the positive edge of the clock
signal, CLK). Each of the x16's 6,777,216-bit banks is organized
as 4,096 rows by 256 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a pro-
grammed number of locations in a programmed sequence. Ac-
cesses begin with the registration of an ACTIVE command,
which is then followed by a READ or WRITE command. The
address bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed (BA0, BA1
select the bank; A0-A11 select the row). The address bits
registered coincident with the READ or WRITE command are
used to select the starting column location for the burst access.
The SDRAM provides for programmable READ or WRITE
burst lengths of 1, 2, 4 or 8 locations, or the full page, with a
burst terminate option. An AUTO PRECHARGE function may
be enabled to provide a self-timed row precharge that is initi-
ated at the end of the burst sequence.
The 64Mb SDRAM uses an internal pipelined architecture
to achieve high-speed operation. This architecture is compat-
ible with the 2n rule of prefetch architectures, but it also allows
the column address to be changed on every clock cycle to
achieve a high-speed, fully random access. Precharging one
bank while accessing one of the other three banks will hide the
precharge cycles and provide seamless, high-speed, random-
access operation.
The 64Mb SDRAM is designed to operate in 3.3V, low-
power memory systems. An auto refresh mode is provided,
along with a power-saving, power-down mode. All inputs and
outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM operating
performance, including the ability to synchronously burst data
at a high data rate with automatic column-address generation,
the ability to interleave between internal banks in order to hide
precharge time and the capability to randomly change column
addresses on each clock cycle during a burst access.
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
AS4SD4M16
Austin Semiconductor, Inc.
AS4SD4M16
Rev. 2.0 6/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
TABLE OF CONTENTS
Functional Block Diagram - 4 Meg x 16 ........................................ 4
Pin Descriptions ............................................................................. 5
Functional Description ................................................................. 6
Initialization ............................................................................. 6
Register Definition ................................................................. 6
Mode Register ................................................................ 6
Burst Length ................................................................... 6
Burst Type ....................................................................... 7
CAS Latency ................................................................... 8
Operating Mode ............................................................. 8
Write Burst Mode .......................................................... 8
Commands ....................................................................................... 9
Truth Table 1 (Commands and DQM Operation) ...
......................
9
Command Inhibit .................................................................... 10
No Operation (NOP) .................................................................10
Load Mode Register ............................................................. 10
Active ....................................................................................... 10
Read .......................................................................................... 10
Write ......................................................................................... 10
Precharge ................................................................................. 10
Auto Precharge ...................................................................... 10
Burst Terminate ...................................................................... 11
Auto Refresh .......................................................................... 11
Self Refresh ............................................................................. 11
Operation ..................................................................................... 12
Bank/Row Activation ............................................................ 12
Reads ........................................................................................ 13
Writes ....................................................................................... 19
Precharge................................................................................... 21
Power-Down...............................................................................21
Clock Suspend......................................................................... 22
Burst Read/Single Write ...........................................................22
Concurrent Auto Precharge ................................................. 23
Truth Table 2 (CKE) ......................................................................2
5
Truth Table 3 (Current State, Same Bank) .........................
........
26
Truth Table 4 (Current State, Different Bank) ...........................
28
Absolute Maximum Ratings ........................................................ 30
DC Electrical Characteristics and Operating Conditions......... 30
I
CC
Specifications and Conditions .............................................. 30
Capacitance ..................................................................................... 31
AC Electrical Characteristics (Timing Table) ............................31
Timing Waveforms
Initialize and Load Mode Register ..................................... 34
Power-Down Mode ................................................................ 35
Clock Suspend Mode ........................................................... 36
Auto Refresh Mode .............................................................. 37
Self Refresh Mode ................................................................. 38
Reads
Read - Without Auto Precharge ................................. 39
Read - With Auto Precharge ....................................... 40
Alternating Bank Read Accesses .............................. 41
Read - Full-Page Burst ......................................................... 42
Read - DQM Operation ................................................ 43
Writes
Write - Without Auto Precharge ................................ 44
Write - With Auto Precharge ...................................... 45
Alternating Bank Write Accesses .............................. 46
Write - Full-Page Burst ................................................. 47
Write - DQM Operation ............................................... 48
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
AS4SD4M16
Austin Semiconductor, Inc.
AS4SD4M16
Rev. 2.0 6/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
CKE
CLK
CS\
WE\
CAS\
RAS\
DQML, DQMH
DQ0-DQ15
A0,
A10,
BA
1
2
12
12
ROW
ADDRESS
MUX
ADDRESS
REGISTER
REFRESH
COUNTER
12
CONTROL
LOGIC
COMMAND
DECODE
MODE REGISTER
14
DATA
OUTPUT
REGISTER
DATA
INPUT
REGISTER
16
16
16
BANK0
ROW-
ADDRESS
LATCH &
DECODER
12
BANK 0
MEMORY
ARRAY
(4,096 X 256 X 16)
SENSE AMPLIFIERS
4096
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
4096
COLUMN
DECODER
256
(X16)
BANK
CONTROL
LOGIC
COLUMN-
ADDRESS
COUNTER/
LATCH
8
2
2
8
BANK1
BANK2 BANK3
2
2
FUNCTIONAL BLOCK DIAGRAM
4 Meg x 16 SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
AS4SD4M16
Austin Semiconductor, Inc.
AS4SD4M16
Rev. 2.0 6/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
PIN DESCRIPTION
TSOP
PIN NUMBERS
38
CLK
Input
Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal burst
counter and controls the output registers.
37
CKE
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides PRECHARGE POWER-DOWN and SELF
REFRESH operations (all banks idle), ACTIVE POWER-DOWN (row ACTIVE
in either bank) or CLOCK SUSPEND operation (burst/access in progress).
CKE is synchronous except after the device enters power-down and self
refresh modes, where CKE becomes asynchronous until after exiting the
same mode. The input buffers, including CLK, are disabled during power-down
and self refresh modes, providing low standby power. CKE may be tied
HIGH.
19
CS\
Input
Chip Select: CS\ enables (registered LOW) and disables (registered HIGH)
the command decoder. All commands are masked when CS\ is registered
HIGH. CS\ provides for external bank selection on systems with multiple
banks. CS\ is considered part of the command code.
16, 17
WE\, CAS\
Input
Command Inputs: RAS\, CAS\, and WE\ (along with CS\) define the
18
RAS\
command being entered.
15, 39
DQML,
Input
Input/Output Mask: DQM is an input mask signal for write accesses and an
DQMH
output enable signal for read accesses. Input data is masked when DQM is
sampled HIGH during a WRITE cycle. The output buffers are placed in a
High-Z state (two-clock latency) when DQM is sampled HIGH during a READ
cycle. DQML corresponds to DQ0-DQ7; DQMH corresponds to DQ8-DQ15.
DQML and DQMH are considered same state when referenced as DQM.
20, 21
BA0, BA1
Input
Bank Address Inputs: BA0 and BA1 define to which bank the ACTIVE, READ,
WRITE or PRECHARGE command is being applied.
23-26, 29-34,
A0-A11
Input
Address Inputs: A0-A11 are sampled during the ACTIVE command (row
22, 35
address A0-A11) and READ/WRITE command (column address A0-A7, with
A10 defining AUTO PRECHARGE) to select one location out of the memory
array in the respective bank. A10 is sampled during a PRECHARGE
command to determine if all banks are to be precharged (A10 HIGH) or bank
selected by BA0,BA1 (LOW). The address inputs also provide the op-code
during a LOAD MODE REGISTER command.
2, 4, 5, 7, 8
DQ0- DQ15
Input/
Data I/O: Data bus.
10, 11, 13, 42
Output
44, 45, 47, 48
50, 51, 53
36, 40
NC
--
No Connect: These pins should be left unconnected.
3, 9, 43, 49
VDDQ
Supply
DQ Power: Provide isolated power to DQs for improved noise immunity.
6, 12, 46, 52
VSSQ
Supply
DQ Ground: Provide isolated ground to DQs for improved noise immunity.
1, 14, 27
VDD
Supply
Power Supply: +3.3V 0.3V.
28, 41, 54
VSS
Supply
Ground.
SYMBOL
TYPE
DESCRIPTION
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