SRAM
AS5C2568
Austin Semiconductor, Inc.
AS5C2568
Rev. 2.0 12/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
FEATURES
Access Times: 12, 15, & 20ns
Fast output enable (tDOE) for cache applications
Low active power: 400 mW (TYP)
Low power standby
Fully static operation, no clock or refresh required
High-performance, low-power CMOS double-metal process
Single +5V (+10%) Power Supply
Easy memory expansion with CE\
All inputs and outputs are TTL compatible
OPTIONS
MARKING
Timing
12ns access*
-12
15ns access
-15
20ns access
-20
Package(s)**
Plastic SOJ
DJ
No. 906
Operating Temperature Ranges
Military -55
o
C to +125
o
C
XT
Industrial -40
o
C to +85
o
C
IT
* -12 available in IT only.
** For ceramic version of this product, see the MT5C2568
data sheet.
PIN ASSIGNMENT
(Top View)
28-PIN PSOJ (DJ)
GENERAL DESCRIPTION
The Austin Semiconductor SRAM family employs
high-speed, low power CMOS designs using a four-transistor
memory cell. These SRAMs are fabricated using double-layer
metal, double-layer polysilicon technology.
For flexibility in high-speed memory applications, Aus-
tin Semiconductor offers chip enable (CE\) and output enable
(OE\) capability. These enhancements can place the outputs in
High-Z for additional flexibility in system design.
Writing to these devices is accomplished when write
enable (WE\) and CE\ inputs are both LOW. Reading is accom-
plished when WE\ remains HIGH and CE\ and OE\ go LOW.
The device offers a reduced power standby mode when dis-
abled. This allows system designs to achieve low standby
power requirements.
All devices operate from a single +5V power supply
and all inputs and outputs are fully TTL compatible.
32K x 8 SRAM
SRAM MEMORY ARRAY
For more products and information
please visit our web site at
www.austinsemiconductor.com
A14 1
28 V
CC
A12 2
27 WE\
A7 3
26 A13
A6 4
25 A8
A5 5
24 A9
A4 6
23 A11
A3 7
22 OE\
A2 8
21 A10
A1 9
20 CE\
A0 10 19 I/O7
I/O0 11 18 I/O6
I/O1 12 17 I/O5
I/O2 13 16 I/O4
GND 14 15
I/O3
SRAM
AS5C2568
Austin Semiconductor, Inc.
AS5C2568
Rev. 2.0 12/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
FUNCTIONAL BLOCK DIAGRAM
TRUTH TABLE
A0
Vcc
GND
A14
I/O0
I/O7
CE\
OE\
WE\
9A128-1
DECODER
I/O
DATA
CIRCUIT
CONTROL
CIRCUIT
256 x 1024
MEMORY ARRAY
COLUMN I/O
MODE
OE\
CE\
WE\
DQ
POWER
STANDBY
X
H
X
HIGH-Z
STANDBY
READ
L
L
H
Q
ACTIVE
READ
H
L
H
HIGH-Z
ACTIVE
WRITE
X
L
L
D
ACTIVE
SRAM
AS5C2568
Austin Semiconductor, Inc.
AS5C2568
Rev. 2.0 12/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Input or DQ Relative
to Vss..................................................................-0.5V to Vcc +0.5V
Voltage on Vcc Supply Relative to Vss.......................-1V to +7V
Storage Temperature..............................................-65
o
C to +150
o
C
Power Dissipation.......................................................................1W
Short Circuit Output Current............................................20mA
Lead Temperature (soldering 10 seconds)........................+260
o
C
Max. Junction Temperature.................................................+175
o
C
*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect reliability.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55
o
C < T
C
< 125
o
C or -40
o
C to +85
o
C; V
CC
= 5.0V +10%)
CAPACITANCE
DESCRIPTION CONDITIONS
SYMBOL
MIN
MAX
UNITS
NOTES
Input High (Logic 1) Voltage
V
IH
2.2 Vcc+0.5 V
1
Input Low (Logic 0) Voltage
V
IL
-0.5 0.8 V 1,
2
Input Leakage Current
0V
V
IN
Vcc
IL
I
-5 5
A
Output Leakage Current
Output(s) disabled
0V < V
OUT
< Vcc
IL
O
-5 5
A
Output High Voltage
I
OH
= -4.0mA
V
OH
2.4
V
1
Output Low Voltage
I
OL
= 8.0mA
V
OL
0.4
V 1
PARAMETER
CONDITIONS
SYM
MAX
UNITS
NOTES
Input Capacitance
C
IN
8
pF
4
Input/Output Capacitance
C
IO
10
pF
4
T
A
= 25
o
C, f = 1MHz
Vcc = 5V
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SRAM
AS5C2568
Austin Semiconductor, Inc.
AS5C2568
Rev. 2.0 12/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 5) (-55
o
C < T
C
< 125
o
C or -40
o
C to +85
o
C; V
CC
= 5.0V +10%)
MIN
MAX
MIN
MAX
MIN
MAX
READ CYCLE
READ cycle time
t
RC
12
15
20
ns
Address access time
t
AA
12
15
20
ns
Chip enable access time
t
ACE
12
15
20
ns
Output hold from address change
t
OH
2
2
2
ns
Chip enable to output in Low-Z
t
LZCE
2
2
2
ns
7
Chip disable to output in High-Z
t
HZCE
7
8
9
ns
6, 7
Chip enable to power-up time
t
PU
0
0
0
ns
4
Chip disable to power-down time
t
PD
12
15
20
ns
4
Output enable to access time
t
AOE
6
7
8
ns
Output enable to output in Low-Z
t
LZOE
0
0
0
ns
Output disable to output in High-Z
t
HZOE
6
7
8
ns
6
WRITE CYCLE
WRITE cycle time
t
WC
12
15
20
ns
Chip enable to end of write
t
CW
9
10
12
ns
Address valid to end of write
t
AW
9
10
12
ns
Address setup time
t
AS
0
0
0
ns
Address hold from end of write
t
AH
0
0
0
ns
WRITE pulse width
t
WP
10
12
15
ns
Data setup time
t
DS
7
8
10
ns
Data hold time
t
DH
0
0
0
ns
Write disable to output in Low-Z
t
LZWE
2
2
2
ns
7
Write enable to output in High-Z
t
HZWE
0
7
0
7
0
9
ns
6, 7
DESCRIPTION
SYM
UNITS NOTES
-12
-15
-20
SRAM
AS5C2568
Austin Semiconductor, Inc.
AS5C2568
Rev. 2.0 12/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
NOTES
1.
All voltages referenced to V
SS
(GND).
2.
-3V for pulse width < 20ns
3.
I
CC
is dependent on output loading and cycle rates. The
specified value applies with the outputs unloaded, and
f = 1 Hz.
t
RC (MIN)
4.
This parameter is guaranteed but not tested.
5.
Test conditions as specified with the output loading as
shown in Fig. 1 unless otherwise noted.
6.
t
HZCE,
t
HZOE and
t
HZWE are specified with CL = 5pF
as in Fig. 2. Transition is measured 500mV typical from
steady state voltage, allowing for actual tester RC time
constant.
7.
At any given temperature and voltage condition,
t
HZCE
is less than
t
LZCE, and
t
HZWE is less than
t
LZWE.
8.
WE\ is HIGH for READ cycle.
9.
Device is continuously selected. Chip enables and
output enables are held in their active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11.
t
RC = Read Cycle Time.
12. Chip enable (CE\) and write enable (WE\) can initiate and
terminate a WRITE cycle.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
LOW Vcc DATA RETENTION WAVEFORM
123
123
123
123
1234
1234
1234
1234
DON'T CARE
UNDEFINED
AC TEST CONDITIONS
Input pulse levels....................................................Vss to 3V
Input rise and fall times.....................................................5ns
Input timing reference level.............................................1.5V
Output reference level......................................................1.5V
Output load.................................................See figures 1 & 2
DESCRIPTION SYMBOL
MIN
MAX
UNITS
NOTES
V
CC
for Retention Data
V
DR
2
--
V
V
CC
= 2V
I
CCDR
1.0 mA
V
CC
= 3V
2.0 mA
Chip Deselect to Data
Retention Time
t
CDR
0
--
ns 4
Operation Recovery Time
t
R
t
RC
ns
4, 11
Data Retention Current
CE\ > (V
CC
- 0.2V)
V
IN
> (V
CC
- 0.2V)
or < 0.2V
CONDITIONS
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123
123
123
123
123
1234
1234
1234
1234
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12
12
12
12
12
123
123
123
123
DATA RETENTION MODE
V
DR
> 2V
4.5V
4.5V
V
DR
t
CDR
t
R
V
IH
V
IL
V
CC
CE\
Fig. 2
OUTPUT LOAD
EQUIVALENT
Fig. 1
OUTPUT LOAD
EQUIVALENT
+5V
Q
255
30 pF
480
5 pF
+5V
Q
255
480
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