SRAM
MT5C6408
Austin Semiconductor, Inc.
MT5C6408
Rev. 3.0 2/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
FEATURES
High Speed: 12, 15, 20, 25, 35, 45, 55, and 70ns
Battery Backup: 2V data retention
High-performance, low-power CMOS double-metal
process
Single +5V (+10%) Power Supply
Easy memory expansion with CE1\ and CE2
All inputs and outputs are TTL compatible
OPTIONS
MARKING
Timing
12ns access
-12
15ns access
-15
20ns access
-20
25ns access
-25
35ns access
-35
45ns access
-45
55ns access
-55*
70ns access
-70*
Package(s)
Ceramic DIP (300 mil)
C
No. 108
Ceramic LCC
E C
No. 204
Ceramic Flatpack
F
No. 302
Operating Temperature Ranges
Industrial (-40
o
C to +85
o
C)
IT
Military (-55
o
C to +125
o
C)
XT
2V data retention/low power
L
*Electrical characteristics identical to those provided for the
45ns access devices.
PIN ASSIGNMENT
(Top View)
AVAILABLE AS MILITARY
SPECIFICATIONS
SMD 5962-38294
MIL-STD-883
28-Pin DIP (C)
(300 MIL)
28-Pin Flat Pack (F)
28-Pin LCC (EC)
GENERAL DESCRIPTION
The MT5C6408, 8K x 8 SRAM, employs high-speed,
low-power CMOS technology, eliminating the need for clocks
or refreshing. These SRAM's have equal access and cycle
times.
For flexibility in high-speed memory applications,
Austin Semiconductor offers dual chip enables (CE1\, CE2) and
output enable (OE\) capability. These enhancements can place
the outputs in High-Z for additional flexibility in system design.
Writing to these devices is accomplished when write
enable (WE\) and CE1\ inputs are both LOW and CE2 is HIGH.
Reading is accomplished when WE\ and CE2 remain HIGH and
CE1\ and OE\ go LOW. The device offers a reduced power
standby mode when disabled. This allows system designs to
achieve low standby power requirements.
These devices operate from a single +5V power sup-
ply and all inputs and outputs are fully TTL compatible.
8K x 8 SRAM
SRAM MEMORY ARRAY
For more products and information
please visit our web site at
www.austinsemiconductor.com
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
Vss
Vcc
WE\
CE2
A8
A9
A11
OE\
A10
CE1\
DQ8
DQ7
DQ6
DQ5
DQ4
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
Vss
Vcc
WE\
CE2
A8
A9
A11
OE\
A10
CE1\
DQ8
DQ7
DQ6
DQ5
DQ4
4 3 2 1 28 27 26
12 13 14 15 16 17 18
5
6
7
8
9
1 0
1 1
2 5
2 4
2 3
2 2
2 1
2 0
1 9
A 5
A 4
A 3
A 2
A 1
A 0
DQ0
A 8
A 9
A 1 1
OE\
A 1 0
CE1\
DQ7
DQ6
DQ5
DQ4
DQ3
Vss
DQ2
DQ1
A6
A7
A12
NC
Vcc
WE\
CE2\
SRAM
MT5C6408
Austin Semiconductor, Inc.
MT5C6408
Rev. 3.0 2/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
FUNCTIONAL BLOCK DIAGRAM
TRUTH TABLE
ROW DECODER
65,536-BIT
MEMORY ARRAY
I/O CONTROL
V
CC
Vss
DQ8
DQ1
CE1\
OE\
WE\
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
COLUMN DECODER
A
8
A
9
A
10
A
11
A
12
POWER
DOWN
CE2
MODE
CE1\
CE2
WE\
OE\
DQ
POWER
STANDBY
H
X
X
X
HIGH-Z
STANDBY
STANDBY
X
L
X
X
HIGH-Z
STANDBY
READ
L
H
H
L
Q
ACTIVE
READ
L
H
H
H
HIGH-Z
ACTIVE
WRITE
L
H
L
X
D
ACTIVE
SRAM
MT5C6408
Austin Semiconductor, Inc.
MT5C6408
Rev. 3.0 2/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
ABSOLUTE MAXIMUM RATINGS*
Voltage on any Input or DQ Relative to Vss........-0.5V to +7.0V
Voltage on Vcc Supply Relative to Vss.................-0.5V to +7.0V
Storage Temperature............................................-65
o
C to +150
o
C
Power Dissipation......................................................................1W
Max Junction Temperature..................................................+175
C
Lead Temperature (soldering 10 seconds)........................+260
o
C
Short Circuit Output Current................................................50mA
*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect reliability.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55
o
C < T
C
< 125
o
C; V
CC
= 5V +10%)
CAPACITANCE
DESCRIPTION CONDITIONS
SYMBOL
MIN
MAX
UNITS
NOTES
Input High (Logic 1) Voltage
V
IH
2.2 Vcc+0.5 V
1
Input Low (Logic 0) Voltage
V
IL
-0.5 0.8 V 1,
2
Input Leakage Current
0V
V
IN
Vcc
IL
I
-10 10
A
Output Leakage Current
Output(s) disabled
0V < V
OUT
< Vcc
IL
O
-10 10
A
Output High Voltage
I
OH
= -4.0mA
V
OH
2.4
V
1
Output Low Voltage
I
OL
= 8.0mA
V
OL
0.4
V 1
SYM
-12
-15
-20
-25
-35
-45
UNITS NOTES
I
cc
180
170
160
155
155
145
mA
3
I
SBTSP
40
40
40
40
40
40
mA
I
SBTLP
30
30
30
30
30
30
mA
I
SBCSP
20
20
20
20
20
20
mA
I
SBCLP
10
10
10
10
10
10
mA
Power Supply
Current: Standby
MAX
CE\ > V
IH
; All Other Inputs
< V
IL
or > V
IH
, V
CC
= MAX
f = 0 Hz
CE\ > (V
CC
-0.2); V
CC
= MAX
All Other Inputs < 0.2V
or > (V
CC
- 0.2V), f = 0 Hz
CONDITIONS
CE\ < V
IL
; V
CC
= MAX
f = MAX = 1/t
RC
(MIN)
Output Open
Power Supply
Current: Operating
PARAMETER
DESCRIPTION
CONDITIONS
SYM
MAX
UNITS
NOTES
Input Capacitance
C
I
6
pF
4
Output Capacitance
C
O
7
pF
4
T
A
= 25
o
C, f = 1MHz
Vcc = 5V
SRAM
MT5C6408
Austin Semiconductor, Inc.
MT5C6408
Rev. 3.0 2/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 5) (-55
o
C < T
C
< 125
o
C; V
CC
= 5V +10%)
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES
READ CYCLE
READ cycle time
t
RC
12
15
20
25
35
45
ns
Address access time
t
AA
12
15
20
25
35
45
ns
Chip Enable access time
t
ACE
12
15
20
25
35
45
ns
Output hold from address change
t
OH
2
0
0
0
3
3
ns
Chip Enable to output in Low-Z
t
LZCE
2
0
0
0
0
0
ns
7
Chip disable to output in High-Z
t
HZCE
7
10
15
15
15
25
ns
6, 7
Output Enable access time
t
AOE
8
12
15
15
15
20
ns
Output Enable to output in Low-Z
t
LZOE
0
0
0
0
0
0
ns
Output disable to output in High-Z
t
HZOE
7
10
15
15
30
40
ns
6
WRITE CYCLE
WRITE cycle time
t
WC
12
15
20
25
35
45
ns
Chip Enable to end of write
t
CW
10
13
15
20
30
40
ns
Address valid to end of write
t
AW
10
13
15
20
30
40
ns
Address setup time
t
AS
0
0
0
0
0
0
ns
Address hold from end of write
t
AH
0
0
0
0
0
0
ns
WRITE pulse width
t
WP
10
13
15
20
30
40
ns
Data setup time
t
DS
7
10
12
15
15
20
ns
Data hold time
t
DH
0
0
0
0
5
5
ns
Write disable to output in Low-Z
t
LZWE
2
0
0
0
0
0
ns
7
Write Enable to output in High-Z
t
HZWE
0
7
0
10
0
10
0
15
0
15
0
25
ns
6, 7
DESCRIPTION
-12
SYMBOL
-45
-35
-25
-20
-15
SRAM
MT5C6408
Austin Semiconductor, Inc.
MT5C6408
Rev. 3.0 2/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
AC TEST CONDITIONS
Input pulse levels ...................................... Vss to 3.0V
Input rise and fall times ......................................... 5ns
Input timing reference levels ................................ 1.5V
Output reference levels ....................................... 1.5V
Output load ................................. See Figures 1 and 2
NOTES
1.
All voltages referenced to V
SS
(GND).
2.
-3V for pulse width < 20ns
3.
I
CC
is dependent on output loading and cycle rates.
The specified value applies with the outputs
unloaded, and f = 1 Hz.
t
RC (MIN)
4.
This parameter is guaranteed but not tested.
5.
Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6.
t
LZCE
, t
LZWE
, t
LZOE
, t
HZCE
, t
HZOE
and t
HZWE
are specified with CL = 5pF as in Fig. 2. Transition is
measured 200mV typical from steady state voltage,
allowing for actual tester RC time constant.
7.
At any given temperature and voltage condition,
t
HZCE
is less than t
LZCE
, and t
HZWE
is less than t
LZWE
and
t
HZOE
is less than t
LZOE
.
8.
WE\ is HIGH for READ cycle.
9.
Device is continuously selected. Chip enables and
output enables are held in their active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11.
t
RC = Read Cycle Time.
12. CE2 timing is the same as CE1\ timing. The waveform is
inverted.
13. Chip enable (CE1\, CE2) and write enable (WE\) can
initiate and terminate a WRITE cycle.
Fig. 1 Output Load
Equivalent
Fig. 2 Output Load
Equivalent
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
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DON'T CARE
UNDEFINED
LOW Vcc DATA RETENTION WAVEFORM
DESCRIPTION
SYM
MIN
MAX
UNITS
NOTES
V
CC
for Retention Data
V
DR
2
---
V
Data Retention Current
CE\ > (V
CC
- 0.2V)
V
IN
> (V
CC
- 0.2V)
or < 0.2V
V
CC
= 2V
I
CCDR
300
A
Chip Deselect to Data
Retention Time
t
CDR
0
---
ns
4
Operation Recovery Time
t
R
t
RC
ns
4, 11
CONDITIONS
V
TH
= 1.73V
Q
167
30pF
V
TH
= 1.73V
Q
167
5pF
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DATA RETENTION MODE
V
DR
> 2V
4.5V
4.5V
V
DR
t
CDR
t
R
V
IH
V
IL
V
CC
CE\
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