AL5DS9xx9V

Preliminary Version 0.6

Amendments

(Since January 4, 2002)

02.01.04 Preliminary

version

0.1

02.01.10

Preliminary version 0.2:
(1) Modifies truth table and note descriptions in paragraph 7
(2) Modifies Absolute Maximum Ratings in paragraph 8.1
(3) Modifies C

and C

OUT

DC characteristics in paragraph 8.3

(4) Modifies Bank Select Pipelined Read and Counter Rest in Pipelined Mode timing

diagrams

02.04.09

Preliminary version 0.3:
(1) Modifies features in paragraph 2
(2) Modifies ordering information in paragraph 4.1
(3) Modifies AC characteristics in paragraph 8.5

02.05.07

Preliminary version 0.4:
(1) Modifies marking information in paragraphs 4 and 6
(2) Modifies the font type in paragraphs 6 and 9

02.09.25

Preliminary version 0.5:
(1) Split the datasheets to two parts: AL5DS9389V/9289V/9199V/9099V for 1M bit

density and other parts for less than 1M bit density

(2) Modifies the pin-out diagram in paragraph 6
(3) Modifies the truth table of address control in paragraph 7

02.11.01

Preliminary version 0.6:
Modifies the DC characteristics in paragraph 8.3

THE INFORMATION CONTAINED HEREIN IS SUBJECT TO CHANGE WIHOUT NOTICE.

AL5DS9xx9V

Preliminary Version 0.6

AL5DS9XX9V 3.3V Synchronous Dual-Port SRAM

Contents:

General Description ...............................................................................................4

Features ..................................................................................................................4

Applications ............................................................................................................5

Chip Information....................................................................................................5

4.1 Marking Information.............................................................................................................5

4.2 Ordering Information............................................................................................................5

Function Block Diagram .......................................................................................7

Pin-out Diagram.....................................................................................................8

Pin Definition and Description..............................................................................9

Electrical Characteristics.....................................................................................16

8.1 Absolute Maximum Ratings................................................................................................16

8.2 Recommended Operating Conditions ................................................................................16

8.3 DC Characteristics ...............................................................................................................17

8.4 AC Test Loads ......................................................................................................................18

8.5 AC Characteristics ...............................................................................................................18

Timing Diagrams .................................................................................................21

10 Mechanical Drawing ............................................................................................27

AL5DS9xx9V

Preliminary Version 0.6

1 General Description

A Dual-port RAM is a static RAM with a dual-ported cell. There are separate address, data and
control signals for each port to access a common SRAM array. A dual-port RAM is generally
classified with FIFOs as a "specialty" memory. They are most commonly used in communications
that include the exchange of data between processors, processes and systems.

Each port contains an internal counter for fast memory access applications. The initial address of the
internal counter is loaded with the port's Address Strobe (/ADS). It also allows the Counter Enable
(/CNTEN) to increment the internal counter on each Low to High transition of that port's clock
signal. The counter can address the entire memory array and will loop back to start (address 0). The
internal counter will be reset to zero while asserting Counter Reset (/CNTRST).

The AL5DS9xx9V is a high speed, 3.3V, synchronous, CMOS, dual-ported SRAM series. The
AL5DS9389V is configured as 64K x 18-bit, AL5DS9289V as 64K x 16-bit, AL5DS9199V as
128K x 9-bit and AL5DS9099V as 128K x 8-bit. All these parts support both Pipelined and Flow-
Through modes that are selected via the Pipe/FT pin. In the Pipelined mode, two cycles are required
to reactivate the data outputs. The AL5DS9xx9V series features dual Chip Enables that allow
simple depth and width expansion without external control logic.

All parts are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages. AL5DS9289V and
AL5DS9389V are also available in 128-pin TQFP packages.

2 Features

True dual ported memory cells
4 Flow-Through/Pipelined devices:
-- 64K x 18-bit organization (AL5DS9389V)
-- 64K x 16-bit organization (AL5DS9289V)
-- 128K x 9-bit organization (AL5DS9199V)
-- 128K x 8-bit organization (AL5DS9099V)
Supports byte write/read for 16/18 bit devices
Separate upper-byte and lower-byte controls for bus matching (only for 16/18 bit devices)
3 modes supported:

-Pipelined
-Flow-Through
-Burst

Counter enable and reset
Fast 100-MHz operation on both ports in Pipelined output mode
Supports depth and width expansion
0.25-micron CMOS for optimum speed/power
High speed clock to data access
3.3V low operating power
Pin-compatible and functionally equivalent to IDT or Cypress
Available in 100 or 128 pin TQFP

AL5DS9xx9V

Preliminary Version 0.6

3 Applications

Cellular Base Stations
Cellular Phones
Multi-protocol Routers
LAN/WAN Switches
PBXs
RAIDs (Storage Networks)
Set-top Boxes

Audio/Video Editing
Graphics Accelerators
Satellite Encoders
Cable Modems
Flight Simulators
High-end Printing Servers
Ultrasound Imaging

4 Chip Information

4.1 Marking Information

4.2 Ordering Information

Two packages are available for AL5DS9xx9V series Synchronous Dual-Port SRAM.

Part number

Speed

(MHz)

Package Power

Supply

Word

Length

Bus

Width

AL5DS9069V (A-100-PF100)

100

100 pin TQFP

3.3V 10%

16K 8

bits

AL5DS9069V (A-83-PF100)

100 pin TQFP

3.3V 10%

16K 8

bits

AL5DS9079V (A-100-PF100)

100

100 pin TQFP

3.3V 10%

32K 8

bits

AL5DS9079V (A-83-PF100)

100 pin TQFP

3.3V 10%

32K 8

bits

AL5DS9089V (A-100-PF100)

100

100 pin TQFP

3.3V 10%

64K 8

bits

AL5DS9089V (A-83-PF100)

100 pin TQFP

3.3V 10%

64K 8

bits

AL5DS9149V (A-100-PF100)

100

100 pin TQFP

3.3V 10%

4K 9

bits

AL5DS9149V (A-83-PF100)

100 pin TQFP

3.3V 10%

4K 9

bits

AL5DS9159V (A-100-PF100)

100

100 pin TQFP

3.3V 10%

8K 9

bits

AL5DS9xx9V

Preliminary Version 0.6

Part number

Speed

(MHz)

Package Power

Supply

Word

Length

Bus

Width

AL5DS9159V (A-83-PF100)

100 pin TQFP

3.3V 10%

8K 9

bits

AL5DS9169V (A-100-PF100)

100

100 pin TQFP

3.3V 10%

16K 9

bits

AL5DS9169V (A-83-PF100)

100 pin TQFP

3.3V 10%

16K 9

bits

AL5DS9179V (A-100-PF100)

100

100 pin TQFP

3.3V 10%

32K 9

bits

AL5DS9179V (A-83-PF100)

100 pin TQFP

3.3V 10%

32K 9

bits

AL5DS9189V (A-100-PF100)

100

100 pin TQFP

3.3V 10%

64K 9

bits

AL5DS9189V (A-83-PF100)

100 pin TQFP

3.3V 10%

64K 9

bits

AL5DS9269V (A-100-PF100)

100

100 pin TQFP

3.3V 10%

16K 16

bits

AL5DS9269V (A-83-PF100)

100 pin TQFP

3.3V 10%

16K 16

bits

AL5DS9279V (A-100-PF100)

100

100 pin TQFP

3.3V 10%

32K 16

bits

AL5DS9279V (A-83-PF100)

100 pin TQFP

3.3V 10%

32K 16

bits

AL5DS9269V (A-100-PF128)

100

128 pin TQFP

3.3V 10%

16K 16

bits

AL5DS9269V (A-83-PF128)

128 pin TQFP

3.3V 10%

16K 16

bits

AL5DS9279V (A-100-PF128)

100

128 pin TQFP

3.3V 10%

32K 16

bits

AL5DS9279V (A-83-PF128)

128 pin TQFP

3.3V 10%

32K 16

bits

AL5DS9349V (A-100-PF100)

100

100 pin TQFP

3.3V 10%

4K 18

bits

AL5DS9349V (A-83-PF100)

100 pin TQFP

3.3V 10%

4K 18

bits

AL5DS9359V (A-100-PF100)

100

100 pin TQFP

3.3V 10%

8K 18

bits

AL5DS9359V (A-83-PF100)

100 pin TQFP

3.3V 10%

8K 18

bits

AL5DS9369V (A-100-PF100)

100

100 pin TQFP

3.3V 10%

16K 18

bits

AL5DS9369V (A-83-PF100)

100 pin TQFP

3.3V 10%

16K 18

bits

AL5DS9379V (A-100-PF100)

100

100 pin TQFP

3.3V 10%

32K 18

bits

AL5DS9379V (A-83-PF100)

100 pin TQFP

3.3V 10%

32K 18

bits

AL5DS9379V (A-100-PF128)

100

128 pin TQFP

3.3V 10%

32K 18

bits

AL5DS9379V (A-83-PF128)

128 pin TQFP

3.3V 10%

32K 18

bits

AL5DS9xx9V

Preliminary Version 0.6

100 pin 14mm*14mm*1.4mm TQFP package-1:

100-Pin TQFP (Top View)

AL5DS9379V(A-100-PF100): 32K * 18

AL5DS9379V(A-83-PF100): 32K * 18

AL5DS9369V(A-100-PF100): 16K * 18

AL5DS9369V(A-83-PF100): 16K * 18
AL5DS9359V(A-100-PF100): 8K * 18

AL5DS9359V(A-83-PF100): 8K * 18

AL5DS9349V(A-100-PF100): 4K * 18

AL5DS9349V(A-83-PF100): 4K * 18

Note 1: pins 6 and 69 are NC for AL5DS9369V/59V/49V

Note 2: pins 5 and 70 are NC for AL5DS9359V/49V

Note 3: pins 4 and 71 are NC for AL5DS9349V

GND

ADS

I/O

GND

I/O

11R

PIPE/FT

R/W

I/O

16R

I/O

15R

I/O

14R

I/O

13R

I/O

12R

I/O

17R

CNTRST

10R

11R

14R

[NC]

13R

[NC]

12R

[NC]

10L

11L

[NC]A

12L

[NC]A

13L

[NC]A

14L

GND

I/O

16L

CNTRST

R/W

PIPE/FT

I/O

17L

I/O

14L

I/O

15L

I/O

12L

I/O

13L

I/O

10L

I/O

11L

AL5DS9xx9V

Preliminary Version 0.6

100 pin 14mm*14mm*1.4mm TQFP package-2:

100-Pin TQFP (Top View)

AL5DS9279V(A-100-PF100): 32K * 16

AL5DS9279V(A-83-PF100): 32K * 16

AL5DS9269V(A-100-PF100): 16K * 16

AL5DS9269V(A-83-PF100): 16K * 16

Note 1: pins 6 and 70 are NC for AL5DS9269V

10L

11L

12L

13L

[NC]A

14L

GND

CNTRST

R/W

PIPE/FT

I/O

14L

I/O

15L

I/O

12L

I/O

13L

I/O

10L

I/O

11L

GND

I/O

11R

PIPE/FT

R/W

I/O

15R

I/O

14R

I/O

13R

I/O

12R

CNTRST

10R

11R

12R

13R

14R

[NC]

GND

ADS

I/O

10R

AL5DS9xx9V

Preliminary Version 0.6

100 pin 14mm*14mm*1.4mm TQFP package-3:

100-Pin TQFP (Top View)

AL5DS9189V(A-100-PF100): 64K * 9

AL5DS9189V(A-83-PF100): 64K * 9

AL5DS9179V(A-100-PF100): 32K * 9

AL5DS9179V(A-83-PF100): 32K * 9

AL5DS9169V(A-100-PF100): 16K * 9

AL5DS9169V(A-83-PF100): 16K * 9
AL5DS9159V(A-100-PF100): 8K * 9

AL5DS9159V(A-83-PF100): 8K * 9

AL5DS9149V(A-100-PF100): 4K * 9

AL5DS9149V(A-83-PF100): 4K * 9

Note 1: pins 11 and 65 are NC for AL5DS9179V/69V/59V/49V

Note 2: pins 10 and 66 are NC for AL5DS9169V/59V/49V

Note 3: pins 9 and 67 are NC for AL5DS9159V/49V

Note 4: pins 8 and 68 are NC for AL5DS9149V

[NC]A

12L

[NC]A

13L

[NC]A

14L

CNTRST

R/W

PIPE/FT

[NC]A

15L

GND

PIPE/FT

R/W

CNTRST

10R

11R

12R

[NC]

13R

[NC]

CLK

CNT

CLK

CNT

GND

I/O

NC
NC

10L

11L

14R

[NC]

15R

[NC]

AL5DS9xx9V

Preliminary Version 0.6

100 pin 14mm*14mm*1.4mm TQFP package-4:

100-Pin TQFP (Top View)

AL5DS9089V(A-100-PF100): 64K * 8

AL5DS9089V(A-83-PF100): 64K * 8

AL5DS9079V(A-100-PF100): 32K * 8

AL5DS9079V(A-83-PF100): 32K * 8

AL5DS9069V(A-100-PF100): 16K * 8

AL5DS9069V(A-83-PF100): 16K * 8

Note 1: pins 11 and 65 are NC for AL5DS9079V/69V

Note 2: pins 10 and 66 are NC for AL5DS9069V

12L

13L

[NC]A

14L

CNTRST

R/W

PIPE/FT

[NC]A

15L

GND

PIPE/FT

R/W

CNTRST

10R

11R

12R

13R

CLK

CNT

CLK

CNT

GND

I/O

NC
NC

10L

11L

14R

[NC]

15R

[NC]

AL5DS9xx9V

Preliminary Version 0.6

7 Pin Definition and Description

The pin-out definitions are described as follows:

Left Port

Right Port

I/O

type

Description

16L

16R

Address

bus.

/ADS

Address Strobe. Low active. Asserting this signal LOW
while using an external address will access the port. /ADS
is only dependent of /CNTRST control signal.

/CNTEN

Counter Enable. Low active. When counter is enabled, the
internal address counter increments one on each rising
edge of CLK regardless of Chip Enable and Lower Byte
or Upper Byte Selects.

/CNTRST

Counter Reset. Low active. Resets the internal address
counter to zero. This signal is independent of all other
control signals.

/CE

, CE

/CE

, CE

Chip Enable. Low active for Chip Enable 0 and High
active for Chip Enable 1.

CLK

Clock

input.

I/O

~I/O

17L

I/O

~I/O

17R

I/O

Data bus.

/LB

Lower Byte Select. Low active. Enables the read and
write operations to the lower byte (I/O

-I/O

for 18 bit

devices, I/O

-I/O

for 16 bit devices) while asserting this

signal Low. Not available for 8/9 bit devices.

/UB

Upper Byte Select. Low active. Enables the read and write
operations to the upper byte (I/O

-I/O

for 18 bit devices,

I/O

-I/O

for 16 bit devices) while asserting this signal

Low. Not available for 8/9 bit devices.

/OE

Output Enable. Low active. Asynchronous input signal.

R/W

Read/Write Enable. High active for read operations and
Low active for write operations.

PIPE/FT

Pipelined and Flow-Through Mode Select. High active for
Pipelined mode and Low active for Flow-Through mode.

NC -

connection

Digital Power

Digital

power

GND DP

Digital

ground

Note: For I/O type, I, O, and DP indicate input, output, and digital power respectively.

AL5DS9xx9V

Preliminary Version 0.6

For 18 or 16 bit devices, the truth table of read/write and enable control is as follows:

/CE0 CE1 CLK R/W /UB /LB /OE Upper byte Lower byte

Note

X X X X X

H High-Z High-Z Outputs

disabled

L H

High-Z

Data output Read Lower byte only

L H

L Data output

High-Z

Read Upper byte only

L H

L Data output Data output Read both bytes

L H

High-Z

Data input Write to Lower byte

L H

H X Data input

High-Z

Write to Upper byte

L H

X Data input

Data input Write to both bytes

X X

H H X

High-Z

Both bytes disabled

H X

X X X

High-Z

Chip disabled (Note 2)

X L

X X X

High-Z

Chip disabled (Note 2)

Note 1: H, L, X, and denote V

, V

, Don't Care and Rising-Edge Trigger, respectively.

Note 2: For Pipelined mode, chip is disabled on the following clock cycle if /CE changes state.

For 9 or 8 bit devices, the truth table of read/write and enable control is as follows:

/CE0 CE1 CLK R/W /OE Data I/O

Note

X X X X H High-Z

Outputs

disabled

L H

L Data output Read operation

L H

L X Data

input Write

operation

H X

High-Z

Chip disabled (Note 2)

X L

High-Z

Chip disabled (Note 2)

Note 1: H, L, X, and denote V

, V

, Don't Care and Rising-Edge Trigger, respectively.

Note 2: For Pipelined mode, chip is disabled on the following clock cycle if /CE changes state.

The truth table of address counter control is as follows:

/CNTRST /ADS /CNTEN CLK

Address

input

address

Internal

address

Data I/O

Note

L X X

X X 0 Q

Reset internal address
counter to 0

H L X

X A

Load external address into
internal address counter

H H L

X A

P+1

Enable internal address
counter

H H L

X A

max

Enable internal address
counter (Note 4)

H H H

X A

Disable internal address
counter

Note 1: H, L, X, and denote V

, V

, Don't Care and Rising-Edge Trigger, respectively.

Note 2: Assuming /CE

, /UB, /LB, and /OE = V

and assuming CE

and R/W = V

AL5DS9xx9V

Preliminary Version 0.6

Note 3: Data I/O is configured in Flow-Through mode. For Pipelined mode, the data output will be

delayed by one cycle.

Note 4: Because the internal address counter will be larger than the maximum memory address, it

will not reset the internal address counter to 0 on the next clock cycle when the previous
internal address has encountered the maximum memory address. Therefore, the application
software should remember to load a new address into the internal address counter or to
invoke the /CNTRST signal to reset the internal address counter to 0 if the internal address
has encountered the maximum memory address.

8 Electrical Characteristics

8.1 Absolute Maximum Ratings

(Exceeding the rating can be harmful to product life. These are only user guidelines and are not
tested.)

Parameter

3.3V Rating

Unit

Supply Voltage

-0.3 ~ +3.8

Input Pin Voltage

-0.3 ~ +(V

+0.3) V

Output Current

-20 ~ +20

AMB

Ambient Op. Temperature

0 ~ +85

°C

stg

Storage Temperature

-40 ~ +125

°C

VSOL

Vapor

Phase

Soldering

Temperature (15 Sec.)

220 °C

8.2 Recommended Operating Conditions

3.3V Rating

Parameter

Min. Typical Max.

Unit

Supply

Voltage

+3.0

+3.3

+3.6

High Level Input Voltage

0.7 V

Low Level Input Voltage

0.3 V

AMB

Ambient Op. Temperature

+70

°C

AL5DS9xx9V

Preliminary Version 0.6

8.3 DC Characteristics

(

= 3.3V, GND=0V.

AMB

= 0 to 70°C) Note: Some parameters are guaranteed by

design only and are not production tested.

3.3V Rating

Parameter

Min. Typical Max.

Unit

Hi-level Input Voltage

0.7 V

- V

Lo-level Input Voltage

0.3 V

Hi-level Output Voltage (V

Min., I

= -4 mA)

2.4 - V

Lo-level Output Voltage (V

Min., I

= +4 mA)

- -

+0.4

Input Capacitance at V

=3.3V,

=25°C and f=1MHz

OUT

Output Capacitance at V

=3.3V,

=25°C and f=1MHz

Input Leakage Current (V

3.6V, V

= 0V~ V

)

Output Leakage Current (CE

, V

OUT

= 0V~ V

)

3-state Current (/OE = V

)

TBD

Operating Current (V

= Max.,

OUT

= 0 mA, outputs disabled)

TBD

SB1

Standby Current (Both ports are
TTL level inputs )

TBD

SB2

Standby Current (One port is TTL
level inputs )

TBD

SB3

Standby Current (Both ports are
CMOS level inputs )

TBD

SB4

Standby Current (One port is
CMOS level inputs )

TBD

AL5DS9xx9V

Preliminary Version 0.6

8.4 AC Test Loads

8.4.1 Normal Load (Load 1)

8.4.2 3-State Load (Load 2)

8.5 AC Characteristics

(

= 3.3V, GND=0V, T

AMB

= 0 to 70°C) Note: Some parameters are guaranteed by design

only and are not production tested.

3.3V Rating

-100 -83

Parameter

Min

Max Min Max

Unit

Address Control

ADDRS

Setup time for Address

3.5

ADDRH

Hold time for Address

INr

Rising time for all control inputs

INf

Falling time for all control inputs

ADSS

Setup time for /ADS

3.5

ADSH

Hold time for /ADS

CENS

Setup time for /CNTEN

3.5

4.5

CENH

Hold time for /CNTEN

CRSTS

Setup time for /CNTRST

3.5

CRSTH

Hold time for /CNTRST

AL5DS9xx9V

Preliminary Version 0.6

3.3V Rating

-100 -83

Parameter

Min

Max Min Max

Unit

I/O Control

INr

Rising time for all control inputs

INf

Falling time for all control inputs

CES

Setup time for Chip Enable

3.5

CEH

Hold time for Chip Enable

RWS

Setup time for R/W

3.5

RWH

Hold time for R/W

Setup time for /UB and /LB (not for 8/9 bit
devices)

3.5 4 ns

Hold time for /UB and /LB (not for 8/9 bit
devices)

0 0 ns

DAIS

Setup time for input data

3.5

DAIH

Hold time for input data

Output Enable to data valid

OELZ

Output Enable to Low Z [1]

OEHZ

Output Enable to High Z [1]

CDFT

Clock to data valid of Flow-Through

CDPIPE

Clock to data valid of Pipelined

6.5

7.5

CKLZ

Clock High to Low Z [1]

CKHZ

Clock High to High Z [1]

DAOH

Data output hold time after Clock High

CWDD

Write port Clock High to Read data delay

Clock

Frequency

Flow-Through

53 45

MHz

Clock cycle time of Flow-Through

Duty Factor for Flow-Through (t

FTH

* f

)

40 60 40 60 %

PIPE

Frequency

Pipelined

100 83

MHz

PIPE

Clock cycle time of Pipelined

AL5DS9xx9V

Preliminary Version 0.6

10 Mechanical Drawing

128 PIN 14mm*20mm*1.4mm TQFP:

MILLIMETER INCH

SYMBOL

MIN. NOM. MAX. MIN. NOM. MAX.

0.17

0.20

0.27 0.007 0.008 0.011

0.50 BSC.

0.020 BSC.

18.50 0.728

12.50 0.492

TOLERANCES OF FORM AND POSITION

aaa

0.20 0.008

bbb

0.20 0.008

ccc

0.08 0.003

ddd

0.08 0.003

NOTES:
1. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per

side. D1 and E1 are maximum plastic body size dimensions that include mold mismatch.

2. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall not

cause the lead width to exceed the maximum "b" dimension by more than 0.08mm. Dambar
cannot be located on the lower radius or the foot. Minimum space between protrusion and an
adjacent lead is 0.07mm (for 0.4mm and 0.5mm pitch packages).

AL5DS9xx9V

Preliminary Version 0.6

100 PIN 14mm*14mm*1.4mm TQFP:

MILLIMETER INCH

SYMBOL

MIN. NOM. MAX. MIN. NOM. MAX.

0.17

0.20

0.27 0.007 0.008 0.011

0.50 BSC.

0.020 BSC.

12.00 0.472

TOLERANCES OF FORM AND POSITION

aaa

0.20 0.008

bbb

0.20 0.008

ccc

0.08 0.003

ddd

0.08 0.003

NOTES:
1. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per

side. D1 and E1 are maximum plastic body size dimensions that include mold mismatch.

2. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall not

AL5DS9xx9V

Preliminary Version 0.6

CONTACT INFORMATION

Averlogic Technologies Corp.

4F, No. 514, Sec. 2, Cheng Kung Rd., Nei-Hu Dist., Taipei, Taiwan

Tel: +886 2-27915050

Fax: +886 2-27912132

E-mail:

sales@averlogic.com.tw

URL:

http://www.averlogic.com.tw

Averlogic Technologies, Inc.

90 Great Oaks Blvd. #204, San Jose, CA 95119,U.S.A.

Tel: 1 408 361-0400

Fax: 1 408 361-0404

E-mail:

sales@averlogic.com

URL:

http://www.averlogic.com

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