2DAA-F6R - Integrated Passive & Active Device
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
SOLDER
BUMPS
SILICON
DIE
Electrical Characteristics
Symbol
Minimum
Nominal
Maximum
Unit
(T
A
= 25 C unless otherwise noted)
Per TVS Diode Specification
Capacitance @ 0 V 1 MHz
C
120
150
180
pF
Rated Standoff Voltage
V
WM
5.0
V
Breakdown Voltage @ 1 mA
V
BR
6.0
V
Clamping Voltage
@ I
P
= 5 A t
P
= 8/20 s
V
C
9.5
V
@ I
PP
= 24 A t
P
= 8/20 s
V
C
11
V
Leakage Current @ 5 V
I
R
1
10
A
ESD Protection: IEC 61000-4-2
Contact Discharge
8
kV
Air Discharge
15
kV
Surge Protection: IEC 61000-4-5
8/20 s - Level 2 (Line - Gnd)
24
A
8/20 s - Level 3 (Line - Line)
24
A
Thermal Characteristics
(T
A
= 25 C unless otherwise noted)
Operating Temperature Range
T
J
-40 25 +85 C
Storage Temperature Range
T
STG
-55 25 +150 C
Peak Pulse Power (t
P
= 8/20 s) P
PP
300 W
General Information
Features
Lead free versions available
RoHS compliant (lead free version)*
ESD protection > 25k volts
Protects four unidirectional lines
Small SMT package
Applications
Cell phones
PDAs and notebooks
Digital cameras
MP3 players and GPS
Electrical & Thermal Characteristics
The 2DAA-F6R device provides ESD protection for the I/O
port of portable electronic devices such as cell phones,
modems and PDAs. The device incorporates four TVS
unidirectional diodes configured for interfacing to external
lines.
The ESD protection provided by the component enables
an I/O port to withstand a minimum 8 KV Contact / 15 KV
Air Discharge per the ESD test method specified in IEC
61000-4-2. The device measures 1.00 mm x 1.50 mm and
is available in a 6 bump Flip Chip package intended to be
mounted directly onto an FR4 printed circuit board. The
Flip Chip device meets typical thermal cycle and bend test
specifications without the use of an underfill material.
*RoHS COMPLIANT
VERSIONS
AVAILABLE
*RoHS Directive 2002/95/EC Jan 27 2003 including Annex
DIMENSIONS =
MILLIMETERS
(INCHES)
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
Mechanical Characteristics
2DAA-F6R - Integrated Passive & Active Device
A2
B2
A1
A3
B3
B1
0.490 - 0.524
(0.019 - 0.021)
0.965 - 1.015
(0.038 - 0.040)
0.414 - 0.424
(0.016 - 0.017)
1.475 - 1.525
(0.058 - 0.060)
0.180 - 0.280
(0.007 - 0.011)
0.50
(0.020)
0.50
(0.020)
0.15 - 0.005
(0.006 - 0.002)
0.180 - 0.280
(0.007 - 0.011)
DIA.
0.50
(0.020)
This is a silicon-based device and is packaged using chip scale packaging technology. Solder bumps, formed on the silicon die,
provide the interconnect medium from die to PCB. The bumps are arranged on the die in a regular grid formation. The grid pitch is
0.5 mm and the dimensions for the packaged device are shown below.
Reliability data is gathered on an ongoing basis for Bourns
Integrated Passive and Active Devices.
"Package level" testing of the integrity of the solder joint is carried out on an independent Daisy-Chain test device. A 25-Pin Daisy
Chain component is available from Bourns for this purpose (part number 2TAD-C25R). This is a 5 x 5 array featuring 0.5 mm pitch
solder bumps. The Distance to Neutral Point (DNP) on that component is larger than that of the 2DAA-F6R and is thus deemed
suitable for Thermal Cycle testing.
"Silicon level" reliability performance is based on similarity to other integrated passive CSP devices from Bourns.
Reliability Data
Overshoot and Clamping Voltage Response
ESD Test Pulse - 25 kilovolt, 1/30 ns (waveshape)
5 Volts per Division
-90,000 ns
-5
5
15
25
35
10,000 ns
110,000 ns
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
2DAA-F6R - Integrated Passive & Active Device
Block Diagram
GND
GND
EXT1
EXT4
EXT2
EXT3
The CSP device block diagram below includes the pin names and basic electrical
connections associated with each channel.
Please consult the "Bourns Design
Guide Using CSP" for notes on PCB
design and SMT Processing.
PCB Design and SMT Processing
How to Order
2 DAA - F6R __
__
Thinfilm
Model
Flip Chip
No. of Solder Bumps
Packaging Option
R = Tape and Reel
Packaged 5000 pcs. / 7 " reel
Terminations
LF = Sn/Ag/Cu (lead free)
Blank = Sn/Pb
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
2DAA-F6R - Integrated Passive & Active Device
The pin-out for the device is shown below with the bumps facing up.
Device Pin Out
The surface mount product is packaged in an 8 mm x 4 mm Tape and Reel format per EIA-481 standard.
Packaging
1
2
3
GND x 2
EXT4
B
A
EXT1
EXT3
EXT2
2.00 0.05
(.08 .002)
0.30 0.05
(.01 .002)
1.12 0.05
(.04 .002)
1.70 0.05
(.07 .002)
1.75 0.10
(.07 .004)
3.50 0.05
(.14 .002)
8.00 0.30
(.31 .01)
0.70 0.1
(0.03 0.004)
ORIENTATION
OF COMPONENT
IN POCKET
BACKSIDE FACING UP
TOP SIDE VIEW
(INTO COMPONENT POCKET)
0.3
(0.01)
4.00 0.10
(.16 .004)
4.00 0.10
(.16 .004)
0.25
(0.010)
TYP.
R
1.5 0.1/-0
(.06 .004/-0)
DIA.
MAX.
R
Pin Out
Function
Pin Out
Function
A1
EXT1
B1
EXT4
A2
GND
B2
GND
A3
EXT2
B3
EXT3
DIMENSIONS =
MILLIMETERS
(INCHES)
Asia-Pacific:
TEL +886- (0)2 25624117 FAX +886- (0)2 25624116
Europe:
TEL +41-41 768 5555 FAX +41-41 768 5510
The Americas: TEL +1-951 781-5492 FAX +1-951 781-5700
www.bourns.com
Reliable Electronic Solutions
COPYRIGHT 2004, BOURNS, INC. LITHO IN U.S.A. 08/04 e/IPA0411
2DAA-F6R REV. B, 1/05
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