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AL103
Revision 1.0
8 PORT LOW COST 10/100 SWITCH
Product Description
The AL103 is an eight-port 10/100 Mbit/s dual speed Ethernet switch. A low-cost Fast Ethernet
switch can be implemented using the AL103 with low-cost SGRAM. The AL103 also supports
VLAN and multiple port aggregation trunks.
Figure 1
System Block Diagram
Supports 8 10/100 Mbit/s MII ports
Capable of trunking up to 800 Mbit/s link
Trunk fail-over feature
Full- and half-duplex mode operation
Speed auto-negotiation through MDIO
Built-in storage of 1K MAC addresses
Design to utilize low-cost SGRAM
Serial EEPROM interface for low-cost
system configuration
Automatic source address learning
Secure mode traffic filtering
Broadcast storm control
Port monitoring support
IEEE 802.3x flow control for full-duplex
operation
Optional backpressure flow control sup-
port for half-duplex operation
Supports store-and-forward mode
switching
VLAN support
AL102A pin compatible
3.3V operation
Packaged in 256-pin PQFP
10/100 MAC
10/100 MAC
10/100 MAC
10/100 MAC
10/100 MAC
10/100 MAC
10/100 MAC
10/100 MAC
High Speed
Switch Fabric
Switch
Controller
Address
Control
Address
Table
Buffer
Manager
EEPROM
Interface
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This document contains proprietary information which shall not be reproduced, transferred
to other documents, or used for any other purpose without the prior written consent of Allayer
Communications.
Disclaimer
Allayer Communications reserves the right to make changes, without notice, in the
product(s) described or information contained herein in order to improve the design and/or
performance. Allayer Communications assumes no responsibility or liability for the use of any
of these products, conveys no license or title under any patent or copyright to these products, and
makes no representations or warranties that these products are free from patent or copyright
infringement unless otherwise specified.
Life Support Applications
Allayer Communications products are not designed for use in life support appliances, systems,
or devices where malfunctions can be reasonably expected to result in personal injury.
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Table of Contents
1.
AL103 Overview ..................................................................................................... 5
2.
Pin Descriptions....................................................................................................... 7
3.
Functional Description........................................................................................... 16
3.1
Data Reception............................................................................................... 16
3.1.1
Illegal Frame Length .............................................................................. 16
3.1.2
Long Frames .......................................................................................... 16
3.1.3
False Carrier Events ............................................................................... 16
3.1.4
Frame Filtering....................................................................................... 16
3.2
Frame Forwarding.......................................................................................... 17
3.2.1
Broadcast Storm Control........................................................................ 17
3.2.2
Frame Transmission ............................................................................... 18
3.2.3
Frame Generation................................................................................... 18
3.3
Half Duplex Mode Operation ........................................................................ 18
3.4
Secure Mode Operation ................................................................................. 18
3.5
Address Learning ........................................................................................... 19
3.5.1
Address Aging........................................................................................ 19
3.6
VLAN Support............................................................................................... 19
3.7
Port Aggregation (Trunking).......................................................................... 21
3.7.1
Load Balancing ...................................................................................... 21
3.7.2
Trunk Fail Over...................................................................................... 21
3.7.3
Trunk Port Assignment .......................................................................... 22
3.7.4
Port Based Trunk Load Balancing ......................................................... 22
3.7.5
MAC Based Load Balancing ................................................................. 24
3.8
Flow Control .................................................................................................. 25
3.8.1
Half Duplex Flow Control (Backpressure) ............................................ 25
3.8.2
Full Duplex Flow Control (802.3x) ....................................................... 26
3.9
Queue Management ....................................................................................... 26
3.10
Uplink Port..................................................................................................... 27
3.11
Port Monitoring.............................................................................................. 27
3.12
Media Independent Interface (MII) ............................................................... 28
3.13
PHY Management.......................................................................................... 28
3.13.1
PHY Management MDIO ...................................................................... 28
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3.13.2
PHY Management Master Mode ........................................................... 28
3.13.3
PHY Management Slave Mode.............................................................. 28
3.13.4
Non Auto-negotiation Mode .................................................................. 29
3.13.5
Other PHY Options ................................................................................ 29
3.14
EEPROM Interface ........................................................................................ 29
3.14.1
System Initialization .............................................................................. 29
3.14.2
Start and Stop Bit ................................................................................... 30
3.14.3
Write Cycle Operation ........................................................................... 30
3.14.4
Read Cycle Operation ............................................................................ 31
3.14.5
Reprogramming the EEPROM Configuration....................................... 31
3.14.6
EEPROM Map ....................................................................................... 32
3.15
SGRAM Interface .......................................................................................... 36
4.
Register Description .............................................................................................. 36
5.
Timing Requirements............................................................................................. 51
6.
Electrical Specifications ........................................................................................ 59
7.
AL103 Mechanical Data ........................................................................................ 60
8.
Appendix I (VLAN Mapping Worksheet) ............................................................. 61
9.
Appendix II (Port to Trunk Port Assignment Work Sheet) ................................... 62
10.
Appendix III (Suggested Memory Components)................................................... 63
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1. AL103 Overview
The AL103 provides eight 10/100 Mbit/s Ethernet ports. Each port supports both 10 and 100
Mbit/s data rate. The operation mode is auto-negotiated by the PHY. All ports are full-duplex
capable. The device also supports VLAN for workgroup and segment switching applications.
The AL103 also supports trunking applications. The chip provides two optional load-balancing
schemes, explicit and dynamic. With trunking, it is possible to group up to four full-duplex links
together to form a single 800 Mbit/s link.
Data received from the MAC interface is stored in the external memory buffer. The AL103 utilizes
cost effective SGRAM to provide 8-Mbit or 16-Mbit of buffer memory.
During transmission, the data is obtained from the buffer memory and routed to the destination
port's output buffer. If a collision occurs in half-duplex operation, the MAC control will back off
and retransmit in accordance to the IEEE 802.3 specification.
The AL103 provides two flow control methods. For half-duplex operations, an optional jamming
based flow control (known as backpressure) is available to prevent loss of data. With this method of
flow control, the switch will generate a jam signal when the receive buffer is full and the sending
station will not start to transmit until the line is clear. In the full-duplex mode, the AL103 utilizes
IEEE 802.3x as the flow control mechanism.
All ports support multiple MAC addresses. The switch chip supports 1K MAC addresses internally.
These MAC addresses are shared among all eight ports.
The initialization and configuration of the switch is programmed by an external EEPROM. Field
reconfiguration can be achieved by using a parallel interface to reprogram the EEPROM.
The AL103 also supports port based VLAN. The VLAN register set is used to configure the
destination ports for multicast and broadcast frames.
The device also provides two levels of security for intrusion protection. Security can be
implemented on a per port basis.
The AL103 operates only in the store and forward mode. The entire frame is checked for error and
any frames with errors are automatically filtered and will not be forwarded to the destination port.
The AL103 also features port monitoring and broadcast storm throttling.
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