Revision 1.0
May 2003
1
Preliminary
BSI
Very Low Power/Voltage CMOS SRAM
1M x 16 or 2M x 8 bit switchable
The BS616LV1625 is a high performance, very low power CMOS Static
Random Access Memory organized as 1,048,676 words by 16 bits or
2,097,152 bytes by 8 bits selectable by CIO pin and operates in a Vcc
range of 4.5V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 6.0uA at 5.0V/25
o
C and maximum access time of 55ns at 5.0V/85
o
C .
This device provide three control inputs and three states output drivers
for easy memory expansion.
The BS616LV1625 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV1625 is available in 48-pin 12mmx20mm TSOP1 package.
Vcc operation voltage : 4.5 ~ 5.5V
Very low power consumption :
Vcc = 5.0V C-grade: 113mA (@55ns) operating current
I -grade: 115mA (@55ns) operating current
C-grade: 90mA (@70ns) operating current
I -grade: 92mA (@70ns) operating current
6.0uA (Typ.) CMOS standby current
High speed access time :
-55 55ns
-70 70ns
Automatic power down when chip is deselected
Three state outputs and TTL compatible
DESCRIPTION
FEATURES
BLOCK DIAGRAM
Brilliance Semiconductor Inc
. reserves the right to modify document contents without notice.
PIN CONFIGURATIONS
R0201-BS616LV1625
Row
Decoder
Memory Array
4096 x 4096
Column I/O
Write Driver
Sense Amp
Column Decoder
Data
Buffer
Output
A1 A2 A3
Data
Buffer
Input
Control
Vss
Vdd
OE
WE
CE1
D15
D0
A11
A7
A17
A8
A12
A13
16(8)
16(8)
16(8)
16(8)
16(18)
256(512)
4096
4096
24
A10
A9
A0
A6
A4
A16
A14
Address
Input
Buffer
A18
Address Input Buffer
.
.
.
.
UB
.
.
.
.
LB
A15
CIO
CE2
(SAE)
A5
A19
BS616LV1625
Fully static operation
Data retention supply voltage as low as 1.5V
Easy expansion with CE1, CE2 and OE options
I/O Configuration x8/x16 selectable by CIO, LB and UB pin
PRODUCT FAMILY
POWER DISSIPATION
SPEED
(ns)
STANDBY
(I
CCSB1
, Max)
Operating
(I
CC
, Max)
PRODUCT FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
Vcc=5V
PKG TYPE
BS616LV1625TC
+0
O
C to +70
O
C
4.5V ~ 5.5V
55 / 70
28uA
113mA
90mA
TSOP1-48
(12mmx20mm)
BS616LV1625TI
-40
O
C to +85
O
C
4.5V ~ 5.5V
55 / 70
58uA
115mA
92mA
55ns : 4.5~5.5V
70ns : 4.5~5.5V
Vcc=5V
Vcc=5V
55ns
70ns
TSOP1-48
(12mmx20mm)
48-pin 12mmx20mm TSOP1 top view
24
25
1
48
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
/WE
CE2
NC
/UB
/LB
A18
A17
A7
A6
A5
A4
A3
A2
A1
9
10
13
16
17
A16
CIO
VSS
IO15 / SAE
IO7
IO14
IO6
IO13
IO5
IO12
IO4
VCC
IO11
IO3
IO10
IO2
IO9
IO1
IO8
IO0
/OE
VSS
/CE1
A0
47
BS616LV1625TC
BS616LV1625T I
37
27
46
Revision 1.0
May 2003
2
Preliminary
Name
Function
A0-A19 Address Input
These 20 address inputs select one of the 1,048,576 x 16-bit words in the RAM.
SAE Address Input
This address input incorporates with the above 20 address inputs select one of the
2,097,152 x 8-bit bytes in the RAM if the CIO is LOW. Don't use when CIO is HIGH.
CIO x8/x16 select input
This input selects the organization of the SRAM. 1,048,576 x 16-bit words
configuration is selected if CIO is HIGH. 2,097,152 x 8-bit bytes configuration is
selected if CIO is LOW.
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
LB and UB Data Byte Control Input
Lower byte and upper byte data input/output control pins. The chip is deselected when
both LB and UB pins are HIGH.
D0 - D15 Data Input/Output Ports
These 16 bi-directional ports are used to read data from or write data into the RAM.
Vcc
Power Supply
Gnd
Ground
PIN DESCRIPTIONS
BSI
BS616LV1625
R0201-BS616LV1625
Revision 1.0
May 2003
3
Preliminary
MODE CE1
CE2
OE
WE
CIO
LB
UB
SAE
D0~7
D8~15
VCC
Current
H X
X X
Fully Standby
X L
X X X
X X
X High-Z
High-Z I
CCSB
, I
CCSB1
Output
Disable
L H H H X X X X High-Z
High-Z
I
CC
L H
Dout High-Z
H L
High-Z Dout
Read from SRAM
( WORD mode )
L H L H H
L L
X
Dout Dout
I
CC
L H
Din
X
H L
X
Din
Write to SRAM
( WORD mode )
L H X L H
L L
X
Din Din
I
CC
Read from SRAM
( BYTE Mode )
L H L H L X X A-1 Dout High-Z
I
CC
Write to SRAM
( BYTE Mode )
L H X L L X X A-1 Din
X
I
CC
TRUTH TABLE
BSI
BS616LV1625
C
IN
Input
Capacitance
V
IN
=0V
6
pF
C
DQ
Input/Output
Capacitance
V
I/O
=0V
8
pF
RANGE
AMBIENT
TEMPERATURE
Vcc
Commercial 0
O
C to +70
O
C
4.5V ~ 5.5V
Industrial -40
O
C to +85
O
C
4.5V ~ 5.5V
ABSOLUTE MAXIMUM RATINGS
(1)
OPERATING RANGE
CAPACITANCE
(1)
(TA = 25
o
C, f = 1.0 MHz)
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
1. This parameter is guaranteed and not 100% tested.
SYMBOL
PARAMETER
RATING
UNITS
V
TERM
Terminal Voltage with
Respect to GND
-0.5 to
Vcc+0.5
V
T
BIAS
Temperature Under Bias
-40 to +85
O
C
T
STG
Storage Temperature
-60 to +150
O
C
P
T
Power Dissipation
1.0 W
I
OUT
DC Output Current
20
mA
R0201-BS616LV1625
PARAMETER
CONDITIONS
MAX.
UNIT
SYMBOL
Revision 1.0
May 2003
4
Preliminary
DC ELECTRICAL CHARACTERISTICS
( TA = -40
o
C to + 85
o
C )
BSI
BS616LV1625
R0201-BS616LV1625
1. Typical characteristics are at TA = 25
o
C. 2. Fmax = 1/t
RC
.
3. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
4. Icc
_Max.
is 113mA(@55ns) / 90mA(@70ns) during 0~70
o
C operation.
5. I
cc
s
B1
is 28uA at Vcc=5.0V and T
A
=70
o
C.
PARAMETER
NAME
PARAMETER
TEST CONDITIONS
MIN. TYP.
(1)
MAX.
UNITS
--
V
IL
Guaranteed Input Low
Voltage
(3)
Vcc=5V
-0.5
0.8
V
V
IH
Guaranteed Input High
Voltage
(3)
Vcc=5V
2.2
--
Vcc+0.3
V
I
IL
Input Leakage Current
Vcc = Max, V
IN
= 0V to Vcc
--
--
1
uA
I
LO
Output Leakage Current
Vcc = Max, CE1 = V
IH
, or CE2 =
V
iL
, or
OE = V
IH
, V
I/O
= 0V to Vcc
--
--
1
uA
V
OL
Output Low Voltage
Vcc = Max, I
OL
= 2mA
Vcc=5V
--
--
0.4
V
V
OH
Output High Voltage
Vcc = Min, I
OH
= -1mA
Vcc=5V
2.4
--
--
V
--
--
115
I
CC
Operating Power Supply
Current
CE1 = V
IL
and CE2 = V
IH
, I
DQ
= 0mA, F = Fmax
(2)
Vcc=5V
--
--
92
mA
I
CCSB
Standby Current-TTL
CE1 = V
IH
or CE2 = V
IL
, I
DQ
= 0mA
Vcc=5V
--
--
2.5
mA
I
CCSB1
Standby Current-CMOS
CE1
Vcc-0.2V, or
CE2
0.2V, V
IN
Vcc - 0.2V
or V
IN
0.2V
Vcc=5V
--
6.0
58
uA
(4)
(5)
55ns
70ns
Revision 1.0
May 2003
5
Preliminary
SYMBOL
PARAMETER
TEST CONDITIONS
MIN. TYP.
(1)
MAX.
UNITS
V
DR
Vcc for Data Retention
CE1 Vcc - 0.2V or CE2 0.2V or
LB Vcc - 0.2V and UB Vcc - 0.2V
V
IN
Vcc - 0.2V or V
IN
0.2V
1.5 -- --
V
I
CCDR
Data Retention Current
CE1 Vcc - 0.2V or CE2 0.2V or
LB Vcc - 0.2V and UB Vcc - 0.2V
V
IN
Vcc - 0.2V or V
IN
0.2V
-- 0.7 3.5
uA
t
CDR
Chip Deselect to Data
Retention Time
0 -- --
ns
t
R
Operation Recovery Time
See Retention Waveform
T
RC
(2)
-- --
ns
DATA RETENTION CHARACTERISTICS
( TA = -40
o
C to +85
o
C )
1. Vcc = 1.5V, T
A
= + 25
O
C
2. t
RC
= Read Cycle Time
3. I
cc
DR
(Max.) is 1.7uA at T
A
=70
O
C.
BSI
BS616LV1625
LOW V
CC
DATA RETENTION WAVEFORM (1)
( CE1 Controlled )
CE1
Data Retention Mode
Vcc
t
CDR
Vcc
t
R
V
IH
V
IH
Vcc
V
DR
1.5V
CE1 Vcc - 0.2V
LOW V
CC
DATA RETENTION WAVEFORM (2)
( CE2 Controlled )
CE2
Data Retention Mode
Vcc
t
CDR
Vcc
t
R
V
IL
V
IL
Vcc
V
DR
1.5V
CE2 0.2V
R0201-BS616LV1625
(3)
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