Revision 2.5
April 2002

R0201-BS616LV2013

Very Low Power/Voltage CMOS SRAM
128K X 16 bit

· Very low operation voltage : 2.4 ~ 3.6V
· Very low power consumption :

Vcc = 3.0V

C-grade: 20mA (Max.) operating current

I -grade: 25mA (Max.) operating current

0.1uA (Typ.) CMOS standby current

· High speed access time :

-70

70ns (Max.) at Vcc = 3.0V

-10

100ns (Max.) at Vcc = 3.0V

· Automatic power down when chip is deselected
· Three state outputs and TTL compatible
· Fully static operation
· Data retention supply voltage as low as 1.5V
· Easy expansion with CE and OE options
· I/O Configuration x8/x16 selectable by LB and UB pin

The BS616LV2013 is a high performance, very low power CMOS Static
Random Access Memory organized as 131,072 words by 16 bits and
operates from a wide range of 2.4V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.1uA and maximum access time of 70ns in 3V operation.
Easy memory expansion is provided by active LOW chip enable
(CE), active LOW output enable(OE) and three-state output drivers.
The BS616LV2013 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV2013 is available in DICE form, JEDEC standard 44-pin
TSOP Type II package , JEDEC standard 48-pin TSOP Type I package
and 48-ball BGA package.

DESCRIPTION

FEATURES

BLOCK DIAGRAM

PRODUCT FAMILY

PIN CONFIGURATIONS

Brilliance Semiconductor Inc

. reserves the right to modify document contents without notice.

BS616LV2013

48-ball BGA top view

POWER DISSIPATION

SPEED

( ns )

STANDBY

( I

CCSB1

, Max )

Operating

( I

, Max )

PRODUCT

FAMILY

OPERATING

TEMPERATURE

Vcc

RANGE

Vcc=3.0V

PKG TYPE

BS616LV2013DC

DICE

BS616LV2013EC

TSOP2-44

BS616LV2013TC

TSOP1-48

BS616LV2013AC

C to +70

2.4V ~3.6V

70/100

0.7uA

20mA

BGA-48-0608

BS616LV2013DI

DICE

BS616LV2013EI

TSOP2-44

BS616LV2013TI

TSOP1-48

BS616LV2013AI

-40

C to +85

2.4V ~ 3.6V

70/100

1.5uA

25mA

BGA-48-0608

BSI

Row

Decoder

Memory Array

1024 x 2048

Column I/O

Write Driver

Sense Amp

Column Decoder

Data

Buffer

Output

A3 A2 A1

Data

Buffer

Input

Control

Gnd

Vcc

CE2,CE

DQ15

DQ0

A16

A15

A13

128

2048

1024

A14
A12

A11

Address

Input

Buffer

A10

Address Input Buffer

.
.
.
.

A4
A3
A2
A1
A0

DQ0
DQ1
DQ2
DQ3
VCC

GND

DQ4
DQ5
DQ6
DQ7

WE
A16
A15
A14
A13
A12

A5
A6
A7
OE
UB
LB
DQ15
DQ14
DQ13
DQ12
GND
VCC
DQ11
DQ10
DQ9
DQ8
NC
A8
A9
A10
A11
NC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

BS616LV2013EC
BS616LV2013EI

D15

D14

VSS

VCC

N.C.

D13

A12

A14

D12

D11

D10

A11

A10

A13

A15

A16

N.C.

VSS

VCC

N.C.

A15

A14

A13

A12

A11

A10

/WE

CE2

/UB

/LB

A16

VSS

IO15

IO7

IO14

IO6

IO13

IO5

IO12

IO4

VCC

IO11

IO3

IO10

IO2

IO9

IO1

IO8

IO0

/OE

VSS

/CE

BS616LV2013TC
BS616LV2013TI

Revision 2.5
April 2002

R0201-BS616LV2013

PIN DESCRIPTIONS

BSI

BS616LV2013

Name

Function

A0-A16 Address Input

These 17 address inputs select one of the 131,072 x 16-bit words in the RAM.

CE Chip Enable 1 Input

WE Write Enable Input

The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.

OE Output Enable Input

The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.

LB and UB Data Byte Control Input

Lower byte and upper byte data input/output control pins.

DQ0 - DQ15 Data Input/Output
Ports

These 16 bi-directional ports are used to read data from or write data into the RAM.

Vcc

Power Supply

Gnd

Ground

TRUTH TABLE

CE2 Chip Enable 2 Input

CE is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.

(44L TSOP2 / 48B BGA

ignore

CE2

pin)

MODE

CE2

(1)

D0~D7

D8~D15

Vcc CURRENT

High Z

CCSB

, I

CCSB1

Not selected

(Power Down)

High Z

CCSB

, I

CCSB1

Output Disabled

High Z

Dout

High Z

Dout

Read

Dout

High Z

Din

Write

Din

1. 44L TSOP2 / 48B BGA ignore CE2 condition.

Revision 2.5
April 2002

PARAMETER

NAME

PARAMETER

TEST CONDITIONS

MIN. TYP.

(1)

MAX.

UNITS

Guaranteed Input Low
Voltage

(2)

Vcc=3.0V

-0.5 -- 0.8 V

Guaranteed Input High
Voltage

(2)

Vcc=3.0V

2.0 -- Vcc+0.2 V

Input Leakage Current

Vcc = Max, V

= 0V to Vcc

-- -- 1 uA

Output Leakage Current

Vcc = Max, CE = V

, or CE2 = V

(4)

or OE = V

I/O

= 0V to Vcc

-- -- 1 uA

Output Low Voltage

Vcc = Max, I

= 2mA

Vcc=3.0V

-- -- 0.4 V

Output High Voltage

Vcc = Min, I

= -1mA

Vcc=3.0V

2.4 -- -- V

Operating Power Supply
Current

CE = V

, CE2 = V

(4)

= 0mA, F = Fmax

(3)

Vcc=3.0V

-- -- 20 mA

CCSB

Standby

Current-TTL

CE = V

or CE2 = V

(4)

= 0mA

Vcc=3.0V

-- -- 1 mA

CCSB1

Standby

Current-CMOS

Vcc-0.2V

CE2

0.2V

(4)

Vcc - 0.2V or V

0.2V

Vcc=3.0V

-- 0.1 0.7 uA

R0201-BS616LV2013

SYMBOL

PARAMETER

TEST CONDITIONS

MIN. TYP.

(1)

MAX.

UNITS

Vcc for Data Retention

CE Vcc - 0.2V or CE2 0.2V

(3)

Vcc - 0.2V or V

0.2V

1.5 -- --

CCDR

Data Retention Current

CE Vcc - 0.2V or CE2 0.2V

(3)

Vcc - 0.2V or V

0.2V

-- 0.05 0.5

CDR

Chip Deselect to Data
Retention Time

0 -- --

Operation Recovery Time

See Retention Waveform

(2)

-- --

SYMBOL

PARAMETER

CONDITIONS

MAX.

UNIT

Input
Capacitance

=0V

Input/Output
Capacitance

I/O

=0V

RANGE

AMBIENT

TEMPERATURE

Vcc

Commercial

C to +70

2.4V

3.6V

Industrial

-40

C to +85

2.4V

3.6V

1. Typical characteristics are at TA = 25

2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/t

. 4. 44L TSOP2/ 48B BGA ignore CE2 condition.

DATA RETENTION CHARACTERISTICS

( TA = 0 to + 70

C )

1. Vcc = 1.5V, T

= + 25

2. t

= Read Cycle Time

3. 44L TSOP2/48B BGA ignore CE2 condition.

ABSOLUTE MAXIMUM RATINGS

(1)

OPERATING RANGE

CAPACITANCE

(1)

(TA = 25

C, f = 1.0 MHz)

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.

1. This parameter is guaranteed and not 100% tested.

DC ELECTRICAL CHARACTERISTICS

( TA = 0 to + 70

C )

SYMBOL

PARAMETER

RATING

UNITS

TERM

Terminal Voltage with
Respect to GND

-0.5 to

Vcc+0.5

BIAS

Temperature Under Bias

-40 to +125

STG

Storage Temperature

-60 to +150

Power Dissipation

1.0

OUT

DC Output Current

BSI

BS616LV2013

Revision 2.5
April 2002

R0201-BS616LV2013

JEDEC

PARAMETER

NAME

PARAMETER

NAME

DESCRIPTION

BS616LV2013-70

MIN. TYP. MAX.

BS616LV2013-10

MIN. TYP. MAX.

UNIT

AVAX

Read Cycle Time

100

AVQV

Address Access Time

100

ELQV

ACS1 , 2

Chip Select Access Time

(CE,CE2)

100

Data Byte Control Access Time

(LB,UB)

GLQV

Output Enable to Output Valid

E1LQX

CLZ

Chip Select to Output Low Z

(CE,CE2)

Data Byte Control to Output Low Z

(LB,UB)

GLQX

OLZ

Output Enable to Output in Low Z

EHQZ

CHZ

Chip Deselect to Output in High Z

(CE,CE2)

BDO

Data Byte Control to Output High Z

(LB,UB)

GHQZ

OHZ

Output Disable to Output in High Z

AXOX

Output Disable to Address Change

Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level

Vcc/0V
1V/ns

0.5Vcc

AC ELECTRICAL CHARACTERISTICS

( TA = 0 to + 70

C , Vcc = 3.0V )

READ CYCLE

( 44L TSOP2/48B BGA ignore CE2 condition)

AC TEST CONDITIONS

AC TEST LOADS AND WAVEFORMS

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

MUST BE
STEADY

MAY CHANGE
FROM H TO L

DON T CARE:
ANY CHANGE
PERMITTED

DOES NOT
APPLY

MUST BE
STEADY

WILL BE
CHANGE
FROM H TO L

CHANGE :
STATE
UNKNOWN

CENTER
LINE IS HIGH
IMPEDANCE
"OFF "STATE

MAY CHANGE
FROM L TO H

WILL BE
CHANGE
FROM L TO H

LOW V

DATA RETENTION WAVEFORM ( CE Controlled )

Data Retention Mode

Vcc

CDR

Vcc

Vcc

1.5V

CE Vcc - 0.2V

BSI

BS616LV2013

667

THEVENIN EQUIVALENT

ALL INPUT PULSES

10%

90%

Vcc

GND

5ns

90%

10%

1.73V

OUTPUT

FIGURE 2

3.3V

OUTPUT

INCLUDING
JIG AND
SCOPE

1269

1404

5PF

FIGURE 1B

3.3V

INCLUDING
JIG AND
SCOPE

1269

100PF

FIGURE 1A

1404

OUTPUT

(1)

1. t

is 35ns/50ns (@speed=70ns/100ns) with address toggle. ; .t

is 70ns/100ns (@speed=70ns/100ns) without address toggle.

NOTE :

Revision 2.5
April 2002

R0201-BS616LV2013

BSI

BS616LV2013

SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE1

(1,2,4)

OUT

ADDRESS

READ CYCLE2

(1,3,4)

CLZ

CHZ

(5,6)

OUT

(5,6)

ACS1

CE2

ACS2(6)

READ CYCLE3

(1,4)

OUT

LB,UB

ADDRESS

CLZ

(5,6)

ACS1

CHZ

(1,5,6)

OHZ

(5)

OLZ

BDO

CE2

ACS2(6)

NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = V

and CE2 = V

IH.

3. Address valid prior to or coincident with CE transition low.
4. OE = V

5. Transition is measured 500mV from steady state with C

= 5pF as shown in Figure 1B.

The parameter is guaranteed but not 100% tested.

6. 44L TSOP2/48B BGA ignore this parameters related to CE2 .

Revision 2.5
April 2002

JEDEC

PARAMETER

NAME

PARAMETER

NAME

DESCRIPTION

BS616LV2013-70

MIN. TYP. MAX.

BS616LV2013-10

MIN. TYP. MAX.

UNIT

AVAX

Write Cycle Time

100

E1LWH

Chip Select to End of Write

100

AVWL

Address Setup Time

AVWH

Address Valid to End of Write

100

WLWH

Write Pulse Width

WHAX

Write recovery Time

(CE,CE2,WE)

Date Byte Control to End of Write

(LB,UB)

WLQZ

WHZ

Write to Output in High Z

DVWH

Data to Write Time Overlap

WHDX

Data Hold from Write Time

GHQZ

OHZ

Output Disable to Output in High Z

WHOX

End of Write to Output Active

R0201-BS616LV2013

AC ELECTRICAL CHARACTERISTICS

( TA = 0 to + 70

C , Vcc = 3.0V )

WRITE CYCLE

( 44L TSOP2/ 48B BGA ignore CE2 condition)

BSI

BS616LV2013

SWITCHING WAVEFORMS (WRITE CYCLE)

WRITE CYCLE1

(1)

1. t

is 30ns/40ns (@speed=70ns/100ns) with address toggle. ; t

is 70ns/100ns (@speed=70ns/100ns) without address toggle.

(1)

NOTE :

(CE,CE2)

(3)

(11)

(2)

OHZ

(4,10)

(3)

OUT

ADDRESS

(5)

CE2

(5,12)

(5)

LB,UB

Revision 2.5
April 2002

R0201-BS616LV2013

BSI

BS616LV2013

NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE2, CE and WE low. All signals

must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.

3. T

is measured from the earlier of CE2 going low, or CE or WE going high at the end of write cycle.

4. During this period, DQ pins are in the output state so that the input signals of opposite phase

to the outputs must not be applied.

5. If the CE2 high transition or CE low transition occurs simultaneously with the WE low transitions or after the WE

transition, output remain in a high impedance state.

6. OE is continuously low (OE = V

7. D

OUT

is the same phase of write data of this write cycle.

8. D

OUT

is the read data of next address.

9. If CE2 is high or CE is low during this period, DQ pins are in the output state. Then the data input signals of

opposite phase to the outputs must not be applied to them.

10. Transition is measured 500mV from steady state with C

= 5pF as shown in Figure 1B.

The parameter is guaranteed but not 100% tested.

11. T

is measured from the later of CE2 going high or CE going low to the end of write.

12. 44L TSOP2/ 48B BGA ignore this parameters related to CE2 .

WRITE CYCLE2

(1,6)

(11)

(2)

WHZ

(4,10)

(3)

OUT

ADDRESS

(7)

(8)

(8,9)

CE2

LB,UB

(5)

(5,12)

Revision 2.5
April 2002

R0201-BS616LV2013

BSI

BS616LV2013

PACKAGE DIMENSIONS

SECTION A-A

BASE METAL

WITH PLATING

c c1

0.0236±0.006

0.020±0.004

0.004 ~ 0.006

0.004 ~ 0.008

0.008±0.001

0.009±0.002

0.0433±0.004

0°~ 8°

0.004 Max.

0.0315±0.004

0.708±0.008

0.472±0.004

0.645±0.004

0.039±0.002

0.004±0.002

"A"

Seating Plane

°
(2

)

°
(2

)

L1
y

SYMBOL

b1
c

UNIT

16.40±0.10

0.50±0.10

0.80±0.10

0.60±0.15

18.00±0.20

12.00±0.10

0°~ 8°

0.1 Max.

0.10 ~ 0.16

0.10 ~ 0.21

0.20±0.03

0.22±0.05

1.00±0.05

0.10±0.05

1.10±0.10

INCH

12°(2x)

"A" DETAIL VIEW

GAUGE PLANE

SEATING PLANE

12°(2x)

0.254

TSOP1-48PIN

48 mini-BGA (6 x 8)

VIEW A

1.4 Max.

1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.

BALL PITCH e = 0.75

8.0

6.0

3.75

5.25

NOTES:

PACKAGE DIMENSIONS (continued)

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: BS616LV2013-10

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: BS616LV2013-10