Revision 1.0
Jan. 2003
1
Preliminary
R0201-BS616LV2019
Very Low Power/Voltage CMOS SRAM
128K X 16 bit
Wide Vcc operation voltage : 2.4V ~ 3.6V
Very low power consumption :
Vcc = 3.0V C-grade: 23mA (@55ns) operating current
I -grade: 25mA (@55ns) operating current
C-grade: 15mA (@70ns) operating current
I -grade: 16mA (@70ns) operating current
0.3uA(Typ.) CMOS standby current
High speed access time :
-55 55ns (Max.) at Vcc = 2.7~3.6V / 85
o
C
-70 70ns (Max.) at Vcc = 2.4~3.6V / 85
o
C
Automatic power down when chip is deselected
Three state outputs and TTL compatible
Fully static operation
Data retention supply voltage as low as 1.5V
The BS616LV2019 is a high performance , very low power CMOS Static
Random Access Memory organized as 131,072 words by 16 bits and
operates from a wide range of 2.4V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.3uA at 3.0V /25
o
C and maximum access time of 55ns at 2.7V/ 85
o
C.
Easy memory expansion is provided by active LOW chip enable (CE),
active LOW output enable(OE) and three-state output drivers.
The BS616LV2019 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV2019 is available in DICE form , JEDEC standard 48-pin
TSOP Type I package and 48-ball BGA package.
DESCRIPTION
FEATURES
BLOCK DIAGRAM
PRODUCT FAMILY
PIN CONFIGURATIONS
Brilliance Semiconductor Inc
. reserves the right to modify document contents without notice.
BS616LV2019
48-ball BGA top view
SPEED
( ns )
STANDBY
( I
CCSB1
, Max )
Operating
( I
CC
, Max )
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
Vcc=3.0V
Vcc=3.0V
PKG TYPE
BS616LV2019DC
DICE
BS616LV2019TC
TSOP1-48
BS616LV2019AC
+0
O
C to +70
O
C
2.4V ~3.6V
55/70
3.0uA
15mA
BGA-48-0608
BS616LV2019DI
DICE
BS616LV2019TI
TSOP1-48
BS616LV2019AI
-40
O
C to +85
O
C
2.4V ~ 3.6V
55/70
5.0uA
25mA
BGA-48-0608
BSI
Row
Decoder
Memory Array
1024 x 2048
Column I/O
Write Driver
Sense Amp
Column Decoder
Data
Buffer
Output
A3 A2 A1
Data
Buffer
Input
Control
Gnd
Vcc
OE
WE
CE2,CE
DQ15
DQ0
A16
A5
A6
A7
A15
A13
16
16
16
16
14
128
2048
1024
20
A14
A12
A9
A4
A0
A11
A8
Address
Input
Buffer
A10
Address Input Buffer
.
.
.
.
UB
.
.
.
.
LB
G
H
F
E
D
C
B
A
1
2
3
4
5
6
D15
D14
VSS
D9
D8
LB
VCC
N.C.
A8
A9
D13
A12
A14
D12
D11
D10
A5
UB
OE
A3
A0
A11
A10
A13
A15
WE
D5
A16
A7
A6
D4
D3
D1
D7
D6
D2
A4
A1
A2
D0
N.C.
VSS
VCC
N.C.
CE
N.C.
N.C.
N.C.
24
25
1
48
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
/WE
CE2
NC
/UB
/LB
NC
NC
A7
A6
A5
A4
A3
A2
A1
9
10
13
16
17
A16
NC
VSS
IO15
IO7
IO14
IO6
IO13
IO5
IO12
IO4
VCC
IO11
IO3
IO10
IO2
IO9
IO1
IO8
IO0
/OE
VSS
/CE
A0
47
BS616LV2019TC
BS616LV2019TI
37
27
46
Easy expansion with CE and OE options
I/O Configuration x8/x16 selectable by LB and UB pin
23mA
16mA
55ns
70ns
POWER DISSIPATION
55ns: 2.7~3.6V
70ns: 2.4~3.6V
Revision 1.0
Jan. 2003
2
Preliminary
R0201-BS616LV2019
PIN DESCRIPTIONS
BSI
BS616LV2019
Name
Function
A0-A16 Address Input
These 17 address inputs select one of the 131,072 x 16-bit words in the RAM.
CE Chip Enable 1 Input
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
LB and UB Data Byte Control Input
Lower byte and upper byte data input/output control pins.
DQ0 - DQ15 Data Input/Output
Ports
These 16 bi-directional ports are used to read data from or write data into the RAM.
Vcc
Power Supply
Gnd
Ground
TRUTH TABLE
CE2 Chip Enable 2 Input
CE is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.
(48B BGA
ignore
CE2
pin)
1. 48B BGA ignore CE2 condition.
MODE
CE
CE2
(1)
WE
OE
LB
UB
D0~D7
D8~D15
Vcc CURRENT
H
X
X
X
X
X
High Z
High Z
I
CCSB
, I
CCSB1
Not selected
(Power Down)
X
L
X
X
X
X
High Z
High Z
I
CCSB
, I
CCSB1
Output Disabled
L
H
H
H
X
X
High Z
High Z
I
CC
L
L
Dout
Dout
I
CC
H
L
High Z
Dout
I
CC
Read
L
H
H
L
L
H
Dout
High Z
I
CC
L
L
Din
Din
I
CC
H
L
X
Din
I
CC
Write
L
H
L
X
L
H
Din
X
I
CC
I
CCSB
, I
CCSB1
X
X
X
X
H
H
High Z
High Z
Revision 1.0
Jan. 2003
3
Preliminary
R0201-BS616LV2019
SYMBOL
PARAMETER
TEST CONDITIONS
MIN. TYP.
(1)
MAX.
UNITS
V
DR
Vcc for Data Retention
CE Vcc - 0.2V or CE2 0.2V
(3)
V
IN
Vcc - 0.2V or V
IN
0.2V
1.5 -- --
V
I
CCDR
Data Retention Current
CE Vcc - 0.2V or CE2 0.2V
(3)
V
IN
Vcc - 0.2V or V
IN
0.2V
-- 0.1 1.0
uA
t
CDR
Chip Deselect to Data
Retention Time
0 -- --
ns
t
R
Operation Recovery Time
See Retention Waveform
T
RC
(2)
-- --
ns
SYMBOL
PARAMETER
CONDITIONS
MAX.
UNIT
C
IN
Input
Capacitance
V
IN
=0V
6
pF
C
DQ
Input/Output
Capacitance
V
I/O
=0V
8
pF
RANGE
AMBIENT
TEMPERATURE
Vcc
Commercial
0
O
C to +70
O
C
2.4V ~ 3.6V
Industrial
-40
O
C to +85
O
C
2.4V ~ 3.6V
1. Typical characteristics are at T
A
= 25
o
C.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/t
RC
.
4. 48B BGA ignore CE2 condition.
5.I
cc
s
B1_Max.
is 3.0uA at Vcc=3.0V and T
A
=70
o
C.
6. Icc
_Max.
is 23mA(@55ns) / 15mA(@70ns) at Vcc=3.0V/ 0~70
o
C.
DATA RETENTION CHARACTERISTICS
( TA = -40 to + 85
o
C )
1. Vcc = 1.5V, T
A
= + 25
O
C
2. t
RC
= Read Cycle Time
3. 48B BGA ignore CE2 condition.
4. Icc
DR
is 0.7uA at T
A
=70
o
C.
ABSOLUTE MAXIMUM RATINGS
(1)
OPERATING RANGE
CAPACITANCE
(1)
(TA = 25
o
C, f = 1.0 MHz)
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
1. This parameter is guaranteed and not 100% tested.
DC ELECTRICAL CHARACTERISTICS
( TA = -40 to + 85
o
C )
SYMBOL
PARAMETER
RATING
UNITS
V
TERM
Terminal Voltage with
Respect to GND
-0.5 to
Vcc+0.5
V
T
BIAS
Temperature Under Bias
-40 to +85
O
C
T
STG
Storage Temperature
-60 to +150
O
C
P
T
Power Dissipation
1.0
W
I
OUT
DC Output Current
20
mA
BSI
BS616LV2019
(4)
PARAMETER
NAME
PARAMETER
TEST CONDITIONS
MIN. TYP.
(1)
MAX.
UNITS
V
IL
Guaranteed Input Low
Voltage
(2)
Vcc =3.0V
-0.3
--
0.8
V
V
IH
Guaranteed Input High
Voltage
(2)
Vcc =3.0V
2.0
--
V
cc
+0.3
V
I
IL
Input Leakage Current
Vcc = Max, V
IN
= 0V to Vcc
-- -- 1 uA
I
LO
Output
Leakage
Current
Vcc = Max,CE = V
IH
or CE2
(4)
= V
IL
or OE = V
IH
,
V
I/O
= 0V to Vcc
-- -- 1 uA
V
OL
Output Low Voltage
Vcc = Max, I
OL
= 2.0mA
Vcc =3.0V
--
--
0.4
V
V
OH
Output High Voltage
Vcc = Min, I
OH
= -1.0mA
Vcc
=3.0V 2.4 -- -- V
70ns 16
I
CC
(6)
Operating Power Supply
Current
CE = V
IL
, CE2
(4)
= V
IH
I
DQ
= 0mA, F = Fmax
(3)
V
cc
=3.0V
55ns
-- --
25
mA
I
CCSB
Standby
Current-TTL
CE=V
IH
or CE2
(4)
=V
IL
I
DQ
= 0mA
Vcc =3.0V
--
--
0.5
mA
I
CCSB1
(5)
Standby
Current-CMOS
CE
V
cc
-0.2
V
,
CE2
(4)
0.2
V
,
V
IN
V
cc
-0.2
V
,
V
IN
0.2
V
Vcc =3.0V
--
0.3
5.0
uA
Revision 1.0
Jan. 2003
4
Preliminary
R0201-BS616LV2019
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
BS616LV2019-55
(Vcc = 2.7~3.6V)
BS616LV2019-70
(Vcc = 2.4~3.6V)
UNIT
t
AVAX
t
RC
Read Cycle Time
55
--
--
70
--
--
ns
t
AVQV
t
AA
Address Access Time
--
--
55
--
--
70
ns
t
ELQV
t
ACS1 , 2
Chip Select Access Time
(CE,CE2)
--
--
55
--
--
70
ns
t
BA
t
BA
Data Byte Control Access Time
(LB,UB)
--
--
30
--
--
35
ns
t
GLQV
t
OE
Output Enable to Output Valid
--
--
30
--
--
35
ns
t
E1LQX
t
CLZ
Chip Select to Output Low Z
(CE,CE2)
10
--
--
10
--
--
ns
t
BE
t
BE
Data Byte Control to Output Low Z
(LB,UB)
10
--
--
10
--
--
ns
t
GLQX
t
OLZ
Output Enable to Output in Low Z
5
--
--
5
--
--
ns
t
EHQZ
t
CHZ
Chip Deselect to Output in High Z
(CE,CE2)
0
--
30
0
--
35
ns
t
BDO
t
BDO
Data Byte Control to Output High Z
(LB,UB)
0
--
30
0
--
35
ns
t
GHQZ
t
OHZ
Output Disable to Output in High Z
0
--
25
0
--
30
ns
t
AXOX
t
OH
Output Disable to Address Change
10
--
--
10
--
--
ns
AC ELECTRICAL CHARACTERISTICS
( TA = -40 to + 85
o
C )
READ CYCLE
(48B BGA ignore CE2 condition)
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
"OFF "STATE
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
,
LOW V
CC
DATA RETENTION WAVEFORM ( CE Controlled )
CE
Data Retention Mode
Vcc
t
CDR
Vcc
t
R
V
IH
V
IH
Vcc
V
DR
1.5V
CE Vcc - 0.2V
BSI
BS616LV2019
(1)
1. t
BA
is 30ns/35ns (@speed=55ns/70ns) with address toggle. ; t
BA
is 55ns/70ns (@speed=55ns/70ns) without address toggle.
NOTE :
MIN. TYP. MAX.
MIN. TYP. MAX.
Input Pulse Levels
Vcc / 0V
Input Rise and Fall Times
1V/ns
Input and Output
Timing Reference Level
0.5Vcc
Output Load
C
L
= 100pF+1TTL
C
L
= 30pF+1TTL
Revision 1.0
Jan. 2003
5
Preliminary
R0201-BS616LV2019
BSI
BS616LV2019
READ CYCLE2
(1,3,4)
t
CLZ
t
CHZ
(5,6)
D
OUT
CE
(5,6)
t
ACS1
CE2
t
ACS2(6)
READ CYCLE3
(1,4)
t
OH
t
RC
t
OE
D
OUT
LB,UB
CE
OE
ADDRESS
t
CLZ
(5,6)
t
ACS1
t
CHZ
(1,5,6)
t
OHZ
(5)
t
OLZ
t
AA
t
BDO
t
BA
t
BE
CE2
t
ACS2(6)
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = V
IL
and CE2 = V
IH.
3. Address valid prior to or coincident with CE transition low.
4. OE = V
IL
.
5. The parameter is guaranteed but not 100% tested.
6. 48B BGA ignore this parameters related to CE2 .
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
t
RC
t
OH
t
AA
D
OUT
ADDRESS
t
OH
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